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13-4-2 LMI (Local memory interface)
DDR SDRAM (U301)
1) Feature
• Double data rate architecture: two data transfers per clock cycle
• Bidirectional data strobe (DQS) is transmitted and received with data, to be used
in capturing data at the receiver
• DQS is edge-aligned with data for reads and is center-aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to
both edges of DQS
• Burst Lengths: 2, 4, or 8
• CAS Latency: 2, 2.5, 3
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• RAS-lockout supported tRAP=tRCD
• 7.8µs Maximum Average Periodic Refresh Interval
• 2.5 V (SSTL_2 compatible) I/O
• VDDQ = 2.5 V ± 0.2 V
• VDD = 2.5 V ± 0.2 V
• P-TFBGA-60-11 package
• P-TSOPII-66-1 package
• RoHS Compliant Products1)
Samsung Electronics
Circuit Operating Descriptions
13-15
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