Vdd And Ce Timing At Power On; Table 10 Ce Timing - Epson RX4111CE Applications Manual

10.2. V and CE Timing at Power On
DD
When the power is turned to ON, use with CE=Low,"V
V
DD
CE
Figure 15 VDD, CE sequence

Table 10 CE Timing

Item
CE voltage when power is
turned to ON
CE = V V time when power
CL
is turned to ON
10.2. Restrictions on Access Operations During Power-on Initialization and Recovery from Backup
Because most of RTC registers are synchronized with the oscillation clock of the built-in crystal oscillator, the RTC does
not work normally without the integrated oscillator having stabilized. Please initialize the RTC at the time the power supply
voltage returns (VLF = 1) after the oscillation has stabilized (after oscillation start time t_
If intending to access the RTC after the main supply voltage returns, please note following points:
V
BAT
V
DD
During power-on initialization or power
supply voltage recovery after drop in clock
maintenance voltage
 Internal oscillation
(illustration)
FOUT
Figure 16 Oscillation start time chart (Power initial supply)
RX4111CE
ETM62E-02
1.6 V
t
CL
V
CL
Symbol
CE impressed voltage
V
CL
=1.6 V
until V
DD
Time to maintain CE = V
t
CL =1.6 V
until V
DD
V detect voltage +V
DD
Minimum voltage for clock maintenance V
Oscillation start time
(internal oscillation wait time)
30[ms]
After 30 ms progress, Confirm a state by VLF-bit
At the time of VLF=1: After a t_str wait, initial setting is necessary.
At the time of VLF=0: Register access is possible.
Seiko Epson Corporation
10. Interface timing when power ON / OFF
V in the diagram"as illustrated in the following timing chart.
CL
Condition
CL
DET
CLK  
t
_str
Access is enabled
Normal operation start
Specification Unit
0.3 Max. V
40 Min. ms
).
STA
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