Overview; Features - GE IMP2B Hardware Reference Manual

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1 • Overview
Available with the PowerPC MC7448 RISC CPU with integrated L2 cache, running at
up to 1.4 GHz, the IMP2B is based around a Marvell Discovery V (MV64560)
Integrated System Controller, which combines high performance system control
with multiple communication peripherals including high speed serial and dual
Ethernet ports, all on a single chip.

1.1 Features

8 IMP2B 3U cPCI Single Board Computer
Freescale MPC7448 processor clocked at up to 1.4 GHz
Marvell MV64560 bridge ('Discovery V')
Up to 1 GByte of DDR2-400 SDRAM with ECC (512 MBytes as standard)
Up to 256 MBytes of Spansion Flash memory (128 MBytes as standard)
128 KByte AutoStore NVRAM
32-bit/66 MHz CompactPCI interface (3.3 V signaling only)
64-bit/133 MHz PCI-X to PMC site (3.3 V signaling only)
1 to 49 PMC user rear I/O (1 to 64 if built in 'Peripheral Only' or 'Limited Host,
Full PMC User I/O' modes)
Two serial ports, software-configurable for RS232/RS422, asynchronous only
One 10/100/1000BaseT or two 10/100BaseT Ethernet channels, software selectable
Two USB 2.0 Host Ports (OHCI/EHCI compliant) with power controllers
4 bits of discrete digital I/O, each bit able to generate an interrupt
Four 32-bit timers
Six DMA channels including two XOR DMA engines for CRC32 calculation,
memory initialization and ECC error correction
Watchdog timer
Real-time clock
Elapsed time indicator
Publication No. IMP2B-0HH/5

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