Signal Integrity; Tdo Sampling Example At 12 Mhz; Differential Clock Buffer Example - Xilinx Platform Cable USB II Manual

X-Ref Target - Figure 28
Propagation delay from A to B (26 ns) captured directly at
the target represents 70% of the total propagation delay
seen by the cable (Figure 25).
TCK
TDO
Figure 28: TDO Sampling Example at 12 MHz (Analog Signals on Target System)

Signal Integrity

Platform Cable USB II uses high-slew-rate buffers to drive its output pins. Each buffer has a 30.1Ω series termination
resistor. Users should pay close attention to PCB layout to avoid transmission line effects. Visit the
Central website, and see XAPP361, Planning for High Speed XC9500XV Designs for detailed signal integrity assistance.
If the target system has only one programmable device, the 2-mm connector should be located as close as possible to the
target device. If there are multiple devices in a JTAG or slave-serial single chain on the target system, users should consider
buffering TCK_CCLK_SCK. Differential driver/receiver pairs provide excellent signal quality when the rules identified in
Figure 29 are followed. Buffering is essential if target devices are distributed over a large PCB area.
X-Ref Target - Figure 29
Each differential driver and/or receiver pair contributes approximately 5 ns of propagation delay. This delay is insignificant
when using 12 MHz or slower clock speeds.
DS593 (v1.2.1) March 17, 2011
TDO Sampling Point
SN65LVDS105
Four Differential
Drivers
SN65LVDS2 (2)
TCK_CCLK_SCK
1
4
Locate driver package adjacent to 2-mm connector
Figure 29: Differential Clock Buffer Example
www.xilinx.com
TDO Sampling Point
Route A & B traces for each differential
pair in parallel with equal length and
consistent spacing
Series Termination Resistor
(20Ω −30Ω)
TCK_CCLK_SCK1
TCK_CCLK_SCK4
Locate one receiver adacent
to each target device
DS593_29_021408
Platform Cable USB II
DS593_28_021408
Xilinx Signal Integrity
Four
Buffered
Clocks
27