Virtex-7 Xc7Vx690T-2Ffg1761C Fpga - Xilinx VC709 User Manual

VC709 Evaluation Board Features
Chapter 1:

Virtex-7 XC7VX690T-2FFG1761C FPGA

[Figure
The VC709 board is populated with the Virtex-7 XC7VX690T-2FFG1761C FPGA.
For further information on Virtex-7 FPGAs, see 7 Series FPGAs Overview (DS180)
FPGA Configuration
The VC709 board supports two of the five 7 series FPGA configuration modes:
•
•
Each configuration interface corresponds to one or more configuration modes and bus widths as
listed in
respectively as shown in
Note:
Evaluation Kit Master Answer Record (AR
X-Ref Target - Figure 1-3
The default mode setting is M[2:0] = 010, which selects Master BPI at board power-on. See
Configuration Options
Table 1-2: VC709 Board FPGA Configuration Modes
Configuration Mode
Master BPI
JTAG
For full details on configuring the FPGA, see 7 Series FPGAs Configuration User Guide (UG470)
[Ref
12
Send Feedback
1-2, callout 1]
Master BPI using the onboard linear BPI flash memory
JTAG using a type-A to micro-B USB cable for connecting the host PC to the VC709 board
configuration port
Table 1-2. The mode switches M2, M1, and M0 are on SW11 positions 3, 4, and 5
Figure 1-3.
To determine the FPGA type resident on the VC709 board, see the
ON Position = 1
Figure 1-3: SW11 Default Settings
for detailed information about the mode switch SW11.
SW13 DIP Switch
Settings (M[2:0])
3].
www.xilinx.com
51901).
1 2 3 4 5
OFF Position = 0
Bus Width
x8, x16
010
x1
101
[Ref 1].
Virtex-7 VC709
UG887_c1_03_083112
CCLK Direction
Output
Not applicable
VC709 Evaluation Board
UG887 (v1.6) March 11, 2019