Virtex-6 Xc6Vlx240T-1Ffg1156 Fpga; Configuration - Xilinx ML605 Hardware User's Manual

Chapter 1: ML605 Evaluation Board

1. Virtex-6 XC6VLX240T-1FFG1156 FPGA

A Virtex-6 XC6VLX240T-1FFG1156 FPGA is installed on the embedded development
board.
Keep-Out areas and drill holes are defined around the FPGA to support an Ironwood
Electronics SG-BGA-6046 FPGA socket.
See the Virtex-6 FPGA Data Sheet (DS152).

Configuration

The ML605 supports configuration in the following modes:
•
•
•
•
The ML605 supports Master BPI-Up, JTAG, and Slave SelectMAP. These are selected by
setting M[2:0] options 010, 101 and 110 shown in
Table 1-2: Virtex-6 FPGA Configuration Modes
Master Serial
Master SPI
Master BPI-Up
Master BPI-Down
Master SelectMAP
JTAG
Slave SelectMAP
Slave Serial
Notes:
1. The parallel configuration modes bus is auto-detected by the configuration logic.
2. In Master configuration mode, the CCLK pin is the clock source for the Virtex-6 FPGA internal
3. This is the default setting due to internal pull-up termination on mode pins.
For an overview on configuring the FPGA, see
Note:
M[2:0]=010, which selects Master BPI-Up at board power-on. Switch S1 position 4 must be OFF to
disable the System ACE controller from attempting to boot if a CF card is present.
See the Virtex-6 FPGA Configuration User Guide (UG360) for detailed configuration
information.
16
Send Feedback
Slave SelectMAP (using Platform Flash XL with the onboard 47 MHz oscillator)
Master BPI-Up (using Linear BPI Flash device)
JTAG (using the included USB-A to Mini-B cable)
JTAG (using System ACE CF and CompactFlash card)
Configuration Mode
(2)
(2)
(2)
(2)
(2)
(3)
configuration logic. The Virtex-6 FPGA CCLK output pin must be free from reflections to avoid
double-clocking the internal configuration logic. See the Virtex-6 FPGA Configuration User Guide for
more details. [Ref 5]
The mode switches are part of DIP switch S2. The default mode setting (see
[Ref 5]
www.xilinx.com
[Ref 4]
Table 1-2.
M[2:0] Bus Width
1
000
1
001
8, 16
010
8, 16
011
8, 16
100
1
101
8, 16, 32
110
1
111
Configuration
(1)
CCLK Direction
Output
Output
Output
Output
Output
Input (TCK)
Input
Input
Options.
Table A-34) is
ML605 Hardware User Guide
UG534 (v1.9) February 26, 2019