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5.3.2
Status Register (SR).............................................................................. 131
5.3.3
Status Register Clear Register (SRCR) ..................................................... 134
5.3.4
Interrupt Enable Register (IER)................................................................ 135
5.3.5
Memory Mode Register (MEMR)............................................................. 137
5.3.6
Display Mode Register (DSMR) .............................................................. 138
5.3.7
Rendering Mode Register (REMR) ........................................................... 142
5.3.8
Input Data Conversion Mode Register (IEMR)............................................ 144
5.4
Memory Control Registers................................................................................. 145
5.4.1
Display Size Registers X and Y (DSRX, DSRY) ........................................ 145
5.4.2
Display Start Address Registers 0 and 1 (DSAR0, DSAR1)........................... 146
5.4.3
Display List Start Address Registers H and L (DLSARH, DLSARL) .............. 147
5.4.4
Multi-Valued Source Area Start Address Register (SSAR)............................. 147
5.4.5
Work Area Start Address Register (WSAR) ................................................ 148
5.4.6
5.4.7
DMA Transfer Word Count Register (DWAWR)......................................... 149
5.5
Display Control Registers.................................................................................. 150
5.5.1
Display Window Registers (DSWR (HDS/HDE/VDS/VDE))......................... 150
5.5.2
Horizontal Sync Pulse Width Register (HSWR) .......................................... 151
5.5.3
Horizontal Scan Cycle Register (HCR)...................................................... 151
5.5.4
Vertical Start Position Register (VSPR).................................................... 152
5.5.5
Vertical Scan Cycle Register (VCR) ......................................................... 152
5.5.6
Display Off Output Registers H and L (DOORH, DOORL)........................... 153
5.5.7
Color detection registers H and L (CDERH, CDERL) .................................. 154
5.6
Rendering Control Registers............................................................................... 155
5.6.1
Command Status Registers H and L (CSTRH, CSTRL) ............................... 155
5.7
Input Control Registers..................................................................................... 156
5.7.1
5.7.2
Image Data Size Registers X and Y (IDSRX, IDSRY).................................. 157
5.7.3
Image Data Entry Register (IDER)............................................................ 157
5.8
Color Palette ................................................................................................... 158
5.8.1
Color Palette Registers H, L000-255 (CP000RH, L-CP255H, L) ................. 158
Section 6
6.1
CPU Clock and Q2-CLK0 ................................................................................. 161
6.2
Horizontal Display Start Position Register Value ................................................... 162
6.3
Notes on Data Transfer in YUV Mode.................................................................. 163
6.4
Software Reset Bit............................................................................................ 164
6.5
Note on Use of Auto Display Change Mode.......................................................... 165
6.6
Note on Color Palette Register Writes during Display............................................. 165
6.7
Notes on DMA Mode........................................................................................ 166
6.8
Power-On Sequence .......................................................................................... 167
6.9
Q2 Internal Buffers ........................................................................................... 168
6.10 Notes on Transition to Display Off Mode ............................................................. 170
..................................................................................... 161
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