Hitachi HD64465 Manuals

Manuals and User Guides for Hitachi HD64465. We have 1 Hitachi HD64465 manual available for free PDF download: User Manual

Hitachi HD64465 User Manual (410 pages)

Windows CE Intelligent Peripheral Controller

Brand: Hitachi | Category: Controller | Size: 1.68 MB

Table of Contents
7
Section 1 Features

20
- CPU Interface
  20
- PCMCIA Controller
  20
- AFE Interface
  20
- GPIO Function(Port Interrupt)
  20
- Interrupt Controller
  21
- Power Management
  21
- Timer
  21
- Keyboard Controller Interface
  21
- Uart
  21
- Printer Interface
  22
- Audio CODEC Interface
  22
- Irda
  22
- Clock Generator and PLL
  22
- USB Host Controller
  23
- 10-Bit ADC
  23
- Package
  23
Section 2 General Description

24
System Block Diagram

26
- Application Circuit
  26
- Section 3 System Block Diagram
  26
- System Block Diagram
  27
- Physical Address Space
  28
- HD64465 Memory Address
  29
- Pin Configuration
  30
  - HD64465BP Top View
    30
  - HD64465BP Bottom View
    31
  - HD64465BQ Top View
    32
  - HD64465BQ Bottom View
    33
Section 4 Pin Description

34
Tables

36
Section 5 Internal CPU Interface

60
Section 6 Power Management and System Configuration

70
Section 7 General Purpose I/O Port

86
Interrupt Controller (INTC)

98
- Overview
  98
  - Features
    98
  - Block Diagram
    99
  - Pin Configuration
    99
  - Register Configuration
    99
  - Figure 8.1 Block Diagram of the Interrupt Controller
    99
- Interrupt Sources
  100
  - On-Chip Module Interrupt
    100
  - Interrupt Exception Processing and Priority
    100
- NIRR: Interrupt Request Register
  101
- NIMR: Interrupt Mask Register
  103
- NITR: Interrupt Trigger Mode Register
  105
Section 9 Timer

108
Section 10 PC Card Controller (PCC)

128
Section 11 FIR Module

148
- Overview
  148
  - Features
    148
  - Functional Block Diagram of FIR
    149
  - Figure 11.1 Functional Block Diagram of FIR
    149
- FIR Controller Register Description
  151
  - UART Register of FIR Portion
    151
  - FIR Controller Register
    152
  - Table 11.1 Summary of FIR Controller Registers
    152
  - Register Description
    153
- FIR Transmit Operation
  172
- FIR Receive Operation
  173
- Example of Initialization and Programming Procedure for HP-SIR
  175
Section 12 UART

176
- Overview
  176
- Features
  176
- Serial Channel Register Description
  177
- Reset
  186
- Table 12.7 Reset Control of Register and Pinout Signals
  186
- Programming
  187
  - Programming Sequence
    187
- Software Reset
  187
- Clock Input Operation
  187
- FIFO Interrupt Mode Operation
  188
- Caution
  189
Section 13 Parallel Port

190
- Overview
  190
- Features
  190
- Parallel Port Register Description
  190
Section 14 Serial CODEC Interface

200
- Overview
  200
  - Features
    200
  - Block Diagram
    201
  - Figure 14.1 the Block Diagram of Serial CODEC Interface
    201
- Register Description
  202
- Function Description
  236
  - Internal Bus Interface
    236
  - Clock Generator
    236
  - CS4218 or CS4271 TX Controller
    237
  - CS4218 or CS4271 RX Controller
    237
  - AC97 TX Controller
    237
  - AC97 RX Controller
    238
  - Miscellaneous Function Block
    238
  - Data Structure of Memory in DMA Mode
    238
  - Figure 14.2 Data Transfer Scheme in DMA TX Mode
    238
- Program Flow
  239
- Figure 14.3 CS4218 or CS4271 TX Controller
  239
- Figure 14.4 CS4218 or CS4271 RX Controller
  239
- Figure 14.5 AC97 TX Controller
  240
- Figure 14.6 AC97 RX Controller
  241
- Figure 14.7 TX Flow in PIO Mode for CS4218 or CS4271
  242
- Figure 14.8 RX Flow in PIO Mode for CS4218 or CS4271
  243
- Figure 14.9 AC97 DMA Program Flow
  244
- Figure 14.10 Warm/Cold Reset Timing
  245
- Figure 14.11 Serial Data Setup, Hold and Output Delay Timing
  245
- Table 14.3 AC97 Timing
  246
Section 15 AFE Interface

248
- Overview
  248
  - Features
    248
  - Block Diagram
    249
  - Figure 15.1 AFE Interface Block Diagram
    249
- Register Description
  250
  - Table 15.1 Pin Function of AFE Interface Module
    250
  - Table 15.2 Registers of AFE Interface
    250
  - Control Register (CTR)
    251
  - Status Register (STR)
    252
  - Receive Data Register (RXDR)
    255
  - Transmit Data Buffers (TXDB0,1)
    255
  - Transmit Data Register (TXDR)
    255
  - Transmit Shift Register (TSFTR)
    255
  - Receive Data Buffers (RXDB0,1)
    256
  - Receive Shift Register (RSFTR)
    256
- Data Transfer
  256
  - Data Transmit
    256
  - Data Receive
    257
- Divider
  258
- Figure 15.2 Divider Configuration
  258
- External Chip Control Signal
  259
- Figure 15.3 HC1 Pin and Control Data Outputs
  259
- Interrupt
  260
- Figure 15.4 TDEI Output Timing
  260
- How to Use the Special Pin (RLYCNT, RING)
  261
  - How to Use the RLYCNT Pin
    261
  - How to Use the RING Pin
    261
  - Figure 15.5 RDFI Output Timing
    261
Section 16 Keyboard Controller Interface

262
Section 17 PS/2 Interface

268
- Overview
  268
- Pin Configuration
  268
- Registers Description
  268
- Block Diagram
  273
- Figure 17.1 PS/2 Keyboard/Mouse Interface Block Diagram
  273
- Operation
  274
  - Serial Data Format
    274
  - Software Operational Sequence
    274
  - Figure 17.2 Keyboard Serial Data Format
    274
  - Communication Protocol
    275
  - Table 17.2 Data Receive Timing Parameters
    276
  - Figure 17.3 Data Receive Timing
    276
- Caution
  277
- Table 17.3 Data Send Timing Parameters
  277
- Figure 17.4 Data Send Timing
  277
Section 18 USB Host Controller

278
- Introduction
  278
  - Device Description / Purpose
    278
  - Reference Information
    278
- Function Description
  279
  - System Architecture
    279
  - USB Host Controller
    280
  - Figure 18.1 USB States
    280
  - Figure 18.2 List Priority Within a USB Frame
    283
  - Figure 18-3. Example of Control/Bulk Service Ratio of 4:1
    284
  - Figure 18.4 List Service Flow
    287
  - Figure 18.5 Endpoint Descriptor Service Flow
    290
  - Figure 18.6 Endpoint Descriptor
    292
  - Figure 18.7 Transfer Description Service Flow
    293
  - Table 18.1 Example Calculation of R and Host Controller Action
    294
  - Table 18.2 ITD Packet Offset Location
    295
  - Table 18.3 Completion Codes
    298
  - Table 18.4 Dword0 GTD Fields
    301
  - Table 18.5 Dword0 ITD Fields
    301
  - Table 18.6 Dword1 GTD Fields
    301
  - Table 18.7 Dword1 ITD Fields
    302
  - Table 18.8 Dword2 Fields
    302
  - Table 18.9 Dword3 GTD Fields
    302
  - Table 18.10 Dword3 ITD Fields
    302
  - Table 18.11 Offset0 Field Description
    303
  - Table 18.12 List Processor Control Signals
    304
  - USB Interface
    312
  - Table 18.13 Transaction Control Information
    313
  - Table 18.14 PID Encoding
    314
  - Figure 18.8 Standard Token Packet Format
    315
  - Figure 18.9 SOF Token Packet Format
    315
  - Figure 18.10 Data Packet Format
    316
  - Figure 18.11 Handshake Packet Format
    316
  - Figure 18.12 Preamble Packet Format
    317
  - Figure 18.13 Serializer
    318
  - Figure 18.14 CRC Logic
    319
  - Figure 18.15 Non-Isochronous Bus Transaction
    323
  - Table 18.15 Bus Time-Out Periods
    324
  - Figure 18.16 Isochronous Bus Transaction
    324
  - Table 18.16 SIE EOF Timing Requirements
    325
  - Table 18.17 SIE Completion Status
    327
  - Table 18.18 in Transaction Error Response
    328
  - Table 18.19 out Transaction Error Response
    328
  - Table 18.20 Hub / Port Commands
    329
  - Table 18.21 Power Switching Configurations
    330
  - Power Management
    334
  - Register/Address Summary
    335
  - Table 18.22 HC Operational Register Summary
    335
  - Table 18.23 Hcrevision Register
    336
  - Table 18.24 Hccontrol Register
    337
  - Table 18.25 Hccommandstatus Register
    338
  - Table 18.26 Hcinterruptstatus Register
    339
  - Table 18.27 Hcinterrutpenable Register
    340
  - Table 18.28 Hcinterruptdisable Register
    341
  - Table 18.29 Hchcca Register
    342
  - Table 18.30 Hcperiodcurrented Register
    342
  - Table 18.31 Hccontrolheaded
    342
  - Table 18.32 Hccontrolcurrented Register
    343
  - Table 18.33 Hcbulkheaded Register
    343
  - Table 18.34 Hcbulkcurrented Register
    343
  - Table 18.35 Hcdonehead Register
    344
  - Table 18.36 Hcfminterval Register
    344
  - Table 18.37 Hcframeremaining Register
    345
  - Table 18.38 Hcfmnumberb Register
    345
  - Table 18.39 Hcperiodicstart Register
    345
  - Table 18.40 Hclsthreshold Register
    346
  - Table 18.41 Hcrhdescriptora Register
    347
  - Table 18.42 Hcrhdescriptorb Register
    348
  - Table 18.43 Hcrhstatus Register
    349
  - Table 18.44 Hcrhportstatus Register
    350
Section 19 A/D Converter

352
- Overview
  352
  - Features
    352
  - Block Diagram
    353
  - Input Pins
    353
  - Table 19.1 A/D Converter Pins
    353
  - Figure 19.1 A/D Converter Block Diagram
    353
  - Register Configuration
    354
  - Table 19.2 A/D Converter Registers
    354
- Register Descriptions
  355
- Operation
  358
- Interrupts
  363
- Table 19.4 A/D Conversion Time (Single Mode)
  363
- Figure 19.5 External Trigger Input Timing
  363
- Usage Notes
  364
- A/D Conversion Characteristics
  364
- Table 19.5 A/D Conversion Characteristics
  364
- Analog Input Pin Characteristics
  365
- Table 19.6 Analog Input Pin Characteristics
  365
- Figure 19.6 Analog Input Pin RC Equivalent Circuit
  365
Section 20 Electrical Characteristics

366
Section 21 Recommended Reflow Condition

384
Section 22 Package Information

386
- Figure 22.1 HD64465BP Package Dimensions
  386
- Figure 22.2 HD64465BQ Package Dimensions
  387
Section 23 Ordering Information

388
Appendix

390

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Hitachi HD64465 Manuals

Hitachi HD64465 User Manual (410 pages)

Table of Contents

Section 1 Features

Section 2 General Description

System Block Diagram

Section 4 Pin Description

Tables

Section 5 Internal CPU Interface

Figures

Section 6 Power Management and System Configuration

Section 7 General Purpose I/O Port

Interrupt Controller (INTC)

Section 9 Timer

Section 10 PC Card Controller (PCC)

Section 11 FIR Module

Section 12 UART

Section 13 Parallel Port

Section 14 Serial CODEC Interface

Section 15 AFE Interface

Section 16 Keyboard Controller Interface

Section 17 PS/2 Interface

Section 18 USB Host Controller

Section 19 A/D Converter

Section 20 Electrical Characteristics

Section 21 Recommended Reflow Condition

Section 22 Package Information

Section 23 Ordering Information

Appendix

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