Dma Transfer Word Count Register (Dwawr) - Hitachi HD64411 Q2 User Manual

The upper bits (A22 to A16) of the start address are set in the DMASH field in DMASRH, and the
lower bits (A15 to A1) in the DMASL field in DMASRL.
If the value of these registers is modified during a series of DMA operations from the time bits
DMA1 and DMA0 in SYSR are set to 10 by the CPU until they are cleared automatically by the
Q2, operation will be unstable.
When bits DMA1 and DMA0 are set to 11, the value in these registers is not referenced. Transfer
data passes via the image data entry register (IDER), is converted, and stored sequentially starting at
the data transfer start address indicated by the image data transfer start address register (ISAR).
The address (A22 to A1) indicated by the DMASH and DMASL fields is a word address.
Bits 15 to 7 of DMASRH and bit 0 of DMASRL are reserved. Only 0 should be written to these
bits (a read will return an undefined value).
The values of the DMASH field in DMASRH and the DMASL field in DMASRL are initialized
to all-0 by a reset.
5 . 4 . 7

DMA Transfer Word Count Register (DWAWR)

Bit: 15 14
— —
Initial value: — —
Read/Write: — —
The DMA transfer word count register (DWAWR) is a 16-bit readable/writable register that
specifies the number of words (1 word = 16 bits) to be transferred in DMA transfer.
If the value of this register is modified during a series of DMA operations from the time bits
DMA1 and DMA0 in SYSR are set to 10 or 11 by the CPU until they are cleared automatically
by the Q2, operation will be unstable.
When bits DMA1 and DMA0 are set to 11, the operation depends on the relative size of the value
set in image data size registers X and Y (IDSRX, IDSRY) and the value set in this register, as
follows. If the total data pixel number set in IDSRX and IDSRY is greater than the transfer word
count set in this register, YUV mode is not exited until the missing data has arrived. If smaller,
YUV mode is exited in the middle of the DMA transfer, and the remaining data is ignored.
Bits 15 and 14 of DMAWR are reserved. Only 0 should be written to these bits (a read will return
an undefined value).
The value of DMAWR bits DMAW is initialized to all-0 by a reset.
13 12 11 10 9
DMAW DMAW DMAW DMAW DMAW
0 0 0 0 0
R/W R/W R/W R/W R/W
8 7 6 5 4
DMAW DMAW DMAW DMAW DMAW
0 0 0 0 0
R/W R/W R/W R/W R/W
3 2 1 0
DMAW DMAW DMAW DMAW
0 0 0 0
R/W R/W R/W R/W
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