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MEMORY MAP
WMOD
— Watch Timer Mode Register
Bit
Identifier
Value
RESET
Read/Write
Bit Addressing
.7
.6
.5–.4
.3
.2
.1
.0
NOTE:
RESET sets WMOD.3 to the current input level of the subsystem clock, XT
WMOD.3 is set to logic one; if low, WMOD.3 is cleared to zero along with all the other bits in the WMOD
register.
4-32
7
6
.7
"0"
0
0
W
W
8
8
Enable/Disable Buzzer Output Bit
0
Disable buzzer (BUZ) signal output
1
Enable buzzer (BUZ) signal output
Bit 6
0
Always logic zero
Output Buzzer Frequency Selection Bits
0
0
2 kHz buzzer (BUZ) signal output
0
1
4 kHz buzzer (BUZ) signal output
1
0
8 kHz buzzer (BUZ) signal output
1
1
16 kHz buzzer (BUZ) signal output
XT
Input Level Control Bit
IN
Input level to XT
0
IN
Input level to XT
1
IN
Enable/Disable Watch Timer Bit
0
Disable watch timer and clear frequency dividing circuits
1
Enable watch timer
Watch Timer Speed Control Bit
0
Normal speed; set IRQW to 0.5 seconds
1
High-speed operation; set IRQW to 3.91 ms
Watch Timer Clock Selection Bit
0
Select the system clock (fxx/128) as the watch timer clock
1
Select a subsystem clock as the watch timer clock
5
4
.5
.4
.3
0
0
(note)
W
W
8
8
pin is low; 1-bit read-only addressable for test
pin is high; 1-bit read-only addressable for test
KS57C2308/P2308/C2316/P2316
3
2
1
.2
.1
0
0
R
W
W
1
8
8
. If the input level is high,
IN
F89H, F88H
0
.0
0
W
8
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