Samsung KS57C2308 Manual page 214

I/O PORTS
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PROGRAMMING TIP — Enabling and Disabling I/O Port Pull-Up Resistors
P2 and P3 are enabled to be pull-up resistors.
BITS
SMB
LD
LD
N-CHANNEL OPEN-DRAIN MODE REGISTER (PNE)
The n-channel open-drain mode register (PNE) is used to configure ports 4 and 5 to n-channel open-drain or as
push-pull outputs. When a bit in the PNE register is set to "1", the corresponding output pin is configured to
n-channel, open-drain; when set to "0", the output pin is configured to push-pull. The PNE register consists of an
8-bit register, PNE can be addressed by 8-bit write instructions only.
FD6H PNE4.3
FD7H PNE5.3
PIN ADDRESSING FOR OUTPUT PORT 8
The addresses for the port 8 1-bit output pin buffers are located in bank 1 of data memory instead of bank 15. To
address port 8 output pins, use the settings EMB = 1 and SMB = 1. The LCD mode register, LMOD is used to
control whether the pin address is used for LCD data output or for normal data output:
Table 10-5. LMOD.7 and LMOD.6 Setting for Port 8 Output Control
LMOD.7 LMOD.6
0 0
0 1
1 0
1 1
Each address in RAM bank 1 corresponds to a 4-bit register location. The LSB (bit 0) of the register location is
used as the port buffer for either LCD segment output or normal 1-bit data output. Locations that are unused for
LCD or port I/O can be used as normal data memory. After a
buffer are left undetermined.
Table 10-6 shows port 8 pin addresses and also the corresponding LCD segment names if the pins are used to
output LCD segment data. Pin addresses that are not used for LCD segment output can be used for normal 1-bit
output.
10-4
EMB
15
EA,#0CH
PUMOD,EA
PNE4.2 PNE4.1
PNE5.2 PNE5.1
LCD Output Segments
Seg 24–31
Seg 24–27
Seg 28–31
; enable the pull-up resistors of P2 and P3
PNE4.0
PNE5.0
–
, the values contained in the port 8 output
RESET
KS57C2308/P2308/C2316/P2316
1-Bit Output Pins
–
P8.4–P8.7 (Seg 28–31)
P8.0–P8.3 (Seg 24–27)
P8.0–P8.7 (Seg 24–31)