Samsung S5PV210 Hardware Design Manual
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Samsung S5PV210 Hardware Design Manual

Risc microprocessor
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S5PV210_HARDWARE DESING GUIDE REV 1.0
Hardware Design
Guide
S5PV210
RISC Microprocessor
FEB 8, 2010
REV 1.0

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Summary of Contents for Samsung S5PV210

  • Page 1 S5PV210_HARDWARE DESING GUIDE REV 1.0 Hardware Design Guide S5PV210 RISC Microprocessor FEB 8, 2010 REV 1.0...

  • Page 2: Important Notice

    Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes.
  • Page 3 S5PV210 RISC Microprocessor Hardware Design Guide, Revision 1.0 Copyright © 2010 Samsung Electronics Co., Ltd. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics.

  • Page 4: Revision History

    S5PV210_HARDWARE DESING GUIDE REV 1.0 Revision History Revision No Description of Change Refer to Author(s) Date - First release version Feb 08, 2010...

  • Page 5: Table Of Contents

    S5PV210_HARDWARE DESING GUIDE REV 1.0 Table of Contents OVERVIEW ...............................8 1.1. S5PV210 Pin Information...........................8 BALL NUMBER ASSIGNMENT ......................63 POWER ..............................71 3.1. Pin Power Domain............................71 3.2. Recommend Operating Conditions......................73 Circuit design without level shifter ......................75 3.3. Power On/Off Sequence ..........................76 3.4.
  • Page 6 S5PV210_HARDWARE DESING GUIDE REV 1.0 10.1. Overview..............................97 Signal Description ..........................97 10.2. UART ..............................98 Signal descriptoin ..........................98 11.1. IIC-BUS INTERFACE ..........................99 Pin Description .............................99 12.1. 12.2. Equation of the pull-up resistor value....................100 SPI ..............................101 Signal Description ..........................101 13.1. 13.2. EXTERNAL Loading Capacitance.....................101 SPI Maximum Speed ..........................101 13.3.
  • Page 7 S5PV210_HARDWARE DESING GUIDE REV 1.0 Restriction ............................117 20.3. MIPI DSI & CSI ..........................118 Signal Description ..........................118 21.1. 21.2. Design Guide............................119 TV ENCODER............................120 Signal Description ..........................120 22.1. HDMI..............................121 23.1. Overview..............................121 Signal Description ..........................121 23.2. Circuit Diagram Example ........................122 23.3. PCB Artwork Guide ..........................124 23.4.

  • Page 8: Overview

    S5PV210_HARDWARE DESING GUIDE REV 1.0 1. Overview 1.1. S5PV210 Pin Information Definitions Available Usage(AU) - G/E/W : GPIO & EINT & Wake up source - G/E : GPIO & EINT - G : GPIO - D : Dedicated signal - I : Internally connected to MCP and ball out...
  • Page 9 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_IO XuRXD[0] GPA0[0] I(L) UART_0_RXD Ret_IO XuTXD[0] GPA0[1] I(L) UART_0_TXD Ret_IO XuCTSn[0] GPA0[2] I(L) UART_0_CTSn Ret_IO XuRTSn[0]...
  • Page 10 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_UA for RP(Low Power UART_AUDIO_ XuTXD[2] GPA1[1] I(L) UART_2_TXD Audio)debugging Ret_UA XuRXD[3] GPA1[2] I(L) UART_3_RXD UART_2_CTSn Ret_UA...
  • Page 11 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down XspiCSn[1 Ret_IO GPB[5] I(L) SPI_1_nSS XspiMISO[ Ret_IO GPB[6] I(L) SPI_1_MISO XspiMOSI[ Ret_IO GPB[7] I(L) SPI_1_MOSI Ret_IO VDD_AUD...
  • Page 12 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Xpcm2FSYN Ret_IO GPC1[2] I(L) PCM_2_FSYNC LCD_FRM I2S_2_LRCK Ret_IO Xpcm2SIN GPC1[3] I(L) PCM_2_SIN I2S_2_SDI Ret_IO Xpcm2SOUT GPC1[4] I(L)
  • Page 13 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_IO For HDMI Xi2c1SCL GPD1[3] I(L) I2C1_SCL Ret_IO Xi2c2SDA GPD1[4] I(L) I2C2_SDA IEM_SCLK Ret_IO Xi2c2SCL GPD1[5] I(L)
  • Page 14 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down XciDATA[4 CAM_A_DATA[ Ret_IO GPE0[7] I(L) XciDATA[5 CAM_A_DATA[ Ret_IO GPE1[0] I(L) XciDATA[6 CAM_A_DATA[ Ret_IO GPE1[1] I(L) XciDATA[7 CAM_A_DATA[...
  • Page 15 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_IO XvVD[0] GPF0[4] I(L) LCD_VD[0] SYS_VD[0] VEN_DATA[0] Ret_IO XvVD[1] GPF0[5] I(L) LCD_VD[1] SYS_VD[1] VEN_DATA[1] Ret_IO XvVD[2] GPF0[6]...
  • Page 16 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down V656_DATA[3 Ret_IO XvVD[11] GPF1[7] I(L) LCD_VD[11] SYS_VD[11] V656_DATA[4 Ret_IO XvVD[12] GPF2[0] I(L) LCD_VD[12] SYS_VD[12] V656_DATA[5 Ret_IO XvVD[13]...
  • Page 17 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_IO XvVD[21] GPF3[1] I(L) LCD_VD[21] SYS_VD[21] Ret_IO XvVD[22] GPF3[2] I(L) LCD_VD[22] SYS_VD[22] Ret_IO XvVD[23] GPF3[3] I(L) LCD_VD[23]...
  • Page 18 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_MM Xmmc0DATA SD_0_DATA[2 GPG0[5] I(L) Ret_MM Xmmc0DATA SD_0_DATA[3 GPG0[6] I(L) Ret_MM Xmmc1CLK GPG1[0] I(L) SD_1_CLK Ret_MM Xmmc1CMD...
  • Page 19 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_MM Xmmc2CLK GPG2[0] I(L) SD_2_CLK Ret_MM Xmmc2CMD GPG2[1] I(L) SD_2_CMD Ret_MM Xmmc2CDn GPG2[2] I(L) SD_2_CDn Ret_MM Xmmc2DATA...
  • Page 20 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_MM Xmmc3CMD GPG3[1] I(L) SD_3_CMD Ret_MM Xmmc3CDn GPG3[2] I(L) SD_3_CDn Ret_MM Xmmc3DATA SD_3_DATA[0 GPG3[3] I(L) SD_2_DATA[4] Ret_MM...
  • Page 21 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down G/E/ No_Ret wakeup source XEINT[2] GPH0[2] I(L) G/E/ No_Ret wakeup source XEINT[3] GPH0[3] I(L) G/E/ No_Ret wakeup source...
  • Page 22 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down G/E/ No_Ret wakeup source XEINT[10] GPH1[2] I(L) G/E/ No_Ret wakeup source XEINT[11] GPH1[3] I(L) G/E/ No_Ret wakeup source...
  • Page 23 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down G/E/ No_Ret wakeup source XEINT[19] GPH2[3] I(L) KP_COL[3] G/E/ No_Ret wakeup source XEINT[20] GPH2[4] I(L) KP_COL[4] G/E/...
  • Page 24 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down G/E/ No_Ret wakeup source XEINT[27] GPH3[3] I(L) KP_ROW[3] G/E/ No_Ret wakeup source XEINT[28] GPH3[4] I(L) KP_ROW[4] G/E/...
  • Page 25 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_IO Cannot be used as GPIO Func Xi2s0LRCK GPI[2] O(L) I2S_0_LRCK PCM_0_FSYNC (sleep) & EINT Ret_IO Func Xi2s0SDI...
  • Page 26 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down CAM_B_DATA[ XmsmADDR[ Ret_CF GPJ0[2] I(L) MSM_ADDR[2] CF_ADDR[2] TS_CLK CAM_B_DATA[ Ret_CF XmsmADDR[ GPJ0[3] I(L) MSM_ADDR[3] CF_IORDY TS_SYNC Ret_CF...
  • Page 27 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_CF XmsmADDR[ MSM_ADDR[10 SROM_ADDR[1 CAM_B_HREF GPJ1[2] I(L) MHL_D3 Ret_CF XmsmADDR[ MSM_ADDR[11 SROM_ADDR[1 CAM_B_FIELD GPJ1[3] I(L) MHL_D4 CAM_B_CLKOU...
  • Page 28 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_CF XmsmDATA[ GPJ2[5] I(L) MSM_DATA[5] KP_COL[6] CF_DATA[5] MHL_D12 Ret_CF XmsmDATA[ GPJ2[6] I(L) MSM_DATA[6] KP_COL[7] CF_DATA[6] MHL_D13 Ret_CF...
  • Page 29 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_CF XmsmDATA[ MSM_DATA[13 GPJ3[5] I(L) KP_ROW[6] CF_DATA[13] MHL_D20 Ret_CF XmsmDATA[ MSM_DATA[14 GPJ3[6] I(L) KP_ROW[7] CF_DATA[14] MHL_D21 Ret_CF...
  • Page 30 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_aut Func Xm0CSn[2] MP0_1[2] O(H) SROM_CSn[2] NFCSn[0] Ret_aut Func Xm0CSn[3] MP0_1[3] O(H) SROM_CSn[3] NFCSn[1] Should be connected to Ret_aut Func...
  • Page 31 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_aut External pull up resistor is Func Xm0WAITn MP0_2[2] SROM_WAITn needed Ret_aut Xm0DATA_R Func EBI_DATA_RD MP0_2[3] O(L)
  • Page 32 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_aut Xm0FRnB[3 Func MP0_3[7] NF_RnB[3] Ret_aut Xm0ADDR[0 Func MP0_4[0] O(L) EBI_ADDR[0] Ret_aut Xm0ADDR[1 Func MP0_4[1] O(L) EBI_ADDR[1]...
  • Page 33 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_aut Xm0ADDR[7 Func MP0_4[7] O(L) EBI_ADDR[7] Ret_aut Xm0ADDR[8 Func MP0_5[0] O(L) EBI_ADDR[8] Ret_aut Xm0ADDR[9 Func MP0_5[1] O(L)
  • Page 34 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_aut Internally connected to Xm0DATA[0 Func MP0_6[0] O(L) EBI_DATA[0] OneNAND Ret_aut Xm0DATA[1 Func MP0_6[1] O(L) EBI_DATA[1] Ret_aut...
  • Page 35 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_aut Xm0DATA[8 Func MP0_7[0] O(L) EBI_DATA[8] Ret_aut Xm0DATA[9 Func MP0_7[1] O(L) EBI_DATA[9] Ret_aut Xm0DATA[1 Func EBI_DATA[10 MP0_7[2]...
  • Page 36 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down OneDRAM Ret_aut Xm1ADDR[1 Func I(X) MP1_0[1] O(L) LD0_ADDR[1] Ret_aut Xm1ADDR[2 Func I(X) MP1_0[2] O(L) LD0_ADDR[2] Ret_aut Xm1ADDR[3...
  • Page 37 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_aut Xm1ADDR[9 Func I(X) MP1_1[1] O(L) LD0_ADDR[9] Ret_aut Xm1ADDR[1 Func LD0_ADDR[10 I(X) MP1_1[2] O(L) Ret_aut Xm1ADDR[1 Func...
  • Page 38 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_aut Xm1DATA[2 Func I(X) MP1_2[2] LD0_DATA[2] Ret_aut Xm1DATA[3 Func I(X) MP1_2[3] LD0_DATA[3] Ret_aut Xm1DATA[4 Func I(X) MP1_2[4]...
  • Page 39 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_aut Xm1DATA[1 Func LD0_DATA[10 I(X) MP1_3[2] Ret_aut Xm1DATA[1 Func LD0_DATA[11 I(X) MP1_3[3] Ret_aut Xm1DATA[1 Func LD0_DATA[12 I(X)
  • Page 40 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_aut Xm1DATA[1 Func LD0_DATA[19 I(X) MP1_4[3] Ret_aut Xm1DATA[2 Func LD0_DATA[20 I(X) MP1_4[4] Ret_aut Xm1DATA[2 Func LD0_DATA[21 I(X)
  • Page 41 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_aut Xm1DATA[2 Func LD0_DATA[27 I(X) MP1_5[3] Ret_aut Xm1DATA[2 Func LD0_DATA[28 I(X) MP1_5[4] Ret_aut Xm1DATA[2 Func LD0_DATA[29 I(X)
  • Page 42 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_aut Xm1DQSn[0 Func I(X) MP1_6[4] LD0_DQSn[0] Ret_aut Xm1DQSn[1 Func I(X) MP1_6[5] LD0_DQSn[1] Ret_aut Xm1DQSn[2 Func I(X) MP1_6[6]...
  • Page 43 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_aut Func I(X) Xm1CKE[0] MP1_7[4] O(L) LD0_CKE[0] Ret_aut Func I(X) Xm1CKE[1] MP1_7[5] O(L) LD0_CKE[1] Ret_aut Func I(X)
  • Page 44 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_aut Internally connnected to Xm2ADDR[0 Func I(X) VDD_M2 MP2_0[0] O(L) LD1_ADDR[0] mDDR Ret_aut Xm2ADDR[1 Func I(X) MP2_0[1]...
  • Page 45 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_aut Xm2ADDR[8 Func I(X) MP2_1[0] O(L) LD1_ADDR[8] Ret_aut Xm2ADDR[9 Func I(X) MP2_1[1] O(L) LD1_ADDR[9] Ret_aut Xm2ADDR[1 Func...
  • Page 46 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_aut Xm2DATA[1 Func I(X) MP2_2[1] LD1_DATA[1] Ret_aut Xm2DATA[2 Func I(X) MP2_2[2] LD1_DATA[2] Ret_aut Xm2DATA[3 Func I(X) MP2_2[3]...
  • Page 47 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_aut Xm2DATA[9 Func I(X) MP2_3[1] LD1_DATA[9] Ret_aut Xm2DATA[1 Func LD1_DATA[10 I(X) MP2_3[2] Ret_aut Xm2DATA[1 Func LD1_DATA[11 I(X)
  • Page 48 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_aut Xm2DATA[1 Func LD1_DATA[18 I(X) MP2_4[2] Ret_aut Xm2DATA[1 Func LD1_DATA[19 I(X) MP2_4[3] Ret_aut Xm2DATA[2 Func LD1_DATA[20 I(X)
  • Page 49 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_aut Xm2DATA[2 Func LD1_DATA[26 I(X) MP2_5[2] Ret_aut Xm2DATA[2 Func LD1_DATA[27 I(X) MP2_5[3] Ret_aut Xm2DATA[2 Func LD1_DATA[28 I(X)
  • Page 50 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_aut Func I(X) Xm2DQS[3] MP2_6[3] LD1_DQS[3] Ret_aut Xm2DQSn[0 Func I(X) MP2_6[4] LD1_DQSn[0] Ret_aut Xm2DQSn[1 Func I(X) MP2_6[5]...
  • Page 51 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_aut Func I(X) Xm2DQM[3] MP2_7[3] O(L) LD1_DQM[3] Ret_aut Func I(X) Xm2CKE[0] MP2_7[4] O(L) LD1_CKE[0] Ret_aut Func I(X)
  • Page 52 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Ret_aut Func I(X) Xm2WEn MP2_8[4] O(H) LD1_WEn Ret_aut Internally connected to Pd VDD_SYS0 XjTRSTn ETC0[0] I(L) XjTRSTn...
  • Page 53 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Externally should be Ret_aut connected to pull down XjDBGSEL ETC0[5] XjDBGSEL resistor or GND No_Ret Booting option XOM[0]...
  • Page 54 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down mDDR: 'Low', DDR2 & LPDDR2 : 'High'. Should Ret_IO XDDR2SEL ETC1[6] XDDR2_SEL connect to pull down or No_Ret XPWRRGTON ETC1[7]...
  • Page 55 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down Charge pump enable XuhostPWR Ret_IO ETC2[6] O(L) XuhostPWREN signal XuhostOVE XuhostOVERC Ret_IO ETC2[7] RCUR -14pF external cap(each No_Ret XrtcXTI...
  • Page 56 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down XadcAIN[2 ANALOG[2 AIN[2] XadcAIN[3 ANALOG[3 AIN[3] XadcAIN[4 ANALOG[4 AIN[4] XadcAIN[5 ANALOG[5 AIN[5] XadcAIN[6 ANALOG[6 AIN[6] XadcAIN[7 ANALOG[7...
  • Page 57 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down ANALOG[1 75ohm pull-down XdacOUT XdacOUT ANALOG[1 1.2Kohm/1% pull-down XdacIREF XdacIREF VDD_DAC ANALOG[1 100nF GND tie XdacVREF XdacVREF ANALOG[1...
  • Page 58 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down ANALOG[2 XhdmiTX2N HDMI_TX2N ANALOG[2 XhdmiTXCP HDMI_TXCP ANALOG[2 XhdmiTXCN HDMI_TXCN ANALOG[2 4.6Kohm 1% pull-down XhdmiREXT HDMI_REXT ANALOG[2 -14pF external cap(each...
  • Page 59 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down ANALOG[3 XmipiMDP2 MIPI_MDP_2 ANALOG[3 XmipiMDP3 MIPI_MDP_3 ANALOG[3 XmipiMDN0 MIPI_MDN_0 ANALOG[3 XmipiMDN1 MIPI_MDN_1 ANALOG[3 XmipiMDN2 MIPI_MDN_2 ANALOG[3 XmipiMDN3...
  • Page 60 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down ANALOG[3 XmipiSDP3 MIPI_SDP_3 ANALOG[4 XmipiSDN0 MIPI_SDN_0 ANALOG[4 XmipiSDN1 MIPI_SDN_1 ANALOG[4 XmipiSDN2 MIPI_SDN_2 ANALOG[4 XmipiSDN3 MIPI_SDN_3 XmipiMDPC ANALOG[4...
  • Page 61 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down XmipiSDNC ANALOG[4 MIPI_CLK_RX XmipiVREG ANALOG[4 MIPI_Reg_ca 2nF GND tie _0P4V ANALOG[4 XuotgDP XuotgDP VDD_UOTG ANALOG[5 44.2ohm/1% pull-down XuotgREXT...
  • Page 62 S5PV210_HARDWARE DESING GUIDE REV 1.0 GPIO Rese Reset RET @ IO Power value Ball Name Port Func-0 Func-1 Func-2 Func-3 Power Circuit guide Domain stat down ANALOG[6 XuhostDM XuhostDM ANALOG[6 XuotgID XuotgID VDD_UOTG ANALOG[6 XuotgVBUS XuotgVBUS Xepllfilt 1.8nF cap...

  • Page 63: Ball Number Assignment

    S5PV210_HARDWARE DESING GUIDE REV 1.0 2. Ball number assignment Table 2.1-1 S5PV210 584 Pin Assignment − Pin Number Order (1/8) Ball Pin Name Ball Pin Name Ball Pin Name Ball Pin Name AA16 VSS_UHOST_AC XVVD_22 AD21 XUOTGDP XMSMDATA_15 AA17 XCIDATA_7...
  • Page 64 S5PV210_HARDWARE DESING GUIDE REV 1.0 Table 2.0-1 S5PV210 584 Pin Assignment − Pin Number Order (2/8) Ball Pin Name Ball Pin Name Ball Pin Name Ball Pin Name XM1DATA_5 AB11 XADCAIN_2 XI2S1SCLK AE16 XMIPIMDP1 XM1DQSN_0 AB12 XADCAIN_9 XI2S0SCLK AE17 XMIPIMDP0...
  • Page 65 S5PV210_HARDWARE DESING GUIDE REV 1.0 Table 2.0-2 S5PV210 584 Pin Assignment − Pin Number Order (3/8) Ball Pin Name Ball Pin Name Ball Pin Name Ball Pin Name XSPICSN_1 XMSMDATA_4 XM1ADDR_14 XMSMADDR_1 XM1DATA_30 XMSMDATA_6 XM1ADDR_2 XM1DATA_28 XMSMDATA_3 XM1ADDR_8 XMSMCSN XM1DATA_25...
  • Page 66 S5PV210_HARDWARE DESING GUIDE REV 1.0 Table 2.0-3 S5PV210 584 Pin Assignment − Pin Number Order (4/8) Ball Pin Name Ball Pin Name Ball Pin Name Ball Pin Name XMMC0DATA_3 XM1ADDR_15 XI2C0SDA XMSMADDR_0 XMMC1CDN XM2DATA_28 XPWMTOUT_3 XMSMADDR_5 XURXD_0 XM2DATA_26 XM1DATA_22 XM0ADDR_15...
  • Page 67 S5PV210_HARDWARE DESING GUIDE REV 1.0 Table 2.0-5 S5PV210 584 Pin Assignment − Pin Number Order (5/8) Ball Pin Name Ball Pin Name Ball Pin Name Ball Pin Name VDD_MODEM XM0DATA_8 VDD_APLL VDD_ARM XSPIMISO_0 XM0DATA_9 XM2DATA_8 VDD_ARM VDD_EXT0 XM0DATA_1 XM2DATA_5 XSPIMOSI_0...
  • Page 68 S5PV210_HARDWARE DESING GUIDE REV 1.0 Table 2.0-6 S5PV210 584 Pin Assignment − Pin Number Order (6/8) Ball Pin Name Ball Pin Name Ball Pin Name Ball Pin Name XM0ADDR_5 XM2DATA_10 VDD_INT XM0ADDR_0 XM2DQS_1 VSS_MPLL VDD_INT XM0ADDR_6 XM2DQSN_1 VDD_MPLL VDD_INT XM0ADDR_11...
  • Page 69 S5PV210_HARDWARE DESING GUIDE REV 1.0 Table 2.0-7 S5PV210 584 Pin Assignment − Pin Number Order (7/8) Ball Pin Name Ball Pin Name Ball Pin Name Ball Pin Name VDD_HDMI_OSC XHDMITX2N XHDMIXTI VDD_EXT1 XHDMITX2P XMMC2DATA_2 XM0FRNB_2 XMMC2DATA_0 VDD_INT XDACCOMP XMMC2DATA_1 XDACVREF...
  • Page 70 S5PV210_HARDWARE DESING GUIDE REV 1.0 Table 2.0-8 S5PV210 584 Pin Assignment − Pin Number Order (8/8) Ball Pin Name Ball Pin Name Ball Pin Name Ball Pin Name XJTCK XEINT_27 XDACOUT XVVSYNC_LDI XEINT_17 VSS_DAC_A XVVD_9 XEINT_10 VDD_DAC_A VDD_ADC XEINT_3 VDD_AUD...

  • Page 71: Power

    S5PV210_HARDWARE DESING GUIDE REV 1.0 3. Power 3.1. Pin Power Domain Power Ball Group Signal Ball Name Name XM2ADDR[13:0],XM2BA[1:0],XM2CASN,XM2RASN, DIGITAL XM2WEN,XM2CKE0,XM2CKE1/ADDR14,XM2CSN[1:0], VDD_M2 XM2DQS[3:0],XM2DQSN[3:0],XM2DM[3:0],XM2SCLK, POWER XM2SCLKN,XM2DATA[31:0] XM1ADDR[13:0],XM1BA[1:0],XM1CASN,XM1RASN, XM1WEN,XM1CKE0,XM1CKE1/ADDR14,XM1CSN[1:0], VDD_M1 XM1DQS[3:0],XM1DQSN[3:0],XM1DM[3:0],XM1SCLK, XM1SCLKN,XM1DATA[31:0] XM0ADDR_[15:0],XM0BEN_[1:0],XM0CSN_[5:0], XM0DATA_[15:0],XM0DATA_RDN,XM0FALE,XM0FCLE, VDD_M0 XM0FREN,XM0FRNB_[3:0],XM0FWEN,XM0OEN,XM0WAITN, XM0WEN, XEFFSOURCE_0 XVHSYNC,XVSYS_OE,XVVCLK,XVVD_[23:0],XVVDEN, VDD_LCD XVVSYNC,XVVSYNC_LDI XCICLKENB,XCIDATA_[7:0],XCIFIELD,XCIHREF,XCIPCLK, VDD_CAM XCIVSYNC XI2S0CDCLK,XI2S0LRCK,XI2S0SCLK,XI2S0SDI,...
  • Page 72 S5PV210_HARDWARE DESING GUIDE REV 1.0 Power Ball Group Signal Ball Name Name XUTXD_2,XURXD_3,XUTXD_3 XMMC3CDN,XMMC3CLK,XMMC3CMD,XMMC3DATA_[3:0], VDD_EXT2 XSPICLK_1,XSPICSN_1,XSPIMISO_1,XSPIMOSI_1 VDD_CKO XRTCCLKO VDD_RTC XRTCXTI,XRTCXTO VDD_DAC XDACCOMP,XDACIREF,XDACOUT_0,XDACVREF XHDMIREXT,XHDMITX0N,XHDMITX0P,XHDMITX1N, VDD_HDMI XHDMITX1P,XHDMITX2N,XHDMITX2P,XHDMITXCN, XHDMITXCP VDDOSC_HDMI XHDMIXTI,XHDMIXTO ANALOG POWER XMIPIMDNCLK, XMIPIMDPCLK, XMIPISDNCLK, XMIPISDPCLK, VDD_MIPI_D - should XMIPIVREG_0P4V be OFF in Sleep XMIPIMDN[3:0], XMIPIMDP[3:0], XMIPISDN[3:0], mode...

  • Page 73: Recommend Operating Conditions

    S5PV210_HARDWARE DESING GUIDE REV 1.0 3.2. Recommend Operating Conditions Symbol On/Off @ Reset On/Off @ Sleep Unit VDDALIVE 1.05 1.35 VDDAPLL VDDMPLL VDDEPLL VDDVPLL 800MHz 1.15 1.35 VDDINT 1GHz 1.15 1.35 800MHz 1.15 1.35 VDDARM 1GHz 1.15 1.35 VDD_M0 1.8/2.5/3.3 VDD_M1 1.15 1.2/1.8...
  • Page 74 S5PV210_HARDWARE DESING GUIDE REV 1.0 Symbol On/Off @ Reset On/Off @ Sleep Unit VDD_MIPI_A On/Off VDD_MIPI_D On/Off 1.05 1.15 VDD_MIPI_PLL On/Off 1.05 1.15 On/Off VDD_UOTG_A On/Off VDDI_UOTG_D 1.05 1.15 VDD_UHOST_A On/Off On/Off VDDI_UHOST_D 1.05 1.15 Operating Temperature TA Industrial -40 to 85 Operating Temperature TA Extended -20 to 70...

  • Page 75: Circuit Design Without Level Shifter

    S5PV210_HARDWARE DESING GUIDE REV 1.0 3.3. Circuit design without level shifter Power VDD_EXT0 VDD_EXT1 VDD_EXT2 SD/MMC MMC0, MMC1 MMC2 MMC3 SPI0 SPI1 SPI1 Uart UART0, UART1 UART2, UART3 I2C0 I2C1, I2C2 MMC 4channel, SPI 2channel, Uart 4channel and I2C 3channel has different Power domains Ex) 2 MMC channel , 2Uart channel ¸1 SPI channel, 1 I2C channel : 1.8V, 2MMC channel, 2Uart channel, 1 SPI channel, 2 I2C channel : 3.0V =>...

  • Page 76: Power On/Off Sequence

    S5PV210_HARDWARE DESING GUIDE REV 1.0 3.4. Power On/Off Sequence Power On sequence OSC_STABLE > 0ns > 0ns Figure 3-1) Power on sequence ote) 1. OSC’s frequency should be meet the specification which is 24Mhz...
  • Page 77 S5PV210_HARDWARE DESING GUIDE REV 1.0 Power Off Sequence Figure 3-2) Power off sequence...

  • Page 78: Pin Configuration Guide In Sleep Mode

    Output pin XMADDR, XMDQM Retention IO S5PV210 has a lot of retention I/O that is remaining data during the Power down mode (deep-stop(top off), deep-idle(top off), sleep mode) Alive block GPIO (GPH0, GPH1,GPH 2, GPH3) is not retention I/O After wake up from power down mode, you should first set GPIO configuration as the same ones before those power down mode and then you should set ENABLE_GPIO, ENABLE_MMC_IO, and ENABLE_UART_IO bits to ‘1’...

  • Page 79: Syscon

    S5PV210_HARDWARE DESING GUIDE REV 1.0 4. SYSCON 4.1. Signal Description - JTAG (Dedicated signal) Ball Name Description XjTRSTn (TAP Controller Reset) resets the TAP controller at start. XJTRSTN XjTMS (TAP Controller Mode Select) controls the sequence of the TAP controller’s XJTMS states.
  • Page 80 S5PV210_HARDWARE DESING GUIDE REV 1.0 - Clock (Dedicated signal) Ball Name Description 32.768 KHz crystal input for RTC XRTCXTI XRTCXTO 32.768 KHz crystal output for RTC Crystal Input for internal osc circuit XXTI Crystal output for internal osc circuit. XXTO Crystal Input for internal USB circuit XUSBXTI Crystal output for internal USB circuit...

  • Page 81: Booting Option

    S5PV210_HARDWARE DESING GUIDE REV 1.0 4.2. Booting Option OM[5:0] pin should be tied with VDDSYS or GND, directly. It is aimed for minimize leakage current when entering the sleep mode. But if you have to get an option, you should add a pull-up and pull-down resistor with 100K ohms over. OM[5] OM[4] OM[3]...

  • Page 82: Feature Of The Irom Boot Mode

    - Xm0CSn4/NFCSn2/ONANDXL_CSn0 signal should be used for boot 2. NAND : - Using S/W 8bit ECC at boot page - S5PV210 supports 16bit ECC in case of 4KB, 5cycle Nand type,. - Xm0CSn2/NFCSn0 signal should be used for boot 3. SD/MMC and eMMC : - SDMMC CH0 is used for first 4bit boot.

  • Page 83: Clock

    S5PV210_HARDWARE DESING GUIDE REV 1.0 4.4. Clock 4.4.1. Input Clock U S B M A I N X U S B X T I X X T I R f e d R f e d _ U S B M A I N M A I N X U S B X T O...
  • Page 84 S5PV210_HARDWARE DESING GUIDE REV 1.0 Aging: ±3.0ppm/year max. Note) External capacitance calculation External capacitor C1,2 can be calculated by following equation. ) } + pcb strays (assumed to 1~3pF) CL ≒ { (C1 + C ) (C2 + C ) / (C + C1 + C2 + C IC_IN IC_OUT...

  • Page 85: Memory Subsystem

    Memory Address, Bank Address, CS, CKE signals 5.2. TQ : Temperature Indicator Samsung mDDR includes the enhanced feature, Temperature Indicator (TQ), which informs MDRAM’s internal temperature of controller, in order to notice that DRAM inside temperature become higher than 85’C which is the highest temperature guaranteed normally in the specification.
  • Page 86 S5PV210_HARDWARE DESING GUIDE REV 1.0 Power and ground design guide General design rule is applied on this case. I. Ground layer has to be placed adjacent to signal layer for current return path. II. Ground plane has not to be split. III.
  • Page 87 S5PV210_HARDWARE DESING GUIDE REV 1.0 II. CSn, CKE, ADDR[13:0], BA[1:0], RASn, CASn, WEn, AP signal 　 a) SCLK(n) & ADDR[15:0], CASn, RASn, CKE[1:0], WEn Skew: -/+ 100ps (Target length: -/+ 10mm). b) T-branch topology is recommended for Command, Address and Control net.(CKE[1:0], CSn[1:0], 　...

  • Page 88: Srom Controller

    If data is output, this signal goes to High. EBI_DATA_RDn If data is input, this signal goes to Low. EBI_ADDR[15:0] O Memory port 0 Address bus EBI_DATA[15:0] IO Memory port 0 Data bus SRAM/ROM S5PV210 8bit data bus Xm0ADDR0 Addr. connection Half-word base(AddrMode =0)(default) Xm0ADDR0 16bit data...

  • Page 89: Sram/Rom Interface Examples

    S5PV210_HARDWARE DESING GUIDE REV 1.0 6.2. SRAM/ROM Interface Examples Figure 6-1) Memory Interface with 8-bit SRAM Figure 6-2) Memory Interface with 16-bit SRAM 1) Xm0ADDR[16:22] are muxed with other functions. And Xm0ADDR[16:22] are not released retention Note. automatically like Xm0ADDR[0:15]. 2) Address space : Up to 16MB per Bank...

  • Page 90: Onenand Controller

    7. OneNAND Controller Overview S5PV210 supports external 16-bit bus for OneNAND and Flex-OneNAND memory devices. The OneNAND controller supports asynchronous and synchronous read/write bus operations. It also integrates its own dedicated DMA engine and microsequencer to accelerate the OneNAND memory device operation.

  • Page 91: Circuit Diagram Example

    S5PV210_HARDWARE DESING GUIDE REV 1.0 7.2. Circuit Diagram Example S5PV210 has an external OneNAND control ports. Xm0ADDR[15:0] Xm0DATA[15:0] Xm0DATA[15:0] ONANDXL_CSn[1] ONANDXL_CSn[1] Xm0WEn Xm0WEn Demux S5PC110 S5PC110 Xm0OEn Xm0OEn OneNAND OneNAND ONDXL_AVD ONDXL_INT[1] ONDXL_RPn ONDXL_AVD ONDXL_SMCLK ONDXL_RPn ONDXL_SMCLK Figure 7-1) Mux & Demux OneNand connection block diagram Note) In case of internal OneNand(POP), ONANDXL_CSn[0] and ONDXL_INT[0] signals are used for internal OneNand.

  • Page 92: Nand Flash Controller

    S5PV210_HARDWARE DESING GUIDE REV 1.0 8. NAND Flash Controller 8.1. Signal Description Signal Description Comment Memory Port 0 NAND Command Latch Enable NF_CLE Memory Port 0 NAND Address Latch Enable NF_ALE Memory Port 0 NAND Flash Write Enable NF_FWEn Memory Port 0 NAND Flash Read Enalbe NF_FREn - NF_RnB[0] signal used for iROM Memory Port 0 NAND Flash Ready/Busy...
  • Page 93 S5PV210_HARDWARE DESING GUIDE REV 1.0 ure 8-1) 1-CE case and 2-CE case connection Figure 8-2) 4-CE case connection (1) Nand signal power domain belongs to VDD_M0. Confirm the voltage level of another SRAM interface. (2) External 4.7K pull-up resistor need to be added to RnB signal. (3) When NAND is selected for iROM booting storage, Xm0CSn2(NFCSn0),Xm0FRnB0 should be used for NAND chip select &...

  • Page 94: Cf Controller

    S5PV210_HARDWARE DESING GUIDE REV 1.0 9. CF Controller 9.1. CFCON feature CF Controller support only True-IDE mode.(don’t support PC card mode.) This is compatible with ATA/ATAPI-6 standard. Cautions (1) Check voltage domain of CF address and data, because addr/data shared MSM interface. (2) CF Card Vdd is controlled by GPIO.

  • Page 95: Cf 1-Slot Operation Guide

    S5PV210_HARDWARE DESING GUIDE REV 1.0 9.3. CF 1-slot operation guide...

  • Page 96: Cf 2-Slot Operation Guide

    S5PV210_HARDWARE DESING GUIDE REV 1.0 9.4. CF 2-slot operation guide (1) S5PV210 CF Controller can use CF card and HDD together by using 2slot operation (master and slave) (2) Follow Figure 10_2) using 2 slot Schematic (master socket is selected by nCSEL_n pin state. Master : low-level, Slave : NC) (ex) CON1 : Master, CON2 : Slave =>...

  • Page 97: Pwm Timer

    10.1. Overview The S5PV210 has five 32-bit timers. These timers generate internal interrupts to the ARM subsystem. In addition, Timers 0, 1, 2 and 3 include a Pulse Width Modulation (PWM) function which drives an external I/O signal. The PWM for timer 0 has an optional dead-zone generator capability to support a large current device.

  • Page 98: Uart

    S5PV210_HARDWARE DESING GUIDE REV 1.0 11. UART 11.1. Signal descriptoin Signal Description Comment UART receives data input CH0 FIFO Depth : 256byte UART0/1/2/3_RXD CH1 FIFO Depth : 64byte CH2 FIFO Depth : 16byte O UART transmits data output UART0/1/2/3_TXD CH3 FIFO Depth : 16byte UART clear to send input signal UART0/1/2_CTSn - CH2 is for Low Power Audio(RP)

  • Page 99: Iic-Bus Interface

    S5PV210 has 3 IIC control block, Channel 1 can use internally for HDMI DDC control. Channel 0 and 2 can be used general IIC port. But When you use HDM DDC, You should not use Channel 1 in general IIC, 12.1.

  • Page 100: Equation Of The Pull-Up Resistor Value

    S5PV210_HARDWARE DESING GUIDE REV 1.0 12.2. Equation of the pull-up resistor value = 0.3 V = 0.7 V Figure 12-1) Definition of timing for High-Speed mode devices on the IIC –bus 1) tr (Rising time) which depends on Pull- up resistance and bus capacitance affects SCL frequency change ( Higher tr makes slower SCL), especially when it is High-Speed mode (400kHz) 2) tr (Rising time) maximum is 300 ns , minimum is 20 + 0.1 Cb (bus capacitance) 3) When tr (Rising time) is 300ns, SCL might be maximum 13% slower than original setting value...

  • Page 101: Signal Description

    SPI master output / slave input line SPI0/1_MOSI 13.2. EXTERNAL Loading Capacitance S5PV210 has three SPI controllers. Both controllers should follow the external loading capacitance below. Output capacitance must be lower than 30pF at the channel 0/1. 13.3. SPI Maximum Speed The maximum frequency Master Tx/Master Rx/Slave Rx/Slave Tx(CPHA=0) is up to 50MHz.

  • Page 102: Usb Host

    S5PV210_HARDWARE DESING GUIDE REV 1.0 14. USB Host 14.1. Singnal Description Ball Name Description USB HOST charge pump enable XUHOSTPWREN USB HOST over current flag XUHOSTOVERCUR USB HOST Data pin DATA(+) XUHOSTDP USB HOST External 44.2ohm (+/- 1%) pull-down XUHOSTREXT USB HOST Data pin DATA(-) XUHOSTDM 14.2.

  • Page 103: Usb Signal Routing

    S5PV210_HARDWARE DESING GUIDE REV 1.0 USB HOST VDD_3V3 R218 XuhREXT 44.2/1% R273 XuhOVERCUR 100K SN74LVC1G04DBV DC5V DC5V R220 CTB64 R222 10uF/10V CON14 VBUS XuhDN R224 XuhDP XuhPWREN USB SINGLE Port - A Ty pe (Host) R226 TPS2051BDBV DN and DP should be routed evenly Figure 14-1) USB Host circuit example 14.4.
  • Page 104 S5PV210_HARDWARE DESING GUIDE REV 1.0 HS clock and HS USB different pairs should be first routed with minimum trace length. III. Route high-speed USB signals not using vias and stubs with using two 45 degree turns or an arc instead of making a single 90 degree trun.

  • Page 105: Signal Descriptoin

    S5PV210_HARDWARE DESING GUIDE REV 1.0 15. USB 2.0 HS OTG 15.1. Signal Descriptoin Comment Ball Name Description O USB OTG charge pump enable XUOTGDRVVUBS IO USB OTG Data pin DATA(+) XUOTGDP USB OTG External 44.2ohm (+/- 1%) resistor XUOTGREXT connection IO USB OTG Data pin DATA(-) XUOTGDM IO USB OTG Mini-Receptacle Identifier...
  • Page 106 S5PV210_HARDWARE DESING GUIDE REV 1.0 R227 0 USB OTG XuoVBUS R228 R229 R230 (10K) XuoREXT [2,19] XEINT24/KP_ROW0 44.2/1% R234 DC5V CTB66 CON15 10uF/10V VBUS XuoDM XuoDP R239 CB125 XuoID XuoDRVVBUS GND G9 100nF USB-MINIAB R240 TPS2051BDBV Figure 15-1) USB OTG Circuit Example Note) In this case VBUS signal can be used for wakeup source.

  • Page 107: Modem Interface

    This specification defines the interface between the Base-band Modem and the Application Processor for the data- exchange of these two devices. For the data-exchange, the AP (Application Processor, S5PV210) has a DPSRAM(Dual Port SRAM, 16KB) buffer (on-chip) and the Modem chip can access that DPSRAM buffer using a typical asynchronous-SRAM interface.
  • Page 108 S5PV210_HARDWARE DESING GUIDE REV 1.0 Caution (1) Voltage level is same between MODEM(memory bus and EXINT) and AP(MODEM I/F). Confirm the datasheet what you want to use. (2) There is only one interrupt request pin from AP to MODEM(XmsmIRQn). Any other extra interrupt request pin doesn’t needs between AP and modem because interrupt requests from modem to AP are delivered through XmsmADDR[12:0] and XmsmDATA[15:0] by writing some value to INT2AP register of DPSRAM in AP.

  • Page 109: Sd/Mmc Host Controller

    S5PV210_HARDWARE DESING GUIDE REV 1.0 17. SD/MMC HOST CONTROLLER S5PV210 has three slots for supporting high speed SD/MMC interface. SDMMC0 as 4-bit/8-bit MMC interface, SDMMC1 support 4-bit MMC interfaces. Every MMC controller belongs to VDD_EXT0/1/2 power. 17.1. Signal Description Signal...
  • Page 110 S5PV210_HARDWARE DESING GUIDE REV 1.0...

  • Page 111: Signal Description

    S5PV210_HARDWARE DESING GUIDE REV 1.0 18. TSI 18.1. Signal Description Signal Description TS_CLK TSI system clock TS_SYNC TSI synchronization control signal TS_VAL TSI valid signal TS_DATA TSI input data TS_ERROR TSI error indicate signal 18.2. Connection Example Channel Chip C110 TS CLK TS CLK TS SYNC...

  • Page 112: Display Controller

    S5PV210_HARDWARE DESING GUIDE REV 1.0 19. DISPLAY CONTROLLER 19.1. Signal Description Signal Description LCD type Horizontal Sync Signal for RGB interfacel LCD_HSYNC Vertical Sync Signal for RGB interface LCD_VSYNC Data Enable for RGB interface LCD_VDEN RGB I/F Video Clock for RGB interface LCD_VCLK LCD_VD[23:0] LCD pixel data output for RGB interface...

  • Page 113: Vd Signal Connection

    S5PV210_HARDWARE DESING GUIDE REV 1.0 19.2. VD signal connection Func0 Func1 Func2 Ball Name LCD_HSYNC O SYS_CS0 O VEN_HSYNC XVHSYNC LCD_VSYNC O SYS_CS1 O VEN_VSYNC XVVSYNC LCD_VDEN O SYS_RS O VEN_HREF XVVDEN LCD_VCLK O SYS_WE O V601_CLK XVVCLK LCD_VD[0] O SYS_VD[0] IO VEN_DATA[0] XVVD_0 LCD_VD[1]...

  • Page 114: Vd Signal Connection At Each Bpp Mode

    S5PV210_HARDWARE DESING GUIDE REV 1.0 19.3. VD signal connection at each bpp mode. Parallel RGB Serial RGB 24BPP 18BPP 16BPP 24BPP (888) 18BPP (666) (888) (666) (565) R[7] R[5] R[4] D[7] D[5] XVVD_23 R[6] R[4] R[3] D[6] D[4] XVVD_22 R[5] R[3] R[2] D[5]...
  • Page 115 S5PV210_HARDWARE DESING GUIDE REV 1.0 I80 CPU I/F (Parallel) 16BPP(565) 18BPP(666) 18BPP(666) 24BPP 18BPP(666) 16BPP(565) (888) Lx_DATA1 XVVD_23 XVVD_22 XVVD_21 XVVD_20 XVVD_19 XVVD_18 R[5] XVVD_17 R[4] XVVD_16 R[4] R[5] R[7] B[7] R[3] XVVD_15 R[3] R[4] R[6] B[6] R[2] XVVD_14 R[2] R[3] R[5] B[5]...

  • Page 116: Camera Interface

    S5PV210_HARDWARE DESING GUIDE REV 1.0 20. Camera Interface 20.1. Signal Description Signal Description Pixel Clock, driven by the Camera processor A CAM_A/B_PCLK Vertical Sync, driven by the Camera processor A CAM_A/B_VSYNC Horizontal Sync, driven by the Camera processor A CAM_A/B_HREF Pixel Data for YCbCr in 8-bit mode or for Y in 16-bit mode, driven by the CAM_A/B_DATA[7:0 Camera processor A...

  • Page 117: Camera Input

    S5PV210_HARDWARE DESING GUIDE REV 1.0 20.2. Camera INPUT Camera Interface can support the next video standards, (1) ITU-R BT 601 YCbCr 8-bit mode (2) ITU-R BT 656 YCbCr 8-bit mode * Maximum. 8192 x 8192 pixels Camera input support Camera Interface max. Horizontal size Max size Item CAMIF 0...

  • Page 118: Mipi Dsi & Csi

    S5PV210_HARDWARE DESING GUIDE REV 1.0 21. MIPI DSI & CSI 21.1. Signal Description Ball Name I/O Description Comment IO Master DATA LANE0 DP for MIPI-DPHY XMIPIMDP0 IO Master DATA LANE1 DP for MIPI-DPHY XMIPIMDP1 IO Master DATA LANE2 DP for MIPI-DPHY XMIPIMDP2 IO Master DATA LANE3 DP for MIPI-DPHY XMIPIMDP3...

  • Page 119: Design Guide

    S5PV210_HARDWARE DESING GUIDE REV 1.0 21.2. Design Guide It is NOT attached passive device on Dp, Dn Cable Interface. Routing Length of Dp and Dn have same length between Master and Slave.( An aberration of them is under 3mm) Maximum Loading capacitance of Cable interface is 70pF. Differential Cable Interface impedance is 100 Ω...

  • Page 120: Tv Encoder

    S5PV210_HARDWARE DESING GUIDE REV 1.0 22. TV ENCODER 22.1. Signal Description Ball Name I/O Description Comment XdacCOMP IO External capacitor connection Connect 0.1uF ceramic capacitor to VDDDAC XdacVREF IO Reference voltage input Connect 0.1uF ceramic capacitor to GND Connect 1.2KΩ to GND for full scale output XdacIREF IO External resistor connection (1.3V)(Tolerance +- 1%)

  • Page 121: Hdmi

    S5PV210_HARDWARE DESING GUIDE REV 1.0 23. HDMI 23.1. Overview HDMI 1.3 Tx Subsystem V1.0 is comprised of an HDMI Tx Core with I2S/SPDIF input interface, CEC block and HDCP Key Block 23.2. Signal Description - ADC/ DAC / HDMI/ MIPI (Dedicated) Ball Name I/O Description Comment...

  • Page 122: Circuit Diagram Example

    S5PV210_HARDWARE DESING GUIDE REV 1.0 23.3. Circuit Diagram Example VDD_3V3 CEC Isolation Circuit 100nF SDMP0340LT 1.8K CBL_CEC XEINT12/HDMI_CEC...
  • Page 123 S5PV210_HARDWARE DESING GUIDE REV 1.0 HDMI VDD_EXT DC5V 100nF 100nF 4.7K 4.7K VCCA VCCB HDMI_SCL Xi2cSCL1 SCLA SCLB HDMI_SDA Xi2cSDA1 SDAA SDAB HDMI_I2C_EN PCA9517DGK HDMI XhdmiTX2P XhdmiTX2N XhdmiTX1P GND0 GND4 XhdmiTX1N TMDS_D2+ TMDS_SHIELD0 Rclamp0502B(N.C) Rclamp0502B(N.C) TMDS_D2- TMDS_D1+ TMDS_SHIELD1 TMDS_D1- XhdmiTX0P TMDS_D0+ XhdmiTX0N TMDS_SHIELD2...

  • Page 124: Pcb Artwork Guide

    S5PV210_HARDWARE DESING GUIDE REV 1.0 23.4. PCB Artwork Guide Transmission Line Design of Differential pairs For high-frequency signal transmission along the traces of the differential signals, the trace structure must be a transmission line structure. The strip line structure and the microstrip line structure are the most recommended structures.
  • Page 125 S5PV210_HARDWARE DESING GUIDE REV 1.0 Limit your trace length. Longer trace display more resistance and inductance and introduce more delays. It also limits the bandwidth which varies inversely with the square of trace length. Do not use any clock signal loops. Keep clock lines straight when possible. Do not route signals close to the edge of the PCB board.

  • Page 126: Signal Description

    IIS-bus serial data output for channel 0 (Lower Power Audio) 24.2. Audio Port There are three IIS Interface Controllers in S5PV210. IIS channel 1,2 are for normal 2 channel IIS. You can use 5.1 channel IIS with channel 0. External Clock Source S5PV210 provides a master clock to the codec through the I2S_CDCLK line.
  • Page 127 S5PV210_HARDWARE DESING GUIDE REV 1.0 Connection Example Figure 24-1) IIS Connection Example with WM8580 (Master Mode)

  • Page 128: Iis Bus Controller

    S5PV210 provides a master clock to the codec through the Xi2sCDCLK line. This configuration has an advantage that it is not necessary to configure oscillator circuit. For the making Master Clock, S5PV210 uses and divides EPLL, MPLL or PCLK (refer to the User’s Manual). If an oscillator circuit is configured for a precise clock for the Sampling Frequency without PLLs or Internal clocks, there is a way to accept to this frequency as a source of master clock through the Xi2sCDCLK line.

  • Page 129: Connection Example

    S5PV210_HARDWARE DESING GUIDE REV 1.0 25.3. Connection Example This example shows I2S connection using WM8580 Secondary interface. Figure 25-1) IIS Connection Example with WM8580 (Master Mode) Figure 25-2) External OSC Circuit for IISCDCLK (with WM8580)

  • Page 130: Ac97 Controller

    Serial Data In From AC97 CODEC AC97SDO Serial Data OUT to AC97 CODEC 26.2. Audio Ports In S5PV210, There is one AC97 Controller. AC97 PORT is shared with I2S channel 1 and PCM channel 1.functions. 26.3. Connection Example Figure 26-1) AC97 connection example...

  • Page 131: Pcm Bus Controller

    S5PV210_HARDWARE DESING GUIDE REV 1.0 27. PCM BUS CONTROLLER 27.1. Signal Description Signal Description PCM Serial Shift Clock for channel 0 PCM_0_SCLK Optional reference clock for channel 0 PCM_0_EXTCLK PCM Sync indicating start of word for channel 0 PCM_0_FSYNC PCM Serial Data Input for channel 0 PCM_0_SIN PCM Serial Shift Clock for channel 0 PCM_0_SOUT...

  • Page 132: External Clock Source

    S5PV210_HARDWARE DESING GUIDE REV 1.0 27.2. External Clock Source To make PCM Serial clock and PCM Frame Sync, PCM interface controller divides EPLL, MPLL or PCLK When these clocks are divided, its advantage is that it is not necessary to configure oscillator circuit(for feeding auxiliary clock(256fs/384fs) to Codec chip (MCLK), please refer to SEC).
  • Page 133 S5PV210_HARDWARE DESING GUIDE REV 1.0 Figure 27-1) Internal clocks(ex:EPLL) for PCM master clock (with WM8580) Figure 27-2) External clocks(ex:2.048MHz) for PCM master clock (with WM8580)

  • Page 134: Spdif

    S5PV210_HARDWARE DESING GUIDE REV 1.0 28. SPDIF 28.1. Signal Description Signal Description Global audio main clock(External MCLK) SPDIF_EXTCLK SPDIFOUT data output(Tx only) SPDIF_0_OUT Connection Example This example shows using TOSLINK. Figure 28-1) SPDIF Connection Example...

  • Page 135: Adc&Touch Screen Interface

    The 10/12bit CMOS ADC is a recycling type device with 10-channel analog inputs. It’s maximum conversion rate of 1Msps with 5MHz A/D converter clock. Touch screen interface can control/select pads (XP,XM,YP,YM) of the touch screen for X,Y position. In S5PV210, There are available two Touch screen interface. A mapped with touch signal like bellows.

  • Page 136: Keypad Interface

    S5PV210_HARDWARE DESING GUIDE REV 1.0 30. KEYPAD INTERFACE In S5PV210, The Key Pad ports multiplexed with GPIO ports provide up to 14 row and 8 columns. Keypad signals(Key_pad_ROW and Key_pad_COL) are multiplexed Host I/F and EINT. Therefore it is requisite to set GPIO ports as keypad function.

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