Page 1 USER'S MANUAL S3C2416 16/32-Bit RISC Microprocessor August 2008 REV 1.00 Confidential Proprietary of Samsung Electronics Co., Ltd Copyright © 2008 Samsung Electronics, Inc. All Rights Reserved...
Page 2: Important Notice
Samsung reserves the right to make changes in its intended for surgical implant into the body, for other products or product specifications with the intent to...
Page 3: Revision History
NOTIFICATION OF REVISIONS Samsung Electronics, LSI Development Group, Gi-Heung, South Korea ORIGINATOR: S3C2416 RISC Microprocessor PRODUCT NAME: S3C2416 User's Manual, Revision 1.00 DOCUMENT NAME: 21.10-S3-C2416-082008 DOCUMENT NUMBER: August, 2008 EFFECTIVE DATE: Revision 1.00 DIRECTIONS: REVISION HISTORY Revision No Description of Change...
Page 4 REVISION DESCRIPTIONS FOR REVISION 1.00 Chapter Subjects (Major changes comparing with last version) Chapter Name Page...
Page 5: Table Of Contents
3 Block Diagram............................1-5 4 Pin Assignments ............................1-6 4.1 Signal Descriptions.......................... 1-24 4.2 S3C2416 Operation Mode Description ................... 1-31 4.3 S3C2416 Memory MAP and Base Address of Special Registers........... 1-32 Chapter 2 System Controller 1 Overview ..............................2-1 2 Feature..............................2-1 3 Block Diagram............................
Page 6 Table of Contents (Continued) Chapter 2 System Controller (Continued) 8 Individual Register Descriptions........................2-22 8.1 Clock Source Control Registers (LOCKCON0, LOCKCON1, OSCSET, MPLLCON, and EPLLCON) ..........2-22 8.2 Clock Control Register (CLKSRC, CLKDIV, HCLKCON, PCLKCON, and SCLKCON)....2-25 8.3 Power Management Registers (PWRMODE and PWRCFG) ............2-31 8.4 Reset Control Registers (SWRST and RSTCON)................2-33 8.5 Control of retention PAD(I/O) when normal mode and wake-up from sleep mode......2-34 8.6 System Controller Status Registers (WKUPSTAT and RSTSTAT)..........2-35...
Page 7 Table of Contents (Continued) Chapter 5 Static Memory Controller (SMC) 1 Overview ..............................5-1 2 Feature..............................5-2 3 Block Diagram............................5-3 3.1 Asynchronous Read ........................5-4 3.2 Asynchronous Burst Read....................... 5-6 3.3 Synchronous Read/Synchronous Burst Read................. 5-7 3.4 Asynchronous Write ........................5-8 3.5 Synchronous Write/ Synchronous Burst Write ................
Page 8 Table of Contents (Continued) Chapter 7 NAND Flash Controller 1 Overview..............................7-1 2 Features ..............................7-1 3 Block Diagram ............................7-2 4 Boot Loader Function ..........................7-2 5 GPC5/6/7 Pin Configuration Table in IROM Boot Mode ................7-3 6 NAND Flash Memory Timing ........................7-3 7 NAND Flash Access..........................7-4 8 Data Register Configuration........................7-5 9 Steppingstone (8KB in 64KB SRAM) ......................7-5 10 1bit / 4bit / 8bit ECC (Error Correction Code) ..................7-5...
Page 9 Table of Contents (Continued) Chapter 8 DMA Controller 1 Overview ..............................8-1 2 DMA Request Sources ..........................8-2 3 DMA Operation ............................8-3 3.1 External DMA Dreq/Dack Protocol ....................8-4 3.2 Examples of Possible Cases......................8-7 4 DMA Special Registers ..........................8-8 4.1 DMA Initial Source Register (DISRC)....................
Page 10 Table of Contents (Continued) Chapter 10 I/O Ports 1 Overview..............................10-1 2 Port Control Descriptions ..........................10-9 2.1 Port Configuration Register (GPACON-GPMCON).................10-9 2.2 Port Data Register (GPADAT-GPMDAT) ..................10-9 2.3 Port Pull-Up/Down Register (GPBUDP-GPMUDP) .................10-9 2.4 Miscellaneous Control Register .......................10-9 2.5 External Interrupt Control Register ....................10-9 3 I/O Port Control Register ...........................10-10 3.1 PORT A Control Registers (GPACON, GPADAT)................10-10 3.2 PORT B Control Registers (GPBCON, GPBDAT, GPBUDP, GPBSEL).........10-12...
Page 11 Table of Contents (Continued) Chapter 11 WatchDog Timer 1 Overview ..............................11-1 1.1 Features............................11-1 2 Watchdog Timer Operation........................11-2 2.1 Block Diagram ..........................11-2 2.2 WTDAT & WTCNT .......................... 11-2 2.3 Consideration of Debugging Environment ..................11-3 3 Watchdog Timer Special Registers ......................11-4 3.1 Watchdog Timer Control (WTCON) Register..................
Page 12 Table of Contents (Continued) Chapter 13 Real Time Clock (RTC) 1 Overview..............................13-1 1.1 Features............................13-1 1.2 Real Time Clock Operation Description ..................13-2 1.3 External Interface..........................13-6 1.4 Register Description ........................13-7 1.5 Individual Register Descriptions ......................13-8 Chapter 14 UART 1 Overview..............................14-1 1.1 Features............................14-1 2 Block Diagram ............................14-2 2.1 UART Operation ..........................14-3 3 UART Special Registers ...........................14-12...
Page 13 Table of Contents (Continued) Chapter 16 USB 2.0 Function 1 Overview ..............................16-1 1.1 Feature ............................16-1 2 Block Diagram............................16-2 3 To Activate USB Port1 for USB 2.0 Function ................... 16-3 4 SIE (Serial Interface Engine) ........................16-4 5 UPH (Universal Protocol Handler) ......................16-4 6 UTMI (USB 2.0 Transceiver Macrocell Interface)..................
Page 14 Table of Contents (Continued) Chapter 17 IIC-Bus Interface 1 Overview..............................17-1 1.1 IIC-Bus Interface ..........................17-3 1.2 Start And Stop Conditions .......................17-3 1.3 Data Transfer Format ........................17-4 1.4 ACK Signal Transmission ........................17-5 1.5 Read-Write Operation........................17-6 1.6 Bus Arbitration Procedures......................17-6 1.7 Abort Conditions ..........................17-6 1.8 Configuring IIC-Bus..........................17-6 1.9 Flowcharts of Operations in Each Mode..................17-7 2 IIC-Bus Interface Special Registers ......................17-11...
Page 15 Table of Contents (Continued) Chapter 19 HS_SPI Controller 1 Overview ..............................19-1 2 Features ..............................19-1 3 Signal Descriptions ........................... 19-2 4 Operation ..............................19-2 4.1 Operation Mode..........................19-3 4.2 FIFO Access............................ 19-3 4.3 Trailing Bytes in the Rx FIFO ......................19-3 4.4 Packet Number Control ........................
Page 16 Table of Contents (Continued) Chapter 20 SD/MMC Host Controller (Continued) 5.13 Block Gap Control Register ......................20-38 5.14 Wakeup Control Register.......................20-40 5.15 Clock Control Register........................20-41 5.16 Timeout Control Register.......................20-43 5.17 Software Reset Register........................20-44 5.18 Normal Interrupt Status Register ....................20-46 5.19 Error Interrupt Status Register.......................20-50 5.20 Normal Interrupt Status Enable Register..................20-53 5.21 Error Interrupt Status Enable Register ..................20-55 5.22 Normal Interrupt Signal Enable Register ..................20-56...
Page 17 Table of Contents (Continued) Chapter 22 ADC & Touch Screen Interface 1 Overview ..............................22-1 1.1 Features............................22-1 2 ADC & Touch Screen Interface Operation....................22-2 2.1 Block Diagram ..........................22-2 2.2 Function Descriptions ........................22-3 3 ADC and Touch Screen Interface Special Registers................22-5 3.1 ADC Control (ADCCON) Register....................
Page 18 Table of Contents (Continued) Chapter 24 AC97 Controller 1 Overview..............................24-1 1.1 Feature.............................24-1 1.2 Signals .............................24-1 2 AC97 Controller Operation........................24-2 2.1 Block Diagram..........................24-2 2.2 Internal Data Path ..........................24-3 3 Operation Flow Chart ..........................24-4 4 AC-link Digital Interface Protocol ......................24-5 4.1 AC-link Output Frame (SDATA_OUT) .....................24-6 4.2 AC-link Input Frame (SDATA_IN)....................24-7 5 AC97 Power-Down............................24-9 6 Codec Reset..............................24-10...
Page 19 Table of Contents (Continued) Chapter 25 PCM Audio Interface 1 Overview ..............................25-1 1.1 Feature ............................25-1 1.2 Signals ............................. 25-1 2 PCM Audio Interface..........................25-2 3 PCM Timing .............................. 25-3 3.1 PCM Input Clock Diagram ....................... 25-4 3.2 PCM Registers ..........................25-5 3.3 PCM Register Summary........................
Page 20 Entering SLEEP Mode and Exiting SLEEP Mode (wake-up) ........2-18 2-13 Usage of PWROFF_SLP ..................... 2-34 The Configuration of MATRIX and Memory Sub-System of S3C2416 ....... 3-1 SMC Block Diagram ....................5-3 SMC Core Block Diagram.................... 5-3 External Memory Two Output Enable Delay State Read ..........5-4 Read Timing Diagram (DRnCS = 1, DRnOWE = 0)............
Page 21 List of Figures Figure Title Page Number Number NAND Flash Controller Block Diagram................7-2 NAND Flash Controller Boot Loader Block Diagram ...........7-2 CLE & ALE Timing (TACLS=1, TWRPH0=0, TWRPH1=0) Block Diagram ....7-3 nWE & nRE Timing (TWRPH0=0, TWRPH1=0) Block Diagram .........7-4 NAND Flash Memory Mapping Block Diagram............7-10 A 8-bit NAND Flash Memory Interface Block Diagram ..........7-11 Softlock and Lock-tight....................7-20...
Page 22 List of Figures Figure Title Page Number Number 13-1 Real Time Clock Block Diagram.................. 13-2 13-2 RTC Tick Interrupt Clock Scheme ................13-5 13-3 Main Oscillator Circuit Example................... 13-6 14-1 UART Block Diagram (with FIFO) ................14-2 14-2 UART AFC Interface....................14-4 14-3 Example showing UART Receiving 5 Characters with 2 Errors........
Page 23 List of Figures Figure Title Page Number Number 19-1 HS_SPI Transfer Format....................19-4 20-1 HSMMC Block Diagram ....................20-2 20-2 SD Card Detect Sequence...................20-3 20-3 SD Clock Supply Sequence..................20-4 20-4 SD Clock Stop Sequence ....................20-5 20-5 SD Clock Change Sequence ..................20-5 20-6 SD Bus Power Control Sequence................20-6 20-7 Change Bus Width Sequence..................20-7...
Page 24 List of Figures Figure Title Page Number Number 22-1 ADC and Touch Screen Interface Block Diagram ............22-2 22-2 Timing Diagram in Auto (Sequential) X/Y Position Conversion Mode ......22-4 23-1 IIS-Bus Block Diagram....................23-2 23-2 IIS Clock Control Block Diagram ................. 23-3 23-3 IIS Audio Serial Data Formats ..................
Page 25 List of Figures Figure Title Page Number Number 26-1 XTIpll Clock Timing ......................26-7 26-2 EXTCLK Clock Input Timing ..................26-7 26-3 EXTCLK/HCLK in case that EXTCLK is used without the PLL ........26-7 26-4 HCLK/CLKOUT/SCLK in case that EXTCLK is used ..........26-8 26-5 Manual Reset Input Timing ..................26-8 26-6...
Page 26 400-Pin FBGA Pin Assignments − Pin Number Order (2/4)........1-8 400-Pin FBGA Pin Assignments − Pin Number Order (3/4)........1-9 400-Pin FBGA Pin Assignments – Pin Number Order (4/4)........1-10 S3C2416 400-Pin FBGA Pin Assignments..............1-11 I/O Cell Types and Descriptions .................. 1-23 S3C2416 Signal Descriptions..................1-24 S3C2416 Operation Mode Description................
Page 27 List of Tables Table Title Page Number Number 16-1 Non-Indexed Registers ....................16-5 16-2 Indexed Registers ......................16-6 19-1 External Signals Description ..................19-2 20-1 Determination of Transfer Type ...................20-24 20-2 Relation Between Parameters and the Name of Response Type .......20-26 20-3 Response Bit Definition for Each Response Type............20-27 20-4 The relation between Command CRC Error and Command Timeout Error....20-52 20-5...
Page 28 List of Tables Table Title Page Number Number 26-1 Absolute Maximum Rating................... 26-1 26-2 Recommended Operating Conditions (400MHz) ............26-2 26-3 Recommended Operating Conditions (533MHz) ............26-3 26-4 Normal I/O PAD DC Electrical Characteristics ............26-4 26-5 Special Memory DDR I/O PAD DC Electrical Characteristics........26-5 26-6 USB DC Electrical Characteristics................
Page 29: Product Overview
PRODUCT OVERVIEW 1 INTRODUCTION This user’s manual describes SAMSUNG's S3C2416X 16/32-bit RISC microprocessor. SAMSUNG’s S3C2416X is designed to provide hand-held devices and general applications with low-power, and high-performance micro- controller solution in small die size. To reduce total system cost, the S3C2416X includes the following components.
Page 30: Features
PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR 2 FEATURES 2.1.1 Architecture 2.1.3 NAND Flash • Integrated system for hand-held devices and • Supports booting from NAND flash memory by general embedded applications. selecting OM as IROM boot mode. (Only 8bit Nand and 8ECC is supported when it boots) •...
Page 31 S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW 2 FEATURES (Continued) • Supports memory to memory, IO to memory, 2.1.6 Interrupt Controller memory to IO, and IO to IO transfers • 71 Interrupt sources • Burst transfer mode to enhance the transfer rate (One Watch dog timer, 5 timers, 12 UARTs, 16 external interrupts, 6 DMA, 2 RTC, 2 ADC, 1 IIC, 2.1.11 LCD Controller...
Page 32 PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR FEATURES (Continued) FIFOs to buffer data 2.1.13 A/D Converter & Touch Screen Interface • 10-ch multiplexed ADC 2.1.20 USB Host • Max. 500KSPS and 12-bit Resolution • 2-port USB Host Complies with OHCI Rev. 1.0 •...
Page 33: Block Diagram
S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW 3 BLOCK DIAGRAM Figure 1-1. S3C2416X Block Diagram...
Page 34: Pin Assignments
PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR 4 PIN ASSIGNMENTS Figure 1-2. S3C2416X Pin Assignments (330-FBGA, 0.65mm pitch) Top view...
Page 35 S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-1. 400-Pin FBGA Pin Assignments − Pin Number Order (1/3) Pin Name Ball Pin Name Ball Pin Name Ball RSMCLK/GPA23 VDDiarm VSS_LCD RSMVAD/GPA24 VSSiarm RGB_VD[20]/GPD12 RSMBWAIT/GPM LEND/GPC0 RGB_VD[21]/GPD13 nRCS[3]/GPA14 VDDiarm RGB_VD[22]/GPD14 nRCS[4]/GPA15 VSSiarm RGB_VD[23]/GPD15 RGB_VCLK/GPC1 nRCS[5]/GPA16 TOUT[0]/GPB0...
Page 36 PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR I2SSCLK/GPE1/AC_SYNC/ VSSi VDD_LCD PCM_SCLK...
Page 37 S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-1. 400-Pin FBGA Pin Assignments − Pin Number Order (2/3) Pin Name Ball Pin Name Ball Pin Name Ball I2SCDCLK/GPE2/AC_BI EINT[11]/GPG3 T_CLK/PCM_CDCLK AIN[0] I2SSDI/GPE3/AC_SDI/P VDD_OP3 CM_SDI Vref I2SSDO/GPE4/AC_SDO VSS_OP3 /PCM_SDO VDDA_ADC EINT[12]/GPG4 SPIMISO/GPE11 VDD_RTC EINT[13]/GPG5 SPIMOSI/GPE12 Xtirtc...
Page 38 PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR EINT[10]/GPG2 SDATA[14] AIN[1] 1-10...
Page 39 S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-1. 400-Pin FBGA Pin Assignments − Pin Number Order (3/3) Pin Name Ball Pin Name Ball Pin Name Ball SDATA[13] SADDR[9] nRCS[0] SDATA[12] SADDR[10] nRCS[1]/GPA12 SDATA[11] SADDR[11] nRCS[2]/GPA13 SDATA[10] SADDR[12] VDD_SDRAM SDATA[9] SADDR[13] VDD_SDRAM SDATA[8] SADDR[14] VDD_SDRAM...
Page 40 PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR SADDR[8] nRWE Table 1-2. S3C2416X 330-Pin FBGA Pin Assignments Default I/O State Number Name Function State @nRESET Type @Sleep RSMCLK/GPA23 RSMCLK O(L) pvhbsudtbrt RSMVAD/GPA24 RSMVAD O(H) pvhbsudtbrt RSMBWAIT/GPM0 RSMBWAIT pvhbsudtbrt nRCS3/GPA14 nRCS3 O(H) pvhbsudtbrt nRCS4/GPA15 nRCS4 O(H) pvhbsudtbrt...
Page 41 S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW Default I/O State Number Name Function State @nRESET Type @Sleep RDATA0 RDATA0 Hi-z pvhbsudtbrt VDDi VDDi vddivh_alv VSSi VSSi vssipvh_alv VDDi VDDi vddivh_alv VSSi VSSi vssipvh_alv VDDiarm VDDiarm vddicvlh_alv VSSiarm VSSiarm vssicvlh_alv RGB_LEND/GPC0 GPC0 pvhbsudtart VDDiarm VDDiarm vddicvlh_alv...
Page 42 PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR Default I/O State Number Name Function State @nRESET Type @Sleep RGB_VD17/GPD9 GPD9 pvhbsudtart RGB_VD18/GPD10 GPD10 pvhbsudtart RGB_VD19/GPD11 GPD11 pvhbsudtart VDDiarm VDDiarm vddicvlh_alv VSSiarm VSSiarm vssicvlh_alv VDD_LCD VDD_LCD vddtvh_alv VSS_LCD VSS_LCD vsstvh_alv RGB_VD20/GPD12 GPD12 pvhbsudtart RGB_VD21/GPD13 GPD13 pvhbsudtart RGB_VD22/GPD14...
Page 43 S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW Default I/O State Number Name Function State @nRESET Type @Sleep CLKOUT1/GPH14 GPH14 pvhbsudtart VDDiarm VDDiarm vddicvlh_alv VSSiarm VSSiarm vssicvlh_alv IICSCL/GPE14 GPE14 pvhbsudtart IICSDA/GPE15 GPE15 pvhbsudtart I2SLRCK/GPE0/ -/-/- GPE0 pvhbsudtart AC_nRESET/PCM_FSYNC I2SSCLK/GPE1/AC_SYNC/PC -/-/- GPE1 pvhbsudtart M_SCLK I2SCDCLK/GPE2/ -/-/- GPE2...
Page 44 PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR Default I/O State Number Name Function State @nRESET Type @Sleep SD1_DAT[3]/GPE10 GPE10 pvhbsudtart VSSA_MPLL VSSA_MPLL vsstvlh_alv VDDA_MPLL VDDA_MPLL vddtvlh_alv VSSA_EPLL VSSA_EPLL vsstvlh_alv UPLLCAP UPLLCAP pvhbr VDDA_EPLL VDDA_EPLL vddtvlh_alv VSSA_ADC VSSA_ADC AIN9(XP) AIN9 vsstvh_alv AIN8(XM) AIN8 pvhbr AIN7(YP) AIN7...
Page 45 S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW Default I/O State Number Name Function State @nRESET Type @Sleep EINT4/GPF4 GPF4 pvhbsudtart_alv EINT5/GPF5 GPF5 pvhbsudtart_alv EINT6/GPF6 GPF6 pvhbsudtart_alv EINT7/GPF7 GPF7 pvhbsudtart_alv PWR_EN PWR_EN O(L) O(H) pvhbsudtart_alv BATT_FLT BATT_FLT pvhbsudtart nRESET nRESET pvhbsudtart VDD_OP1 VDD_OP1 vddtvh_alv VSS_OP1 VSS_OP1...
Page 46 PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR Default I/O State Number Name Function State @nRESET Type @Sleep DM_UDEV DM_UDEV Hi-z pvhtbr REXT REXT pvhbr DP_UDEV DP_UDEV Hi-z pvhtbr VSS33T2 VSSA33T2 vsstvh_alv VDD33 VDDA33T1 vddtvh_alv VDD33 VDDA33T1 vddtvh_alv SDATA31/GPK15 SDATA31 Hi-z pvmbsudtbrt SDATA30/GPK14 SDATA30 Hi-z pvmbsudtbrt...
Page 47 S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW Default I/O State Number Name Function State @nRESET Type @Sleep SDATA5 SDATA5 Hi-z pvmbsudtbrt SDATA4 SDATA4 Hi-z pvmbsudtbrt SDATA3 SDATA3 Hi-z pvmbsudtbrt SDATA2 SDATA2 Hi-z pvmbsudtbrt SDATA1 SDATA1 Hi-z pvmbsudtbrt SDATA0 SDATA0 Hi-z pvmbsudtbrt VDD_SDRAM VDD_SDRAM Hi-z vddtvm_alv...
Page 48 PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR Default I/O State Number Name Function State @nRESET Type @Sleep SADDR10 SADDR10 O(L) pvmbsudtbrt SADDR11 SADDR11 O(L) pvmbsudtbrt SADDR12 SADDR12 O(L) pvmbsudtbrt SADDR13 SADDR13 O(L) pvmbsudtbrt SADDR14 SADDR14 O(L) pvmbsudtbrt SADDR15 SADDR15 O(L) pvmbsudtbrt FSOURCE FSOURCE pvhtbr_efuse00 VGATE...
Page 49 S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW Default I/O State Number Name Function State @nRESET Type @Sleep RADDR2 RADDR2 O(L) pvhbsudtbrt RADDR1 RADDR1 O(L) pvhbsudtbrt RADDR0/GPA0 RADDR0 O(L) pvhbsudtbrt nRBE1 nRBE1 O(H) pvhbsudtbrt nRBE0 nRBE0 O(H) pvhbsudtbrt nROE nROE O(H) pvhbsudtbrt nRWE nRWE O(H) pvhbsudtbrt...
Page 50 PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR Table 1-3. I/O Cell Types and Descriptions Interface CMOS Retention Pull-up Pull-down Cell Name Ftn. Driver Strength Voltage /Schmitt /Control /Control Pvhbdc 1.8/2.5/3.3V analog Pvhbr 1.8/2.5/3.3V analog pvhbsudtart 1.8/2.5/3.3V Schmit 2.6/5.2/7.8/10.5mA pvhbsudtart_alv 1.8/2.5/3.3V Schmit 2.6/5.2/7.8/10.5mA pvhbsudtbrt 1.8/2.5/3.3V Schmit...
Page 51: Signal Descriptions
S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW SIGNAL DESCRIPTIONS Table 1-4. S3C2416X Signal Descriptions Signal In/Out Description Reset, Clock & Power XTIpll Crystal input signals for internal osc circuit. When OM[0] = 0, XTIpll is used for MPLL CLK source and EPLL CLK source.
Page 52 PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR Signal In/Out Description nRBE[1:0] Upper byte/lower byte enable (In case of 16-bit SRAM) nWAIT nWAIT requests to prolong a current bus cycle. As long as nWAIT is L, the current bus cycle cannot be completed. If nWAIT signal isn’t used in your system, nWAIT signal must be tied on pull-up resistor.
Page 53 S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW Signal In/Out Description RGB_LEND/SYS_OE RGB I/F Line End Signal i80 I/F Output Enable Interrupt Control Unit EINT[15:0] External interrupt request External I/F nXDREQ[1:0] External DMA request nXDACK[1:0] External DMA acknowledge nXBREQ nXBREQ (Bus Hold Request) allows another bus master to request control of the local bus.
Page 54 PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR Signal In/Out Description AC_SDI0 Serial, time division multiplexed, AC’97 input stream AC_SDO0 Serial, time division multiplexed, AC’97 output stream PCM0_SCLK Serial shift clock PCM0_FSYNC Serial data indicator and synchronizer PCM0_SDI Serial PCM input data PCM0_SDO Serial PCM output data PCM0_CDCLK Optional External Clock source...
Page 55 S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW Signal In/Out Description JTAG TEST LOGIC nTRST nTRST (TAP Controller Reset) resets the TAP controller at start. If debugger is used, A 10K pull-up resistor has to be connected. If debugger (black ICE) is not used, nTRST pin must be issued by a low active pulse (Typically connected to nRESET).
Page 56 PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR Signal In/Out Description VSSA_ADC S3C2416X ADC VSS VDD_USBOSC USB 2.0 Oscillator Power(1.8 ~ 3.3V) VDDI_UDEV USB 2.0 PHY Power ( 1.2V) VSSI_UDEV USB 2.0 PHY Ground VDDA33C/VDDA33T1 USB 2.0 PHY Power ( 3.3V) VSSA33C/VSSA33T2 USB 2.0 PHY Ground NOTE: I/O : Input/Output.
Page 57: S3C2416 Operation Mode Description
S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW S3C2416X OPERATION MODE DESCRIPTION Table 1-5. S3C2416X Operation Mode Description Operation OM[4] OM[3] OM[2] OM[1] OM[0] OM[4] OM[3] OM[2] OM[1] OM[0] Mode X-TAL iROM iROM EXTCLK Reserved Reserved JTAG JTAG X-TAL OneNAND OneNAND 16-bit (Muxed) (Muxed) EXTCLK X-TAL...
Page 58: Memory Map
PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR S3C2416X MEMORY MAP AND BASE ADDRESS OF SPECIAL REGISTERS 4.3.1 Memory Map SRAM SRAM SRAM (64KB) (64KB) (8KB) 0x40000_0000 SDRAM SDRAM (nSCS1) (nSCS1) MPORT1 0x3800_0000 SDRAM SDRAM (nSCS0) (nSCS0) 0x3000_0000 SROM SROM (nRCS5) (nRCS5) 0x2800_0000 SROM SROM (nRCS4)
Page 59: Base Address Of Special Registers
S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-6. Base Address of Special Registers Address Module Address Module 0x4E00_0000 NFCON 0x5E00_0000 Reserved 0x4D80_0000 Reserved 0x5D00_0000 Reserved 0x4D40_8000 0x5C00_0100 Reserved 0x4D00_0000 Reserved 0x5C00_0000 0x4C80_0000 0x5B00_0000 AC97 0x4C00_0000 SYSCON 0x5A00_0000 Reserved 0x4B80_0000 Reserved 0x5900_0000 Reserved 0x4B00_0700 Reserved...
Page 60 PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR Table 1-7. S3C2416X Special Registers Acc. Read/ Register Name Address Reset Value Function Unit Write DRAM Controller BANKCFG 0x48000000 0x00099F0D Mobile DRAM configuration register BANKCON1 0x48000004 0x00000008 Mobile DRAM control register BANKCON2 0x48000008 0x00000008 Mobile DRAM timing control register BANKCON3 0x4800000C 0x00000008...
Page 61 S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW Acc. Read/ Register Name Address Reset Value Function Unit Write SMBWSTOENR3 0x4F00006C 0x00000002 Bank3 output enable assertion delay control register SMBWSTOENR4 0x4F00008C 0x00000002 Bank4 output enable assertion delay control register SMBWSTOENR5 0x4F0000AC 0x00000002 Bank5 output enable assertion delay control register SMBWSTWENR0 0x4F000010...
Page 62 PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR Acc. Read/ Register Name Address Reset Value Function Unit Write Interrupt Controller SRCPND1 0X4A000000 0x00000000 Interrupt request status INTMOD1 0X4A000004 0x00000000 Interrupt mode control INTMSK1 0X4A000008 0xFFFFFFFF Interrupt mask control INTPND1 0X4A000010 0x00000000 Interrupt request status INTOFFSET1 0X4A000014 0x00000000...
Page 63 S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW Acc. Read/ Register Name Address Reset Value Function Unit Write HcRhDescriptorB 0x4900004C HcRhStatus 0x49000050 HcRhPortStatus1 0x49000054 HcRhPortStatus2 0x49000058 DISRC0 0x4B000000 DMA 0 initial source DISRCC0 0x4B000004 DMA 0 initial source control DIDST0 0x4B000008 DMA 0 initial destination DIDSTC0 0x4B00000C DMA 0 initial destination control...
Page 64 PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR Acc. Read/ Register Name Address Reset Value Function Unit Write DIDST3 0x4B000308 DMA 3 initial destination DIDSTC3 0x4B00030C DMA 3 initial destination control DCON3 0x4B000310 DMA 3 control DSTAT3 0x4B000314 DMA 3 count DCSRC3 0x4B000318 DMA 3 current source DCDST3 0x4B00031C...
Page 65 S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW Acc. Read/ Register Name Address Reset Value Function Unit Write CLKDIV0 0x4C00_0024 0x0000_000C Clock divider ratio control register0 CLKDIV1 0x4C00_0028 0x0000_0000 Clock divider ratio control register1 CLKDIV2 0x4C00_002C 0x0000_0000 Clock divider ratio control register2 HCLKCON 0x4C00_0030 0xFFFF_FFFF HCLK enable register...
Page 66 PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR Acc. Read/ Register Name Address Reset Value Function Unit Write VIDW00ADD0B1 0x4C80_0068 0x0000_0000 Window 0’s buffer start address register, buffer 1 VIDW01ADD0 0x4C80_006C 0x0000_0000 Window 1’s buffer start address register VIDW00ADD1B0 0x4C80_007C 0x0000_0000 Window 0’s buffer end address register, buffer 0 VIDW00ADD1B1 0x4C80_0080...
Page 67 S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW Acc. Read/ Register Name Address Reset Value Function Unit Write NFADDR 0x4E00000C 0x00000000 Address register NFDATA 0x4E000010 Data register NFMECCD0 0x4E000014 0x00000000 1st and 2nd main ECC data register NFMECCD1 0x4E000018 0x00000000 3rd and 4th main ECC data register NFSECCD 0x4E00001C 0x00000000...
Page 68 PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR Acc. Read/ Register Name Address Reset Value Function Unit Write ULCON1 0x50004000 UART 1 line control UCON1 0x50004004 UART 1 control UFCON1 0x50004008 UART 1 FIFO control UMCON1 0x5000400C UART 1 modem control UTRSTAT1 0x50004010 UART 1 Tx/Rx status UERSTAT1 0x50004014...
Page 69 S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW Acc. Read/ Register Name Address Reset Value Function Unit Write TCON 0x51000008 Timer control TCNTB0 0x5100000C Timer count buffer 0 TCMPB0 0x51000010 Timer compare buffer 0 TCNTO0 0x51000014 Timer count observation 0 TCNTB1 0x51000018 Timer count buffer 1 TCMPB1 0x5100001C Timer compare buffer 1...
Page 70 PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR Acc. Read/ Register Name Address Reset Value Function Unit Write 0x4980_002C Endpoints Status Register 0x4980_0030 Endpoints Control Register BRCR 0x4980_0034 Byte Read Count Register BWCR 0x4980_0038 Byte Write Count Register 0x4980_003C Max Packet Register 0x4980_0040 DMA Control Register DTCR 0x4980_0044...
Page 71 S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW Acc. Read/ Register Name Address Reset Value Function Unit Write GPCCON 0x56000020 Port C control GPCDAT 0x56000024 Port C data GPCUDP 0x56000028 0x55555555 Pull-up/down control C GPDCON 0x56000030 Port D control GPDDAT 0x56000034 Port D data GPDUDP 0x56000038 0x55555555...
Page 72 PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR Acc. Read/ Register Name Address Reset Value Function Unit Write EXTINT2 0x56000090 0x000000 External interrupt control register 2 EINTFLT2 0x5600009c 0x000000 External interrupt control register 2 EINTFLT3 0x560000a0 0x000000 External interrupt control register 3 EINTMASK 0x560000a4 0x00FFFFF0 External interrupt mask register...
Page 73 S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW Acc. Read/ Register Name Address Reset Value Function Unit Write ADCDAT0 0x5800000C ADC conversion data ADCDAT1 0x58000010 ADC conversion data ADCUPDN 0x58000014 Stylus up or down interrupt status ADCMUX 0x58000018 Analog input channel select HSSPI(SPI Channel 0) CH_CFG 0x52000000 0x40...
Page 74 PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR Acc. Read/ Register Name Address Reset Value Function Unit Write SWRST 0x4AC0002F 0x00000000 Software Reset Register NORINTSTS 0x4AC00030 0x00000000 ROC/ Normal Interrupt Status Register RW1C ERRINTSTS 0x4AC00032 0x00000000 ROC/ Error Interrupt Status Register RW1C NORINTSTSEN 0x4AC00034 0x00000000 Normal Interrupt Status Enable Register...
Page 75 S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW Acc. Read/ Register Name Address Reset Value Function Unit Write PWRCON 0x4A800029 0x00000000 Present State Register BLKGAP 0x4A80002A 0x00000000 Block Gap Control Register WAKCON 0x4A80002B 0x00000000 Wakeup Control Register CLKCON 0x4A80002C 0x00000000 Command Register TIMEOUTCON 0x4A80002E 0x00000000 Timeout Control Register...
Page 76 PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR Acc. Read/ Register Name Address Reset Value Function Unit Write AC_MICDATA 0x5B00001C AC97 MIC in channel FIFO data register PCM Audio Interface PCM_CTL0 0x5C000000 PCM0 Main Control PCM_CLKCTL0 0x5C000004 PCM0 Clock and Shift control PCM_TXFIFO0 0x5C000008 PCM0 TxFIFO write port PCM_RXFIFO0...
Page 77 S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW Acc. Read/ Register Name Address Reset Value Function Unit Write CW_RB_REG 0x4D408230 0x0000_0000 RightBottom coordinate of Clip Window. CW_RB_X_REG 0x4D408234 0x0000_0000 Right X coordinate of Clip Window. CW_RB_Y_REG 0x4D408238 0x0000_0000 Bottom Y coordinate of Clip Window. COORD0_REG 0x4D408300 0x0000_0000...
Page 78 PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR Acc. Read/ Register Name Address Reset Value Function Unit Write SRC_BASE_ADDR_REG 0x4D408730 0x0000_0000 Source Image Base Address register DEST_BASE_ADDR_REG 0x4D408734 0x0000_0000 Dest Image Base Address register (in most cases, frame buffer address) Cautions on S3C2416X Special Registers 1.
Page 79: Chapter 2 System Controller
400MHz, while the AHB blocks and the APB blocks operate on 133MHz and 66MHz, respectively. Thus, the power control of the ARM core is major issue to reduce the overall power dissipation in S3C2416, and IDLE mode is supported for this purpose. In IDLE mode, the ARM core is not operated until the external interrupts or internal interrupts.
Page 80: Block Diagram
SYSTEM CONTROLLER S3C2416X RISC MICROPROCESSOR 3 BLOCK DIAGRAM off-part alive-part Glue Glue Reset Reset Clock Control Clocks Power Generator ON/OFF Power Management Signal Power Management Masking Register Register Figure 2-1. System Controller Block Diagram Figure 2-1 shows the system controller block diagram. The system controller is divided into two blocks, which are the OFF block and the ON block.
Page 81: Functional Descriptions
In this section, the behavior will be described. RESET MANAGEMENT AND TYPES S3C2416 has four types of resets and reset controller in system controller can place the system into the predefined states with one of the following four resets.
Page 82: Watchdog Reset
SYSTEM CONTROLLER S3C2416X RISC MICROPROCESSOR POWER nRESET EXTCLK or XTIpll PLL is configured by S/W first time Clock Lock time disable VCO is adapte to new clock frequency output SYSCLK The logic is operarted by SYSCLK is FOUT EXTCLK or XTIpll Figure 2-2.
Page 83: Software Reset
7. Reset counter is expired then, internal reset signals and nRSTOUT are deasserted. WAKEUP RESET When S3C2416 is woken up from SLEEP mode by wakeup event, the wakeup reset is invoked. The detail description will be explained in the power management mode section.
Page 84: Clock Management
XTI clock source can be reference of PLL after oscillated at PAD. User can configure stabilization time by setting OSCSET register and ON/OFF when power-down mode by setting PWRCFG register. The clock generator consists of two PLLs (Phase-Locked-Loop) which generate the high-frequency clock signals required in S3C2416. OM[0]...
Page 85: Main Oscillator Circuit Examples
S3C2416X RISC MICROPROCESSOR SYSTEM CONTROLLER Table 2-3. Clock Source Selection for the EPLL CLKSRC[8] (register) CLKSRC[7] (register) OM[0] EPLL Reference Clock EXTCLK EXTCLK Table 2-4. PLL & Clock Generator Condition MPLLCAP : N/A Loop filter capacitance EPLLCAP : Typical 1.8nF 5% MPLL: 10 −...
Page 86: Pll (Phase-Locked-Loop)
CHANGE PLL SETTINGS IN NORMAL OPERATION During the operation of S3C2416 in NORMAL mode, if the user wants to change the frequency by writing the PMS value, the PLL lock time is automatically inserted. During the lock time, the clock is not supplied to the internal blocks in S3C2416.
Page 87: System Clock Control
SYSTEM CONTROLLER SYSTEM CLOCK CONTROL The ARMCLK is used for ARM926EJ core, the main CPU of S3C2416. The HCLK is the reference clock for internal AHB bus and peripherals such as the memory controller, the interrupt controller, LCD controller, the DMA, USB host block, System Controller, Power down controller and etc.
Page 88: Arm & Bus Clock Divide Ratio
ARM & BUS CLOCK DIVIDE RATIO The MSysClk is the base clock for S3C2416 system clock, such as ARMCLK, HCLK, PCLK, DDRCLK, etc. The Table 2-5 shows the clock division ratios between ARMCLK, HLCK and PCLK. This ratio is determined by ARMDIV, PREDIV, HCLKDIV and PCLKDIV bits of CLKDIV0 control register.
Page 89: Examples For Configuring Clock Regiter To Produce Specific Frequency Of Amba Clocks
S3C2416X RISC MICROPROCESSOR SYSTEM CONTROLLER EXAMPLES FOR CONFIGURING CLOCK REGITER TO PRODUCE SPECIFIC FREQUENCY OF AMBA CLOCKS. When PLL output frequency = 800MHz Target frqeuency ARMCLK = 400MHz, HCLK = 133MHz, PCLK = 66MHz, DDRCLK = 266MHz SSMCCLK = 66MHz Register value ARMDIV = 4’b0001, PREDIV = 2’b10,...
Page 90: Esysclk Control
SYSTEM CONTROLLER S3C2416X RISC MICROPROCESSOR Figure 2-9 shows EPLL and special clocks for various peripherals Figure 2-9. EPLL Based Clock Domain ESYSCLK CONTROL Clocks of the EPLL can be used for various peripherals. Each divider value is configured in CLKDIV1 register and all clocks are enabled or disabled by accessing SCLKCON register.
Page 91: Power Management
The power management block controls the system clocks by software for the reduction of power consumption in S3C2416. These schemes are related to PLL, clock control logic(ARMCLK, HCLK, PCLK) and wake-up signal. S3C2416 has four power-down modes. The following section describes each power management mode.
Page 92: Power Saving Modes
PLL locking-time is required to provide stabilized ARMCLK. Those time-waits are automatically inserted by the hardware of S3C2416. During these time-waits, the clock is not supplied to the internal logic circuitry. STOP mode Entering sequence is as follows 1.
Page 93 S3C2416X RISC MICROPROCESSOR SYSTEM CONTROLLER 6. System controller request memory controller to enter self refresh mode. It is for preserving contents in SDRAM. 7. System controller wait for self refresh acknowledge from memory controller. 8. After receiving the self-refresh acknowledge, system controller disables system clocks, and switches SYSCLK’s source to MPLL reference clock.
Page 94 SYSTEM CONTROLLER S3C2416X RISC MICROPROCESSOR 6.2.4 SLEEP MODE In the SLEEP Mode, all the clock sources are off and also the internal logic-power is not supplied except for the wake-up logic circuitry. In this mode, the static power-dissipation of internal logic can be minimized. SLEEP Mode Entering sequence is as follows.
Page 95: Entering Stop Mode And Exiting Stop Mode (Wake-Up)
S3C2416X RISC MICROPROCESSOR SYSTEM CONTROLLER Figure 2-11. Entering STOP Mode and Exiting STOP Mode (wake-up) 2-17...
Page 96: Entering Sleep Mode And Exiting Sleep Mode (Wake-Up)
SYSTEM CONTROLLER S3C2416X RISC MICROPROCESSOR SLEEP mode is initiated Wake-up event ARM Down Req. & Ack. ARMCLK BUS Down Req. & Ack. DRAM Self Refresh Req. & Ack. CKE (DRAM) SYSCLK PWR_EN Figure 2-12. Entering SLEEP Mode and Exiting SLEEP Mode (wake-up) 2-18...
Page 97: Wake-Up Event
SYSTEM CONTROLLER WAKE-UP EVENT When S3C2416 wakes up from the STOP Mode by an External Interrupt, a RTC alarm interrupt and other interrupts, the PLL is turned on automatically. The initial-state of S3C2416 after wake-up from the SLEEP Mode is almost the same as the Power-On-Reset state except for the contents of the external DRAM is preserved.
Page 98: Power Saving Mode Entering/Exiting Condition
SYSTEM CONTROLLER S3C2416X RISC MICROPROCESSOR POWER SAVING MODE ENTERING/EXITING CONDITION Table 2-8 shows that Power Saving mode state and Entering or Exiting condition. In general, the entering conditions are set by the main CPU. Pleas refer to power-related registers(PWRMODE, PWRCFG and WKUPSTAT) before adopting power saving scheme on your system.
Page 99: Register Descriptions
S3C2416X RISC MICROPROCESSOR SYSTEM CONTROLLER 7 REGISTER DESCRIPTIONS The system controller registers are divided into seven categories; clock source control, clock control, power management, reset control, system controller status, bus configuration, and misc. The following section will describe the behavior of the system controller. ADDRESS MAP Table 2-9 summarizes the address map of the system controller.
Page 100: Individual Register Descriptions
In general, an oscillator requires stabilization time. This register specifies the duration based on the reference clock. OSCSET Description Initial Value RESERVED [31:0] RESERVED 0x0000 Crystal oscillator settle-down wait time, this value is valid XTALWAIT [15:0] 0x8000 when s3c2416 is wakeup by stop mode 2-22...
Page 101 S3C2416X RISC MICROPROCESSOR SYSTEM CONTROLLER MPLLCON Description Initial Value RESERVED [31:26] 0x00 MPLLEN_STOP [25] MPLL ON/OFF in STOP mode. 0:OFF, 1:ON ONOFF [24] MPLL ON/OFF. 0:ON, 1:OFF MDIV [23:14] Main divider value of MPLL 0x215 RESERVED [13:11] PDIV [10:5] Pre-divider value of MPLL RESERVED [4:3] SDIV...
Page 102 SYSTEM CONTROLLER S3C2416X RISC MICROPROCESSOR EPLLCON Description Initial Value RESERVED [31:26] 0x00 EPLLEN_STOP [25] EPLL ON/OFF in STOP mode. 0:OFF, 1:ON ONOFF [24] EPLL ON/OFF. 0:ON, 1:OFF MDIV [23:16] EPLL main divider value 0x20 RESERVED [15:14] PDIV [13:8] EPLL pre-divider value RESERVED [7:3] 0x00...
Page 103: Clock Control Register (Clksrc, Clkdiv, Hclkcon, Pclkcon, And Sclkcon)
S3C2416X RISC MICROPROCESSOR SYSTEM CONTROLLER CLOCK CONTROL REGISTER (CLKSRC, CLKDIV, HCLKCON, PCLKCON, AND SCLKCON) The clock generator within the system controller has many dividers and MUXs to generate appropriate clocks. These clocks are controlled by the clock control registers as described in here. Register Address Description...
Page 104 SYSTEM CONTROLLER S3C2416X RISC MICROPROCESSOR The CLKSRC selects the source input of the clocks. CLKSRC Description Initial Value RESERVED [31:19] 0x0_0000 HS-SPI0 clock SELHSSPI0 [18] 0 = EPLL (divided), 1 = MPLL (divided) HSMMC1 clock SELHSMMC1 [17] 0 = EPLL (divided), 1 = EXTCLK HSMMC0 clock SELHSMMC0 [16]...
Page 105 S3C2416X RISC MICROPROCESSOR SYSTEM CONTROLLER The CLKDIV0 configures the division ratio of each clock generator. The operating speed of ARM can be slow to reduce the overall power dissipation, if software doest not require full operating performance. In this case, the power dissipation due to the ARM core can be reduced if the DVS field is ON.
Page 106 SYSTEM CONTROLLER S3C2416X RISC MICROPROCESSOR CLKDIV1 configures the clock ratio related on EPLL. CLKDIV1 Description Initial Value RESERVED [31:26] SPIDIV_0 [25:24] HS-SPI clock divider ratio, ratio = (SPIDIV +1) Display controller clock divider ratio, DISPDIV [23:16] ratio = (DISPDIV + 1) I2SDIV_0 [15:12] I2S0 clock divider ratio, ratio = (I2SDIV_0 + 1)
Page 107 S3C2416X RISC MICROPROCESSOR SYSTEM CONTROLLER The AHB and APB clocks are en/disabled by HCLKCON register. All reserved bits have 1 value at initial state. HCLKCON Description Initial Value RESERVED [31:21] 0x7FF [20] Enable HCLK into 2D DRAMC [19] Enable HCLK into DRAM controller SSMC [18] Enable HCLK into the SSMC block...
Page 108 SYSTEM CONTROLLER S3C2416X RISC MICROPROCESSOR The special clocks are controlled by SCLKCON register. Some blocks in the device require several operating frequencies, i.e., 48 MHz and 24 MHz for USB interface block. Thus, these output frequencies can be controlled by the CLKDIV values. Initial SCLKCON Description...
Page 109: Power Management Registers (Pwrmode And Pwrcfg)
Power management configuration register 0x0000_0000 S3C2416 consists of three power-down modes, which are IDLE, (Deep)STOP, and SLEEP. The mode transition from the NORMAL mode occurs when the appropriate value is written into PWRMODE & PWRCFG register. If software tries to write illegal value, i.e., tries to set multiple power modes concurrently, then the write operation will be ignored.
Page 110 SYSTEM CONTROLLER S3C2416X RISC MICROPROCESSOR PWRCFG Description Initial Value Configure RTC alarm interrupt wakeup mask 0 = Wake-up signal event is generated when RTC alarm RTC_CFG occurs. 1 = Mask RTC alarm interrupt Configure RTC Tick interrupt wakeup mask RTCTICK_CFG 0 = wake-up signal event is generated when RTC Tick occurs.
Page 111: Reset Control Registers (Swrst And Rstcon)
S3C2416X RISC MICROPROCESSOR SYSTEM CONTROLLER RESET CONTROL REGISTERS (SWRST AND RSTCON) Software can reset S3C2416 using SWRST register. The waveform of the reset signals are determined by RSTCON register. Register Address Description Reset Value SWRST 0x4C00_0044 Software reset control register...
Page 112: Control Of Retention Pad(I/O) When Normal Mode And Wake-Up From Sleep Mode
Figure 2-13. Usage of PWROFF_SLP S3C2416 has a lot of retention PADs. Retention pad’s ability is remaining data when internal logic power is off. In normal mode, PWROFF_SLP signal which from RSTCON register can control about PAD output. If SLP_IN signal has LOW value, data assigned to specific PAD go out through level shifter and latch.
Page 113: System Controller Status Registers (Wkupstat And Rststat)
0x0000_0000 After S3C2416 is re-set or woken-up, the following two registers store the source of the activation. The value of RSTSTAT register is cleared by the other reset. If each bit has ‘1’ value, resets or wakeup events are occurred.
Page 114: Bus Configuration Register (Buspri0, Buspri1, And Busmisc)
Bus priority control register 0 0x0000_0000 S3C2416 consists of 2 hierarchical AHB buses. The arbitration priority and order can be configured with BUSPRI0 registers. You can see specific priority number that assigned to each AMBA master in User’s Manual section ‘04- BUS PRIORITIES’.
Page 115: Information Register 0,1,2,3
S3C2416X RISC MICROPROCESSOR SYSTEM CONTROLLER Initial BUSPRI0 Description Value Fixed priority order for AHB-I bus Value Priority Value Priority [2:0] 3’b000 0-1-2-3-4-5-6-7 3’b100 4-5-6-0-1-2-3-7 ORDER_I 3’b001 1-2-3-4-5-6-0-7 3’b101 5-6-0-1-2-3-4-7 3’b010 2-3-4-5-6-0-1-7 3’b110 6-0-1-2-3-4-5-7 3’b011 3-4-5-6-0-1-2-7 3’b111 undefined INFORMATION REGISTER 0,1,2,3 Register Address Description...
Page 116: Usb Phy Control Register (Phyctrl)
SYSTEM CONTROLLER S3C2416X RISC MICROPROCESSOR USB PHY CONTROL REGISTER (PHYCTRL) Register Address Description Reset Value PHYCTRL 0x4C00_0080 USB2.0 PHY Control Register 0x0000_0000 PHYCTRL Description Initial State RESERVED [31:6] CLK_ON_OFF Clock input on off control at pad input area Should be use with EXT_CLK [2]. When Combination of [5],[2] bit is 2’b11 , could be off clock input.
Page 117: Usb Phy Power Control Register (Phypwr)
S3C2416X RISC MICROPROCESSOR SYSTEM CONTROLLER 8.10 USB PHY POWER CONTROL REGISTER (PHYPWR) Register Address Description Reset Value PHYPWR 0x4C00_0084 USB2.0 PHY Power Control Register 0x0000_0000 PHYCTRL Description Initial State RESERVED [31:6] Must be zero RESERVED [5:4] Must be 0x3 2’b00 RESERVED [3:1] Must be zero...
Page 118: Usb Clock Control Register (Uclkcon)
SYSTEM CONTROLLER S3C2416X RISC MICROPROCESSOR 8.12 USB CLOCK CONTROL REGISTER (UCLKCON) Register Address Description Reset Value UCLKCON 0x4C00_008C USB Clock Control Register 0x0000_0000 MSINTEN Description Initial State DETECT_VBUS [31] VBUS Detect This VBUS indicator signal indicates that the VBUS signal on the USB cable is active.
Page 119: Bus Matrix & Ebi
(SDRAM, SRAM, Flash Memory, ROM etc) from different AHB bus (one is for system and the other is for image) at the same time. S3C2416 have two MATRIX cores because it has two memory ports, and each MATRIX can select the priority between rotation type and fixed type.
Page 120: Special Function Registers
BUS MATRIX & EBI S3C2416X RISC MICROPROCESSOR 2 SPECIAL FUNCTION REGISTERS MATRIX CORE 0 PRIORITY REGISTER (BPRIORITY0) Register Address Description Reset Value BPRIORITY0 0X4E800000 Matrix Core 0 priority control register 0x0000_0004 BPRIORITY0 Description Initial State PRI_TYP Priority type 0 = Fixed Type 1 = Rotation Type FIX_PRI_TYP Priority for the fixed priority type...
Page 121: Ebi Control Register (Ebicon)
S3C2416X RISC MICROPROCESSOR BUS MATRIX & EBI EBI CONTROL REGISTER (EBICON) Register Address Description Reset Value EBICON 0X4E800008 EBI control register 0x0000_0004 EBICON Description Initial State Reserved [31:9] Should be ‘0’ BANK1_CFG Bank1 Configuration 0: SROM 1:NAND PRI_TYP Priority type 0: Fixed Type 1: Rotation Type FIX_PRI_TYP...
Page 122 BUS MATRIX & EBI S3C2416X RISC MICROPROCESSOR NOTES...
Page 123: Bus Priorities
BUS PRIORITY MAP The S3C2416 holds 16 masters on the AHB_S(System Bus), 9 masters on the AHB_I(Image Bus) and 9masters on the APB Bus. The following list shows the priorities among these bus masters after a reset.
Page 124 BUS PRIORITIES S3C2416X RISC MICROPROCESSOR Priority AHB_I BUS MASTERS Comment Reserved 1. Fix Type: all priority can be changed according to register value stored in The System Controller. TFTW1-LCD TFTW2-LCD 2 Rotation Type : all masters’ priority can be rotatable according to Reserved register value stored in The System Controller.
Page 125: Static Memory Controller (Smc)
S3C2416X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER STATIC MEMORY CONTROLLER (SMC) 1 OVERVIEW The SMC provides simultaneous support for up to six memory banks (bank0 to bank5) that you can configure independently. Each memory bank supports: • SRAM • • Flash EPROM •...
Page 126: Feature
STATIC MEMORY CONTROLLER S3C2416X RISC MICROPROCESSOR 2 FEATURE • Supports asynchronous static memory-mapped devices including RAM, ROM, OneNAND and flash • Supports synchronous static memory-mapped devices including synchronous burst flash • Supports asynchronous page mode read operation in non-clocked memory subsystems •...
Page 127: Block Diagram
S3C2416X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER 3 BLOCK DIAGRAM SMC Core Memory Control Signals AHB Slave Interface Interface AHB Slave Interface Data and Address Bus Data bus Interface Figure 5-1. SMC Block Diagram nWAIT Synchronizer Module SMCANCELWAIT AHB Slave AHB I/F Interface for Control for SMC SFR...
Page 128: Asynchronous Read
STATIC MEMORY CONTROLLER S3C2416X RISC MICROPROCESSOR ASYNCHRONOUS READ Figure 5-3 shows an external memory read transfer with two output enable delay states, WSTOEN = 2, and two wait states, WSTRD = 2. Four AHB wait states are inserted during the transfer, two for the standard read, and additional two because of the programmed wait states added.
Page 129: Read Timing Diagram (Drncs = 1, Drnowe = 1)
S3C2416X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER SMCLK ADDR nWAIT DATA ( R ) D(A) Figure 5-5. Read Timing Diagram (DRnCS = 1, DRnOWE = 1)
Page 130: Asynchronous Burst Read
STATIC MEMORY CONTROLLER S3C2416X RISC MICROPROCESSOR ASYNCHRONOUS BURST READ The SMC supports sequential access asynchronous burst reads to four or eight consecutive locations in 8 or 16- bit memories, as set using the BurstLenRead bits of the Control Register SMBCRx. Burst mode is enabled by setting the Burst Mode bits, BMRead or BMWrite, in the Control register.
Page 131: Synchronous Read/Synchronous Burst Read
S3C2416X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER SYNCHRONOUS READ/SYNCHRONOUS BURST READ Single synchronous read operations have the same control signal timing as an asynchronous read operation, but with different timing requirements for setup and hold relative to the clock. Because the output signals of the SMC are generated internally from clocked logic, the timing for single synchronous reads is the same as for asynchronous reads.
Page 132: Asynchronous Write
STATIC MEMORY CONTROLLER S3C2416X RISC MICROPROCESSOR ASYNCHRONOUS WRITE You can program the delay between the assertion of the chip select and the write enable from 0-15 cycles using the WSTWEN bits of the Bank Write Enable Assertion Delay Control Register, SMBWSTWENRx. This reduces the power consumption for memories.
Page 133: Write Timing Diagram (Drncs = 1, Drnowe = 0)
S3C2416X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER SMCLK ADDR nWAIT DATA ( W ) D ( A ) Figure 5-9. Write Timing Diagram (DRnCS = 1, DRnOWE = 0) SMCLK ADDR nWAIT DATA ( W ) D ( A ) Figure 5-10. Write Timing Diagram (DRnCS = 1, DRnOWE = 1)
Page 134: Synchronous Write/ Synchronous Burst Write
STATIC MEMORY CONTROLLER S3C2416X RISC MICROPROCESSOR SYNCHRONOUS WRITE/ SYNCHRONOUS BURST WRITE Figure 5-11 shows an example synchronous write operation. In this example the signal SMADDRVALID provides a one-cycle pulse. This behavior is enabled by setting the SyncWriteDev bit in the SMBCRx register. You must also set the AddrValidWriteEn bit for synchronous write.
Page 135: Bus Turnaround
S3C2416X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER BUS TURNAROUND You can configure the SMC for each memory bank to use external bus turnaround cycles between read and write memory accesses. You can program the IDCY field for up to 15 bus turnaround wait states. This avoids bus contention on the external memory data bus.
Page 136 STATIC MEMORY CONTROLLER S3C2416X RISC MICROPROCESSOR 3.6.1 Scenario Examples ADDR<->CS: 3-cycle, CS<->OE: 4-cycle, CS<->WE: 5-cycle 5-12...
Page 137: Memory Interface With 8-Bit Sram (2Mb)
S3C2416X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER 3.6.2 SRAM Memory Interface Examples Figure 5-13. Memory Interface with 8-bit SRAM (2MB) Figure 5-14. Memory Interface with 16-bit SRAM (4MB) SRAM/ROM S3C2416 8bit data bus RADDR0 Addr. connection 16bit data bus RADDR0 5-13...
Page 138: Special Registers
STATIC MEMORY CONTROLLER S3C2416X RISC MICROPROCESSOR 4 SPECIAL REGISTERS BANK IDLE CYCLE CONTROL REGISTERS 0-5 Register Address Description Reset Value SMBIDCYR0 0x4F000000 Bank0 idle cycle control register SMBIDCYR1 0x4F000020 Bank1 idle cycle control register SMBIDCYR2 0x4F000040 Bank2 idle cycle control register SMBIDCYR3 0x4F000060 Bank3 idle cycle control register...
Page 139: Bank Write Wait State Control Registers 0-5
S3C2416X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER BANK WRITE WAIT STATE CONTROL REGISTERS 0-5 Register Address Description Reset Value SMBWSTWRR0 0x4F000008 Bank0 write wait state control register 0x1F SMBWSTWRR1 0x4F000028 Bank1 write wait state control register 0x1F SMBWSTWRR2 0x4F000048 Bank2 write wait state control register 0x1F SMBWSTWRR3 0x4F000068...
Page 140: Bank Write Enable Assertion Delay Control Registers 0-5
STATIC MEMORY CONTROLLER S3C2416X RISC MICROPROCESSOR BANK WRITE ENABLE ASSERTION DELAY CONTROL REGISTERS 0-5 Register Address Description Reset Value SMBWSTWENR0 0x4F000010 Bank0 write enable assertion delay control register SMBWSTWENR1 0x4F000030 Bank1 write enable assertion delay control register SMBWSTWENR2 0x4F000050 Bank2 write enable assertion delay control register SMBWSTWENR3 0x4F000070 Bank3 write enable assertion delay control register...
Page 141: Bank Control Registers 0-5
S3C2416X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER BANK CONTROL REGISTERS 0-5 Register Address Description Reset Value 0x4F000014 Bank0 control register SMBCR0 See note in p5-17 SMBCR1 0x4F000034 Bank1 control register 0x303000 0x4F000054 Bank2 control register 0x303010 SMBCR2 0x4F000074 Bank3 control register 0x303000 SMBCR3 0x4F000094...
Page 142 STATIC MEMORY CONTROLLER S3C2416X RISC MICROPROCESSOR Description Initial State BurstLen [11:10] Burst transfer length. Sets the number of sequential transfers Read that the burst device supports for a read: 00 = 4-transfer burst. 01 = 8-transfer burst. 10 = 16-transfer burst. 11 = Reserved Synchronous access capable device connected.
Page 143: Bank Onenand Type Selection Register
S3C2416X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER BANK ONENAND TYPE SELECTION REGISTER Register Address Description Reset Value SMBONETYPER 0x4F000100 SMC Bank OneNAND type selection register Description Initial State [31:6] Read undefined. BANK5TYPE 0 = DEMUXED OneNAND 1 = MUXED OneNAND BANK4TYPE 0 = DEMUXED OneNAND 1 = MUXED OneNAND BANK3TYPE...
Page 144: Smc Control Register
STATIC MEMORY CONTROLLER S3C2416X RISC MICROPROCESSOR SMC CONTROL REGISTER Register Address Description Reset Value SMCCR 0x4F000204 SMC control register Description Initial State [31:2] Read undefined. Write as zero. MemClkRatio Defines the ratio of SMCLK to HCLK: 0 = SMCLK = HCLK. 1 = SMCLK = HCLK/2.
Page 145: Mobile Dram Controller
MOBILE DRAM CONTROLLER 1 OVERVIEW The S3C2416 Mobile DRAM Controller supports three kinds of memory interface - (Mobile) SDRAM and mobile DDR and DDR2. Mobile DRAM controller provides 2 chip select signals (2 memory banks), these are used for up to 2 (mobile) SDRAM banks or 2 mobile DDR banks or 2 DDR2 banks.
Page 146: Block Diagram
MOBILE DRAM CONTROLLER S3C2416X RISC MICROPROCESSOR 2 BLOCK DIAGRAM Follow Figure 6-1 shows the block diagram of Mobile DRAM Controller Figure 6-1. Mobile DRAM Controller Block Diagram...
Page 147: Mobile Dram Initialization Sequence
S3C2416X RISC MICROPROCESSOR MOBILE DRAM CONTROLLER 3 MOBILE DRAM INITIALIZATION SEQUENCE On power-on reset, software must initialize the memory controller and the mobile DRAM connected to the controller. Refer to the mobile DRAM(SDRAM or mDDR or DDR2) data sheet for the start up procedure, and example sequences are given below: MOBILE DRAM(SDRAM OR MOBILE DDR) INITIALIZATION SEQUENCE 1.
Page 148: Memory Interface With 16-Bit Sdram (4Mx16, 4Banks)
MOBILE DRAM CONTROLLER S3C2416X RISC MICROPROCESSOR 3.2.1 (Mobile) SDRAM Memory Interface Examples DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM0 LDQM DQM1 UDQM nSCS nSCS0 SCKE SCKE nSRAS nSRASn SCLK SCLK nSCAS SCASn Figure 6-2. Memory Interface with 16-bit SDRAM (4Mx16, 4banks) DQ10 DQ10 DQ11...
Page 149: Memory Interface With 16-Bit Mobile Ddr And Ddr2
S3C2416X RISC MICROPROCESSOR MOBILE DRAM CONTROLLER 3.2.2 Mobile DDR (and DDR2) Memory Interface Examples DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM0 LDQM DQM1 UDQM nSCS nSCS0 DQS0 DQS0 nSRAS nSRASn DQS1 DQS1 nSCAS SCASn SCKE SCLK SCLKn Figure 6-4. Memory Interface with 16-bit Mobile DDR and DDR2...
Page 150: Dram Timing Diagram
MOBILE DRAM CONTROLLER S3C2416X RISC MICROPROCESSOR 3.2.3 Supported Programmable Timing Parameters Figure 6-5. DRAM Timing Diagram Figure 6-5 shows a timing diagram of DRAM. There are many timing parameters provided by DRAM. And DRAMC only provides some timing parameters to support various DRAM memories, like SDR, mobile DDR and DDR2.
Page 151: T Arfc Timing Diagram
S3C2416X RISC MICROPROCESSOR MOBILE DRAM CONTROLLER DRAMC also needs tARFC timing parameter to control of the timing for auto-refresh to CMD and self-refresh to CMD period. The Figure 6-7 shows the tARFC timing diagram. Figure 6-7. tARFC Timing Diagram...
Page 152: Mobile Dram Configuration Register
MOBILE DRAM CONTROLLER S3C2416X RISC MICROPROCESSOR MOBILE DRAM CONFIGURATION REGISTER Register Address Description Reset Value BANKCFG 0x48000000 Mobile DRAM configuration register 0x0000_000C BANKCFG Description Initial State Reserved [31:19] Reserved 0x0000 The bit width of RAS (row) address of bank 0 RASBW0 [18:17] 00 = 11-bit...
Page 153: Mobile Dram Control Register
S3C2416X RISC MICROPROCESSOR MOBILE DRAM CONTROLLER MOBILE DRAM CONTROL REGISTER Register Address Description Reset Value BANKCON1 0x48000004 Mobile DRAM control register 0x4400_0040 BANKCON Description Initial State DRAM controller status bit (read only) BUSY [31] 0 = IDLE 1 = BUSY DQSIn Delay selection DQSInDLL [30:28]...
Page 154: Mobile Dram Timming Control Register
MOBILE DRAM CONTROLLER S3C2416X RISC MICROPROCESSOR MOBILE DRAM TIMMING CONTROL REGISTER Register Address Description Reset Value BANKCON2 0x48000008 Mobile DRAM timing control register 0x0099_003F TIMECON Description Initial State Reserved [31:24] Reserved 0x00 Row active time 0000 = 1-clock 0001 = 2-clock 0010 = 3-clock 0011 = 4-clock tRAS [23:20] 1001b...
Page 155: Mobile Dram (Extended ) Mode Register Set Register
S3C2416X RISC MICROPROCESSOR MOBILE DRAM CONTROLLER MOBILE DRAM (EXTENDED ) MODE REGISTER SET REGISTER Register Address Description Reset Value BANKCON3 0x4800000C Mobile DRAM (E)MRS Register 0x8000_0003 3.6.1 mSDRAM / mDDR PnBANKCON Description Initial State [31:30] Bank address for EMRS Reserved [29:23] Should be ‘0’...
Page 156 MOBILE DRAM CONTROLLER S3C2416X RISC MICROPROCESSOR 3.6.2 DDR2 Memory MRS[15:0] and EMRS(1)[31:16] PnBANKCON Description Initial State [31:30] Bank address for EMRS Reserved [29] Should be ‘0’ 0 = Output buffer enable Qoff [28] 1 = Output buffer disable 0 = Disable RDQS [27] 1 = Enable...
Page 157 S3C2416X RISC MICROPROCESSOR MOBILE DRAM CONTROLLER 3.6.3 DDR2 Memory EMRS(2)[31:16] PnBANKCON Description Initial State [31:30] Bank address for EMRS Reserved [29:24] Should be ‘0’ 000000b High Temperature Self-Refresh Rate Enable [23] 0 = Disable 1 = Enable Reserved [22:20] Should be ‘0’ 000b 0 = Disable [19]...
Page 158: Mobile Dram Refresh Control Register
MOBILE DRAM CONTROLLER S3C2416X RISC MICROPROCESSOR MOBILE DRAM REFRESH CONTROL REGISTER Register Address Description Reset Value REFRESH 0x48000010 Mobile DRAM refresh control register 0x0000_0020 REFRESH Description Initial State Reserved [31:16] Reserved 0x0000 DRAM refresh cycle. Example: Refresh period is 15.6us, and HCLK is 66MHz. The REFCYC [15:0] 0x0020...
Page 159: Nand Flash Controller
NAND FLASH CONTROLLER 1 OVERVIEW S3C2416 boot code can be executed on an external NAND flash memory. The S3C2416 is equipped with an internal SRAM buffer called ‘Steppingstone’. This supports NAND flash boot loader. When you use IROM boot and select nand flash as boot device, first 8 KB of the NAND flash memory will be loaded in the Steppingstone by IROM and the boot code will be executed in the steppingstone.
Page 160: Block Diagram
NAND FLASH CONTROLLER S3C2416 RISC MICROPROCESSOR 3 BLOCK DIAGRAM nFCE ECC Gen. NAND FLASH Interface Control & State Machine I/O0 - I/O7 Slave I/F Stepping Stone Stepping Stone Controller (64KB SRAM) Figure 7-1. NAND Flash Controller Block Diagram 4 BOOT LOADER FUNCTION...
Page 161: Gpc5/6/7 Pin Configuration Table In Irom Boot Mode
S3C2416 RISC MICROPROCESSOR NAND FLASH CONTROLLER 5 GPC5/6/7 PIN CONFIGURATION TABLE IN IROM BOOT MODE Page Address Cycle GPC7 [2] GPC6 [1] GPC5 [0] MMC(MoviNAND/iNand) Reserved Nand 2048 4096 Above configuration is applicable when NAND Flash is used as booting memory in IROM boot mode. If NAND Flash is not used as boot memory, the configuration can be changed by setting NFCON SFR ’NFCONF’...
Page 162: Nand Flash Access
Figure 7-4. nWE & nRE Timing (TWRPH0=0, TWRPH1=0) Block Diagram 7 NAND FLASH ACCESS S3C2416 does not support NAND flash access mechanism directly. It only supports signal control mechanism for NAND flash access. Therefore software is responsible for accessing NAND flash memory correctly.
Page 163: Data Register Configuration
S3C2416 RISC MICROPROCESSOR NAND FLASH CONTROLLER 8 DATA REGISTER CONFIGURATION 8.1.1 8-bit NAND Flash Memory Interface Word Access Register Bit [31:24] Bit [23:16] Bit [15:8] Bit [7:0] I/O[ 7:0] I/O[ 7:0] I/O[ 7:0] I/O[ 7:0] NFDATA Half-word Access Register Bit [31:24]...
Page 164 NAND FLASH CONTROLLER S3C2416 RISC MICROPROCESSOR 10.1.1 1-BIT ECC Register Configuration Following tables shows the configuration of 1-bit ECC value read from spare area of external NAND flash memory. For comparing to ECC parity code generated by the H/W modules, each ECC data read from memory must be written to NFMECCDn for main area and NFSECCD for spare area.
Page 165: 1-Bit Ecc Programming Encoding And Decoding
S3C2416 RISC MICROPROCESSOR NAND FLASH CONTROLLER 10.2 1-BIT ECC PROGRAMMING ENCODING AND DECODING 1. To use 1-bit ECC in software mode, reset the ECCType to ‘0’ (enable 1-bit ECC)‘. ECC module generates ECC parity code for all read / write data when MainECCLock (NFCONT[7]) and SpareECCLock (NFCONT[6]) are unlocked(‘0’).
Page 166: 4-Bit Ecc Programming Guide (Decoding)
NAND FLASH CONTROLLER S3C2416 RISC MICROPROCESSOR 10.4 4-BIT ECC PROGRAMMING GUIDE (DECODING) 1. To use 4-bit ECC, set the MsgLength to 0(512-byte message length) and set the ECCType to ‘1’(enable 4-bit ECC). ECC module generates ECC parity code for 512-byte read data. So, you have to reset ECC value by writing the InitMECC (NFCONT[5]) bit as ‘1’...
Page 167: 8-Bit Ecc Programming Guide (Decoding)
S3C2416 RISC MICROPROCESSOR NAND FLASH CONTROLLER 4. To generate spare area ECC parity code, set the MsgLength to 1(24-byte message length), and set the ECCType to “01”(enable 8bit ECC). 8bit ECC module generates the ECC parity code for 24-byte data. In order to initiating the module, you have to write ‘1’...
Page 168: Memory Mapping(Nand Boot And Other Boot)
NAND FLASH CONTROLLER S3C2416 RISC MICROPROCESSOR 11 MEMORY MAPPING(NAND BOOT AND OTHER BOOT) SRAM SRAM (8KB) (8KB) 0x40000_0000 SDRAM SDRAM (nSCS1) (nSCS1) MPORT1 0x3800_0000 SDRAM SDRAM (nSCS0) (nSCS0) 0x3000_0000 SROM SROM (nRCS5) (nRCS5) 0x2800_0000 SROM SROM (nRCS4) (nRCS4) 0x2000_0000 SROM...
Page 169: Nand Flash Memory Configuration
S3C2416 RISC MICROPROCESSOR NAND FLASH CONTROLLER 12 NAND FLASH MEMORY CONFIGURATION Figure 7-6. A 8-bit NAND Flash Memory Interface Block Diagram NOTE: NAND CONTROLLER can support to control two nand flash memories . NAND CS Other BOOT nFCE NAND CONTROLLER CS0...
Page 170: Nand Flash Controller Special Registers
NAND FLASH CONTROLLER S3C2416 RISC MICROPROCESSOR 13 NAND FLASH CONTROLLER SPECIAL REGISTERS 13.1 NAND FLASH CONTROLLER REGISTER MAP Address Reset value Name Description Base + 0x00 0xX000_100X NFCONF Configuration register Base + 0x04 0x0001_00C6 NFCONT Control register Base + 0x08...
Page 171: Nand Flash Configuration Register
S3C2416 RISC MICROPROCESSOR NAND FLASH CONTROLLER 13.2 NAND FLASH CONFIGURATION REGISTER Register Address Description Reset Value NFCONF 0x4E000000 NAND Flash Configuration register 0xX000100X NFCONF Description Initial State Reserved [31] Reserved Reserved [30] Should be 0 Reserved [29:26] Reserved 0000 MsgLength...
Page 172 NAND FLASH CONTROLLER S3C2416 RISC MICROPROCESSOR NFCONF Description Initial State AddrCycle This bit indicates the number of Address cycle of NAND Flash H/W Set memory. (CfgAddrCycle) When Page Size is 512 Bytes, 0 = 3 address cycle 1 = 4 address cycle...
Page 173: Control Register
S3C2416 RISC MICROPROCESSOR NAND FLASH CONTROLLER 13.3 CONTROL REGISTER Register Address Description Reset Value NFCONT 0x4E000004 NAND Flash control register 0x000100C6 NFCONT Description Initial State Reserved [31:19] Reserved ECC Direction [18] 4-bit, 8-bitECC encoding / decoding control 0 = Decoding 4-bit, 8bit ECC, It is used for page read...
Page 174 NAND FLASH CONTROLLER S3C2416 RISC MICROPROCESSOR NFCONT Description Initial State EnbIllegalAccINT [10] Illegal access interrupt control 0 = Disable interrupt 1 = Enable interrupt Illegal access interrupt will occurs when CPU tries to program or erase locking area (the area setting in NFSBLK (0x4E000020) to NFEBLK (0x4E000024)).
Page 175: Command Register
S3C2416 RISC MICROPROCESSOR NAND FLASH CONTROLLER 13.4 COMMAND REGISTER Register Address Description Reset Value NFCMMD 0x4E000008 NAND Flash command set register 0x00 NFCMMD Description Initial State Reserved [31:8] Reserved 0x00 NFCMMD [7:0] NAND Flash memory command value 0x00 13.5 ADDRESS REGISTER...
Page 176: Main Data Area Ecc Register
NAND FLASH CONTROLLER S3C2416 RISC MICROPROCESSOR 13.7 MAIN DATA AREA ECC REGISTER Register Address Description Reset Value NFMECCD0 0x4E000014 0x00000000 NAND Flash ECC 1 register for main area data read Note: Refer to ECC Module Features. NFMECCD1 0x4E000018 0x00000000 NAND Flash ECC 3 register for main area data read Note: Refer to ECC Module Features.
Page 177: Progrmmable Block Address Register
S3C2416 RISC MICROPROCESSOR NAND FLASH CONTROLLER 13.9 PROGRMMABLE BLOCK ADDRESS REGISTER Register Address Description Reset Value NFSBLK 0x4E000020 NAND Flash programmable start block address 0x000000 NFEBLK 0x4E000024 NAND Flash programmable end block address 0x000000 Nand Flash can be programmed between start and end address.
Page 178: Softlock And Lock-Tight
NAND FLASH CONTROLLER S3C2416 RISC MICROPROCESSOR The NFSLK and NFEBLK can be changed while Soft lock bit(NFCONT[16]) is enabled. But cannot be changed when Lock-tight bit(NFCONT[17]) is set. NAND flash memory When NFSBLK > NFEBLK Address Locked area High (Read only)
Page 179: Nfcon Status Register
S3C2416 RISC MICROPROCESSOR NAND FLASH CONTROLLER 13.10 NFCON STATUS REGISTER Register Address Description Reset Value NFSTAT 0x4E000028 NAND Flash operation status register 0x0080001D NFSTAT Description Initial State Reserved [31:24] Read undefined 0x00 Reserved [23:7] Reserved 0x00 ECCDecDone When 4-bit ECC or 8-bit ECC decoding is finished, this value set and issue interrupt if enabled.
Page 180: Ecc0/1 Error Status Register
NAND FLASH CONTROLLER S3C2416 RISC MICROPROCESSOR 13.11 ECC0/1 ERROR STATUS REGISTER Register Address Description Reset Value NFECCERR0 0x4E00002C NAND Flash ECC Error Status register for I/O [7:0] 0xX0XX_XXXX NFECCERR1 0x4E000030 NAND Flash ECC Error Status register for I/O [7:0] 0x0000_0000 13.11.1 When ECCType is 1-bit ECC.
Page 181 S3C2416 RISC MICROPROCESSOR NAND FLASH CONTROLLER 13.11.2 When ECCType is 4-bit ECC. NFECCERR0 Description Initial State ECC Busy [31] Indicates the 4-bit ECC decoding engine is searching whether a error exists or not 0 = Idle 1 = Busy ECC Ready...
Page 182: Main Data Area Ecc0 Status Register
NAND FLASH CONTROLLER S3C2416 RISC MICROPROCESSOR 13.12 MAIN DATA AREA ECC0 STATUS REGISTER Register Address Description Reset Value NFMECC0 0x4E000034 NAND Flash ECC status register 0xXXXXXX NFMECC1 0x4E000038 NAND Flash ECC status register 0xXXXXXX 13.12.1 When ECCType is 1-bit ECC...
Page 183: Spare Area Ecc Status Register
S3C2416 RISC MICROPROCESSOR NAND FLASH CONTROLLER 13.13 SPARE AREA ECC STATUS REGISTER Register Address Description Reset Value NFSECC 0x4E00003C NAND Flash ECC register for I/O [7:0] 0xXXXXXX NFSECC Description Initial State Reserved [31:16] Reserved 0xXXXX SECC0_1 [15:8] Spare area ECC1 Status for I/O[7:0]...
Page 184: Ecc 0/1/2 For 8Bit Ecc Status Register
NAND FLASH CONTROLLER S3C2416 RISC MICROPROCESSOR 13.15 ECC 0/1/2 FOR 8BIT ECC STATUS REGISTER Register Address Description Reset Value NF8ECCERR0 0x4E00_0044 NAND Flash ECC Error Status register 0 0x4000_0000 NF8ECCERR1 0x4E00_0048 NAND Flash ECC Error Status register 1 0x0000_0000 NF8ECCERR2...
Page 185: 8Bit Ecc Main Data Ecc 0/1/2/3 Status Register
S3C2416 RISC MICROPROCESSOR NAND FLASH CONTROLLER 13.16 8BIT ECC MAIN DATA ECC 0/1/2/3 STATUS REGISTER Register Address Description Reset Value NFM8ECC0 0x4E00_0050 8bit ECC status register 0xXXXX_XXXX NFM8ECC1 0x4E00_0054 8bit ECC status register 0xXXXX_XXXX NFM8ECC2 0x4E00_0058 8bit ECC status register...
Page 186: 8Bit Ecc Error Pattern Register
NAND FLASH CONTROLLER S3C2416 RISC MICROPROCESSOR 13.17 8BIT ECC ERROR PATTERN REGISTER Register Address Description Reset Value NFMLC8BITPT0 0x4E00_0060 NAND Flash 8-bit ECC Error Pattern register0 for 0x0000_0000 data[7:0] NFMLC8BITPT1 0x4E00_0064 NAND Flash 8-bit ECC Error Pattern register1 for 0x0000_0000...
Page 187: Dma Controller
DMA CONTROLLER 1 OVERVIEW S3C2416 supports six-channel DMA (Bridge DMA or peripheral DMA) controller that is located between the system bus and the peripheral bus. Each channel of DMA controller can perform data movements between devices in the system bus and/or peripheral bus with no restrictions. In other words, each channel can handle the...
Page 188: Dma Request Sources
DMA CONTROLLER S3C2416X RISC MICROPROCESSOR 2 DMA REQUEST SOURCES Each channel of DMA controller can select one source among 27 DMA sources if H/W DMA request mode is selected by REQSEL register. (Note that if S/W request mode is selected, this DMA request sources have no meaning at all.) The 27 DMA sources for each channel are as follows.
Page 189: Dma Operation
S3C2416X RISC MICROPROCESSOR DMA CONTROLLER 3 DMA OPERATION The details of DMA operation can be explained using three-state FSM (finite state machine) as follows: State-1. As an initial state, it waits for the DMA request. If it comes, go to state-2. At this state, DMA ACK and INT REQ are 0.
Page 190: External Dma Dreq/Dack Protocol
3.1.1 Basic DMA Timing The DMA service means paired Reads and Writes cycles during DMA operation, which is one DMA operation. The Figure 8-1 shows the basic Timing in the DMA operation of the S3C2416. • The setup time and the delay time of XnXDREQ and XnXDACK are same in all the modes.
Page 191: Demand/Handshake Mode Comparison
S3C2416X RISC MICROPROCESSOR DMA CONTROLLER − Demand/Handshake Mode Comparison Related to the Protocol between XnXDREQ and XnXDACK These are two different modes related to the protocol between XnXDREQ and XnXDACK. Figure 8-2 shows the differences between these two modes i.e., Demand and Handshake modes. At the end of one transfer (Single/Burst transfer), DMA checks the state of double-synched XnXDREQ.
Page 192: Burst 4 Transfer Size
DMA CONTROLLER S3C2416X RISC MICROPROCESSOR 3.1.4 Transfer Size • There are two different transfer sizes; single and Burst 4. • DMA holds the bus firmly during the transfer of these chunk of data, thus other bus masters can not get the bus.
Page 193: Examples Of Possible Cases
S3C2416X RISC MICROPROCESSOR DMA CONTROLLER 3.2 EXAMPLES OF POSSIBLE CASES 3.2.1 Single service, Demand Mode, Single Transfer Size The assertion of XnXDREQ is need for every unit transfer (Single service mode), the operation continues while the XnXDREQ is asserted(Demand mode), and one pair of Read and Write(Single transfer size) is performed. XSCLK XnXDREQ XnXDREQ...
Page 194: Dma Special Registers
DMA CONTROLLER S3C2416X RISC MICROPROCESSOR 4 DMA SPECIAL REGISTERS There are 10 control registers for each DMA channel. (Since there are six channels, the total number of control registers is 60.) Seven of them are to control the DMA transfer, and other three are to see the status of DMA controller.
Page 195: Dma Initial Source Control Register (Disrcc)
S3C2416X RISC MICROPROCESSOR DMA CONTROLLER 4.2 DMA INITIAL SOURCE CONTROL REGISTER (DISRCC) Register Address Description Reset Value DISRCC0 0x4B000004 DMA0 Initial Source Control Register 0x00000000 DISRCC1 0x4B000104 DMA1 Initial Source Control Register 0x00000000 DISRCC2 0x4B000204 DMA2 Initial Source Control Register 0x00000000 DISRCC3 0x4B000304...
Page 196: Dma Initial Destination Register (Didst)
DMA CONTROLLER S3C2416X RISC MICROPROCESSOR 4.3 DMA INITIAL DESTINATION REGISTER (DIDST) Register Address Description Reset Value DIDST0 0x4B000008 DMA0 Initial Destination Register 0x00000000 DIDST1 0x4B000108 DMA1 Initial Destination Register 0x00000000 DIDST2 0x4B000208 DMA2 Initial Destination Register 0x00000000 DIDST3 0x4B000308 DMA3 Initial Destination Register 0x00000000 DIDST4 0x4B000408...
Page 197: Dma Initial Destination Control Register (Didstc)
S3C2416X RISC MICROPROCESSOR DMA CONTROLLER 4.4 DMA INITIAL DESTINATION CONTROL REGISTER (DIDSTC) Register Address Description Reset Value DIDSTC0 0x4B00000C DMA0 Initial Destination Control Register 0x00000000 DIDSTC1 0x4B00010C DMA1 Initial Destination Control Register 0x00000000 DIDSTC2 0x4B00020C DMA2 Initial Destination Control Register 0x00000000 DIDSTC3 0x4B00030C...
Page 198: Dma Control Register (Dcon)
DMA CONTROLLER S3C2416X RISC MICROPROCESSOR 4.5 DMA CONTROL REGISTER (DCON) Register Address Description Reset Value DCON0 0x4B000010 DMA0 Control Register 0x00000000 DCON1 0x4B000110 DMA1 Control Register 0x00000000 DCON2 0x4B000210 DMA2 Control Register 0x00000000 DCON3 0x4B000310 DMA3 Control Register 0x00000000 DCON4 0x4B000410 DMA4 Control Register 0x00000000...
Page 199 S3C2416X RISC MICROPROCESSOR DMA CONTROLLER DCONn Description Initial State transfer (single or burst of length four) DMA stops and waits for another DMA request. 1 = Whole service mode is selected in which one request gets atomic transfers to be repeated until the transfer count reaches to 0.
Page 200: Dma Status Register (Dstat)
DMA CONTROLLER S3C2416X RISC MICROPROCESSOR 4.6 DMA STATUS REGISTER (DSTAT) Register Address Description Reset Value DSTAT0 0x4B000014 DMA0 Count Register 000000h DSTAT1 0x4B000114 DMA1 Count Register 000000h DSTAT2 0x4B000214 DMA2 Count Register 000000h DSTAT3 0x4B000314 DMA3 Count Register 000000h DSTAT4 0x4B000414 DMA4 Count Register 000000h...
Page 201: Dma Current Source Register (Dcsrc)
S3C2416X RISC MICROPROCESSOR DMA CONTROLLER 4.7 DMA CURRENT SOURCE REGISTER (DCSRC) Register Address Description Reset Value DCSRC0 0x4B000018 DMA0 Current Source Register 0x00000000 DCSRC1 0x4B000118 DMA1 Current Source Register 0x00000000 DCSRC2 0x4B000218 DMA2 Current Source Register 0x00000000 DCSRC3 0x4B000318 DMA3 Current Source Register 0x00000000 DCSRC4 0x4B000418...
Page 202: Dma Mask Trigger Register (Dmasktrig)
DMA CONTROLLER S3C2416X RISC MICROPROCESSOR 4.9 DMA MASK TRIGGER REGISTER (DMASKTRIG) Register Address Description Reset Value DMASKTRIG0 0x4B000020 DMA0 Mask Trigger Register DMASKTRIG1 0x4B000120 DMA1 Mask Trigger Register DMASKTRIG2 0x4B000220 DMA2 Mask Trigger Register DMASKTRIG3 0x4B000320 DMA3 Mask Trigger Register DMASKTRIG4 0x4B000420 DMA4 Mask Trigger Register...
Page 203: Dma Requeset Selection Register (Dmareqsel)
S3C2416X RISC MICROPROCESSOR DMA CONTROLLER 4.10 DMA REQUESET SELECTION REGISTER (DMAREQSEL) Register Address Description Reset Value DMAREQSEL0 0x4B000024 DMA0 Request Selection Register DMAREQSEL1 0x4B000124 DMA1 Request Selection Register DMAREQSEL2 0x4B000224 DMA2 Request Selection Register DMAREQSEL3 0x4B000324 DMA3 Request Selection Register DMAREQSEL4 0x4B000424 DMA4 Request Selection Register...
Page 204 DMA CONTROLLER S3C2416X RISC MICROPROCESSOR NOTES 8-18...
Page 205: Interrupt Controller
INTERRUPT CONTROLLER 1 OVERVIEW The interrupt controller in the S3C2416 receives the request from 53 interrupt sources. These interrupt sources are provided by internal peripherals such as the DMA controller, the UART, IIC, and others. In these interrupt sources, the UARTn and EINTn interrupts are 'OR'ed to the interrupt controller.
Page 206: Interrupt Group Multiplexing Diagram
INTERRUPT CONTROLLER S3C2416X RISC MICROPROCESSOR The interrupt controller has two groups of interrupt sources, and first group has always higher priority than the other group. Actually, we made this interrupt controller using by two interrupt controllers. The nRIQ of ARM926EJ is connected with ‘AND’...
Page 207: Interrupt Controller Operation
1.1.3 Interrupt Pending Register The S3C2416 has two interrupt pending resisters: source pending register (SRCPND) and interrupt pending register (INTPND). These pending registers indicate whether or not an interrupt request is pending. When the interrupt sources request interrupt service, the corresponding bits of SRCPND register are set to 1, and at the same time, only one bit of the INTPND register is set to 1 automatically after arbitration procedure.
Page 208: Interrupt Sources
INTERRUPT CONTROLLER S3C2416X RISC MICROPROCESSOR 1.2 INTERRUPT SOURCES The interrupt controller supports 51 interrupt sources as shown in the table below. Sources Descriptions Arbiter Group NONE Reserved ARB11 NONE Reserved ARB11 NONE Reserved ARB11 NONE Reserved ARB11 NONE Reserved ARB10 NONE Reserved ARB10...
Page 209 S3C2416X RISC MICROPROCESSOR INTERRUPT CONTROLLER Sources Descriptions Arbiter Group INT_UART0 UART0 Interrupt (ERR, RXD, and TXD) ARB5 INT_IIC0 IIC 0 interrupt ARB4 INT_USBH USB Host interrupt ARB4 INT_USBD USB Device interrupt ARB4 INT_NAND NAND Flash Controller interrupt ARB4 INT_UART1 UART1 Interrupt (ERR, RXD, and TXD) ARB4 INT_SPI0 High speed SPI 0 interrupt...
Page 210: Interrupt Priority Generating Block
INTERRUPT CONTROLLER S3C2416X RISC MICROPROCESSOR 1.3 INTERRUPT PRIORITY GENERATING BLOCK The priority logic for 32 interrupt requests is composed of seven rotation based arbiters: six first-level arbiters and one second-level arbiter as shown in Figure 10-2 below. Figure 9-3. Priority Generating Block 10-6...
Page 211: Interrupt Priority
S3C2416X RISC MICROPROCESSOR INTERRUPT CONTROLLER 1.4 INTERRUPT PRIORITY We have two groups of arbiters. One group is ARBITER0~ARBITER5, and the other is ARMBITER6~ARBITER11. The former group has higher priority than the latter group. And priority of arbiters in each group can be set as below separately. Each arbiter can handle six interrupt requests based on the one bit arbiter mode control (ARB_MODE) and two bits of selection control signals (ARB_SEL) as follows: •...
Page 212: Interrupt Controller Special Registers
INTERRUPT CONTROLLER S3C2416X RISC MICROPROCESSOR 2 INTERRUPT CONTROLLER SPECIAL REGISTERS There are following control registers in the interrupt controller: source pending register, interrupt mode register, mask register, priority register, interrupt pending register, interrupt offset register, sub-source pending register and sub-mask register. All the interrupt requests from the interrupt sources are first registered in the source pending register.
Page 213 S3C2416X RISC MICROPROCESSOR INTERRUPT CONTROLLER Register Address Description Reset Value request. INTMOD 2 0X4A000044 R/W Interrupt mode regiseter for group 2. 0x00000000 0 = IRQ mode 1 = FIQ mode INTMSK2 0X4A000048 R/W Determine which interrupt source of group 2 is 0xFFFFFFFF masked.
Page 214: Source Pending (Srcpnd) Register
INTERRUPT CONTROLLER S3C2416X RISC MICROPROCESSOR 2.1 SOURCE PENDING (SRCPND) REGISTER The SRCPND register is composed of 32 bits each of which is related to an interrupt source. Each bit is set to 1 if the corresponding interrupt source generates the interrupt request and waits for the interrupt to be serviced. Accordingly, this register indicates which interrupt source is waiting for the request to be serviced.
Page 215 S3C2416X RISC MICROPROCESSOR INTERRUPT CONTROLLER SRCPND 1 Description Initial State INT_UART3 [18] 0 = Not requested, 1 = Requested INT_DMA [17] 0 = Not requested, 1 = Requested INT_LCD [16] 0 = Not requested, 1 = Requested INT_UART2 [15] 0 = Not requested, 1 = Requested INT_TIMER4 [14]...
Page 216: Interrupt Mode (Intmod) Register
INTERRUPT CONTROLLER S3C2416X RISC MICROPROCESSOR 2.2 INTERRUPT MODE (INTMOD) REGISTER This register is composed of 32 bits each of which is related to an interrupt source. If a specific bit is set to 1, the corresponding interrupt is processed in the FIQ (fast interrupt) mode. Otherwise, it is processed in the IRQ mode (normal interrupt).
Page 217 S3C2416X RISC MICROPROCESSOR INTERRUPT CONTROLLER INTMOD1 Description Initial State INT_WDT/AC97 0 = IRQ, 1 = FIQ INT_TICK 0 = IRQ, 1 = FIQ nBATT_FLT 0 = IRQ, 1 = FIQ Reserved 0 = IRQ, 1 = FIQ EINT8_15 0 = IRQ, 1 = FIQ EINT4_7 0 = IRQ,...
Page 218: Interrupt Mask (Intmsk) Register
INTERRUPT CONTROLLER S3C2416X RISC MICROPROCESSOR 2.3 INTERRUPT MASK (INTMSK) REGISTER This register also has 32 bits each of which is related to an interrupt source. If a specific bit is set to 1, the CPU does not service the interrupt request from the corresponding interrupt source (note that even in such a case, the corresponding bit of SRCPND register is set to 1).
Page 219 S3C2416X RISC MICROPROCESSOR INTERRUPT CONTROLLER INTMSK1 Description Initial State INT_TICK 0 = Service available, 1 = Masked nBATT_FLT 0 = Service available, 1 = Masked Reserved 0 = Service available, 1 = Masked EINT8_15 0 = Service available, 1 = Masked EINT4_7 0 = Service available, 1 = Masked...
Page 220: Interrupt Pending (Intpnd) Register
INTERRUPT CONTROLLER S3C2416X RISC MICROPROCESSOR 2.4 INTERRUPT PENDING (INTPND) REGISTER Each of the 32 bits in the interrupt pending register shows whether the corresponding interrupt request, which is unmasked and waits for the interrupt to be serviced, has the highest priority. Since the INTPND register is located after the priority logic, only one bit can be set to 1, and that interrupt request generates IRQ to CPU.
Page 221 S3C2416X RISC MICROPROCESSOR INTERRUPT CONTROLLER INTPND1 Description Initial State INT_UART3 [18] 0 = Not requested, 1 = Requested INT_DMA [17] 0 = Not requested, 1 = Requested INT_LCD [16] 0 = Not requested, 1 = Requested INT_UART2 [15] 0 = Not requested, 1 = Requested INT_TIMER4 [14]...
Page 222: Interrupt Offset (Intoffset) Register
INTERRUPT CONTROLLER S3C2416X RISC MICROPROCESSOR 2.5 INTERRUPT OFFSET (INTOFFSET) REGISTER The value in the interrupt offset register shows, which interrupt request of IRQ mode is in the INTPND register. This bit can be cleared automatically by clearing SRCPND and INTPND. Register Address Description...
Page 223 S3C2416X RISC MICROPROCESSOR INTERRUPT CONTROLLER INT Source for group 2 The OFFSET Value INT Source for group 2 The OFFSET Value Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT_2D NOTE: FIQ mode interrupt does not affect the INTOFFSET register as the register is available only for IRQ mode interrupt. 10-19...
Page 224: Sub Source Pending (Subsrcpnd) Register
INTERRUPT CONTROLLER S3C2416X RISC MICROPROCESSOR 2.6 SUB SOURCE PENDING (SUBSRCPND) REGISTER You can clear a specific bit of the SUBSRCPND register by writing a data to this register. It clears only the bit positions of the SUBSRCPND register corresponding to those set to one in the data. The bit positions corresponding to those that are set to 0 in the data remains as they are.
Page 225 S3C2416X RISC MICROPROCESSOR INTERRUPT CONTROLLER SUBSRCPND Description SRCPND Initial State SUBINT_ERR1 0 = Not requested, 1 = Requested INT_UART1 SUBINT_TXD1 0 = Not requested, 1 = Requested SUBINT_RXD1 0 = Not requested, 1 = Requested SUBINT_ERR0 0 = Not requested, 1 = Requested INT_UART0 SUBINT_TXD0...
Page 226: Interrupt Sub Mask (Intsubmsk) Register
INTERRUPT CONTROLLER S3C2416X RISC MICROPROCESSOR 2.7 INTERRUPT SUB MASK (INTSUBMSK) REGISTER This register has 27 bits each of which is related to an interrupt source. If a specific bit is set to 1, the interrupt request from the corresponding interrupt source is not serviced by the CPU (note that even in such a case, the corresponding bit of the SUBSRCPND register is set to 1).
Page 227 S3C2416X RISC MICROPROCESSOR INTERRUPT CONTROLLER INTSUBMASK Description INTMASK Initial State SUBINT_RXD2 0 = Service available, 1 = Masked SUBINT_ERR1 0 = Service available, 1 = Masked INT_UART1 SUBINT_TXD1 0 = Service available, 1 = Masked SUBINT_RXD1 0 = Service available, 1 = Masked SUBINT_ERR0 0 = Service available, 1 = Masked INT_UART0...
Page 228: Priority Mode Register (Priority_Mode)
INTERRUPT CONTROLLER S3C2416X RISC MICROPROCESSOR 2.8 PRIORITY MODE REGISTER (PRIORITY_MODE) Register Address Description Reset Value PRIORITY_MODE1 0x4A000030 IRQ priority mode register 0x00000000 PRIORITY_MODE2 0x4A000070 IRQ priority mode register 0x00000000 PRIORITY_MODE1 Description Initial State ARB_MODE6 [27] Arbiter 6 group priority mode selection 0 = Fixed ends &...
Page 229 S3C2416X RISC MICROPROCESSOR INTERRUPT CONTROLLER PRIORITY_MODE1 Description Initial State ARB_MODE3 [15] Arbiter 3 group priority mode selection 0 = Fixed ends & Rotate middle 1 = Rotate all ARB_SEL3 [14:12] Arbiter 3 group priority order set ARB_MODE3 = 1’b0 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5...
Page 230 INTERRUPT CONTROLLER S3C2416X RISC MICROPROCESSOR PRIORITY_MODE1 Description Initial State 101 = REQ 5-0-1-2-3-4 ARB_MODE0 Arbiter 0 group priority mode selection 0 = Fixed ends & Rotate middle ARB_SEL0 [2:0] Arbiter 0 group priority order set ARB_MODE0 = 1’b0 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5...
Page 231 S3C2416X RISC MICROPROCESSOR INTERRUPT CONTROLLER PRIORITY_MODE2 Description Initial State ARB_MODE13 [27] Arbiter 13 group priority mode selection 0 = Fixed ends & Rotate middle 1 = Rotate all ARB_SEL13 [26:24] Arbiter 13 group priority order set ARB_MODE13 = 1’b0 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5...
Page 232 INTERRUPT CONTROLLER S3C2416X RISC MICROPROCESSOR PRIORITY_MODE2 Description Initial State ARB_MODE10 = 1’b0 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 ARB_MODE10 = 1’b1 000 = REQ 0-1-2-3-4-5 001 = REQ 1-2-3-4-5-0 010 = REQ 2-3-4-5-0-1 011 = REQ 3-4-5-0-1-2 100 = REQ 4-5-0-1-2-3 101 = REQ 5-0-1-2-3-4...
Page 233: Priority Update Register (Priority_Update)
S3C2416X RISC MICROPROCESSOR INTERRUPT CONTROLLER PRIORITY_MODE2 Description Initial State ARB_SEL7 [2:0] Arbiter 7 group priority order set ARB_MODE7 = 1’b0 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 2.9 PRIORITY UPDATE REGISTER (PRIORITY_UPDATE) Register Address Description...
Page 234 INTERRUPT CONTROLLER S3C2416X RISC MICROPROCESSOR PRIORITY_UPDATE2 Description Initial State ARB_UPDATE13 Arbiter 13 group priority rotate enable 0 = Priority does not rotate 1 = Priority rotate enable ARB_UPDATE12 Arbiter 12 group priority rotate enable 0 = Priority does not rotate 1 = Priority rotate enable ARB_UPDATE11 Arbiter 11 group priority rotate enable...
Page 235: Chapter 10 I/O Ports
S3C2416 RISC MICROPROCESSOR I/O PORTS I/O PORTS 1 OVERVIEW S3C2416X has 138 multi-functional input/output port pins and there are 11 ports as shown below: • Port A(GPA) : 25-output port • Port B(GPB) : 9-input/output port Port C(GPC) : 16-input/output port •...
Page 236 I/O PORTS S3C2416 RISC MICROPROCESSOR Table 10-1. S3C2416X Port Configuration (Sheet 1) Port A Selectable Pin Functions GPA27 Output only Reserved − − GPA26 Output only DQM3 − − GPA25 Output only DQM2 − − GPA24 Output only RSMAVD −...
Page 237 S3C2416 RISC MICROPROCESSOR I/O PORTS Table 10-1. S3C2416X Port Configuration (Sheet 2) (Continued) Port B Selectable Pin Functions GPB10 Input/output nXDREQ0 XDREQ0 I2SSDO_2 GPB9 Input/output nXDACK0 XDACK0 I2SSDO_1 Reserved Input/output Reserved Reserved Reserved Reserved Input/output Reserved Reserved Reserved GPB6 Input/output...
Page 238 I/O PORTS S3C2416 RISC MICROPROCESSOR Table 10-1. S3C2416X Port Configuration (Sheet 3) (Continued) Port D Selectable Pin Functions GPD15 Input/output RGB_VD23 − − GPD14 Input/output RGB_VD22 − − GPD13 Input/output RGB_VD21 − − GPD12 Input/output RGB_VD20 − − GPD11 Input/output RGB_VD19 −...
Page 239 S3C2416 RISC MICROPROCESSOR I/O PORTS Table 10-1. S3C2416X Port Configuration (Sheet 4) (Continued) Port F Selectable Pin Functions GPF7 Input/output EINT7 − − GPF6 Input/output EINT6 − − GPF5 Input/output EINT5 − − GPF4 Input/output EINT4 − − GPF3 Input/output EINT3 −...
Page 240 I/O PORTS S3C2416 RISC MICROPROCESSOR Table 10-1. S3C2416X Port Configuration (Sheet 5) (Continued) Port H Selectable Pin Functions GPH14 Input/output CLKOUT1 − − GPH13 Input/output CLKOUT0 − − GPH12 Input/output EXTUARTCLK − − GPH11 Input/output nRTS1 − − GPH10 Input/output nCTS1 −...
Page 241 S3C2416 RISC MICROPROCESSOR I/O PORTS Table 10-1. S3C2416X Port Configuration (Sheet7) (Continued) Port L Selectable Pin Functions Reserved Reserved Input/output − − GPL13 Input/output − − Reserved Reserved Input/output − − Reserved Input/output Reserved − − Reserved Input/output Reserved −...
Page 242: Port Control Descriptions
I/O PORTS S3C2416 RISC MICROPROCESSOR 2 PORT CONTROL DESCRIPTIONS 2.1 PORT CONFIGURATION REGISTER (GPACON-GPMCON) In S3C2416X, most of the pins are multiplexed pins. So, It is determined which function is selected for each pins. The GPxCON(port control register) determines which function is used for each pin.
Page 243: O Port Control Register
S3C2416 RISC MICROPROCESSOR I/O PORTS 3 I/O PORT CONTROL REGISTER 3.1 PORT A CONTROL REGISTERS (GPACON, GPADAT) Register Address Description Reset Value GPACON 0x56000000 Configures the pins of port A 0x0fffffff GPADAT 0x56000004 The data register for port A Reserved 0x56000008 −...
Page 244 I/O PORTS S3C2416 RISC MICROPROCESSOR GPADAT Description Reserved [31:27] Reserved GPA[27:0] [26:0] When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
Page 245: Port B Control Registers (Gpbcon, Gpbdat, Gpbudp, Gpbsel)
S3C2416 RISC MICROPROCESSOR I/O PORTS 3.2 PORT B CONTROL REGISTERS (GPBCON, GPBDAT, GPBUDP, GPBSEL) Register Address Description Reset Value GPBCON 0x56000010 Configures the pins of port B GPBDAT 0x56000014 The data register for port B GPBUDP 0x56000018 Pull-up/down control register for port B...
Page 246 I/O PORTS S3C2416 RISC MICROPROCESSOR GPBUDP Description Reserved [31:22] Reserved GPBUDP10 [21:20] [CPU:CPD] 00 = pull-up/down disable GPBUDP0 [1:0] 01 = pull-down enable 10 = pull-up enable 11 = not-available GPBSEL Description Reserved [31:5] Reserved GPB10SEL 0 = GPB10 1 = I2SSDO_2...
Page 247: Port C Control Registers (Gpccon, Gpcdat, Gpcudp)
S3C2416 RISC MICROPROCESSOR I/O PORTS 3.3 PORT C CONTROL REGISTERS (GPCCON, GPCDAT, GPCUDP) Register Address Description Reset Value GPCCON 0x56000020 Configures the pins of port C GPCDAT 0x56000024 The data register for port C GPCUDP 0x56000028 Pull-up/down control for port C...
Page 248 I/O PORTS S3C2416 RISC MICROPROCESSOR GPCDAT Description Reserved [31:16] Reserved GPC[15:0] [15:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 249: Port D Control Registers (Gpdcon, Gpddat, Gpdudp)
S3C2416 RISC MICROPROCESSOR I/O PORTS 3.4 PORT D CONTROL REGISTERS (GPDCON, GPDDAT, GPDUDP) Register Address Description Reset Value GPDCON 0x56000030 Configures the pins of port D GPDDAT 0x56000034 The data register for port D GPDUDP 0x56000038 Pull-up/down control register for port D...
Page 250 I/O PORTS S3C2416 RISC MICROPROCESSOR GPDDAT Description Reserved [31:16] Reserved GPD[15:0] [15:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 251: Port E Control Registers (Gpecon, Gpedat, Gpeudp, Gpesel)
S3C2416 RISC MICROPROCESSOR I/O PORTS 3.5 PORT E CONTROL REGISTERS (GPECON, GPEDAT, GPEUDP, GPESEL) Register Address Description Reset Value GPECON 0x56000040 Configures the pins of port E GPEDAT 0x56000044 The data register for port E GPEUDP 0x56000048 Pull-up/down control register for port E...
Page 252 I/O PORTS S3C2416 RISC MICROPROCESSOR GPEDAT Description Reserved [31:16] Reserved GPE[15:0] [15:0] When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit.
Page 253: Port F Control Registers (Gpfcon, Gpfdat, Gpfudp)
S3C2416 RISC MICROPROCESSOR I/O PORTS 3.6 PORT F CONTROL REGISTERS (GPFCON, GPFDAT, GPFUDP) If GPF0 − GPF7 will be used for wake-up signals from Sleep/Stop/Deep Stop mode, the ports will be set in EINT. Register Address Description Reset Value GPFCON...
Page 254: Port G Control Registers (Gpgcon, Gpgdat, Gpgudp)
I/O PORTS S3C2416 RISC MICROPROCESSOR 3.7 PORT G CONTROL REGISTERS (GPGCON, GPGDAT, GPGUDP) If GPG0–GPG7 will be used for wake-up signals from Sleep/Stop/Deep Stop mode, the ports will be set in EINT. Register Address Description Reset Value GPGCON 0x56000060 Configures the pins of port G...
Page 255 S3C2416 RISC MICROPROCESSOR I/O PORTS GPGDAT Description Reserved [31:8] Reserved GPG[7:0] [7:0] When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit.
Page 256: Port H Control Registers (Gphcon, Gphdat, Gphudp)
I/O PORTS S3C2416 RISC MICROPROCESSOR 3.8 PORT H CONTROL REGISTERS (GPHCON, GPHDAT, GPHUDP) Register Address Description Reset Value GPHCON 0x56000070 Configures the pins of port H GPHDAT 0x56000074 The data register for port H GPHUDP 0x56000078 pull-up/down control register for port H...
Page 257 S3C2416 RISC MICROPROCESSOR I/O PORTS GPHDAT Description Reserved [31:15] Reserved GPH[14:0] [14:0] When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit.
Page 258: Port K Control Registers (Gpkcon, Gpkdat, Gpkudp)
I/O PORTS S3C2416 RISC MICROPROCESSOR 3.9 PORT K CONTROL REGISTERS (GPKCON, GPKDAT, GPKUDP) Register Address Description Reset Value GPKCON 0x560000e0 Configures the pins of port K 0xaaaaaaaa GPKDAT 0x560000e4 The data register for port K GPKUDP 0x560000e8 pull-up/down control register for port K...
Page 259 S3C2416 RISC MICROPROCESSOR I/O PORTS GPKDAT Description GPK[15:0] [31:0] When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit.
Page 260: Port L Control Registers (Gplcon, Gpldat, Gpludp, Gplsel)
I/O PORTS S3C2416 RISC MICROPROCESSOR 3.10 PORT L CONTROL REGISTERS (GPLCON, GPLDAT, GPLUDP, GPLSEL) Register Address Description Reset Value GPLCON 0x560000f0 Configures the pins of port L GPLDAT 0x560000f4 The data register for port L GPLUDP 0x560000f8 pull-up/down control register for port L...
Page 261 S3C2416 RISC MICROPROCESSOR I/O PORTS GPLUDP Description Reserved [31:28] Reserved GPLUDP13 [27:26] [CPU:CPD] 00 = pull-up/down disable GPLUDP0 [1:0] 01 = pull-down enable 10 = pull-up enable 11 = not-available 10-27...
Page 262: Port M Control Registers (Gpmcon, Gpmdat, Gpmudp)
I/O PORTS S3C2416 RISC MICROPROCESSOR 3.11 PORT M CONTROL REGISTERS (GPMCON, GPMDAT, GPMUDP) Register Address Description Reset Value GPMCON 0x56000100 Configures the pins of port M GPMDAT 0x56000104 The data register for port M GPMUDP 0x560000108 pull-up/down control register for port M...
Page 263: Miscellaneous Control Register (Misccr)
S3C2416 RISC MICROPROCESSOR I/O PORTS 3.12 MISCELLANEOUS CONTROL REGISTER (MISCCR) In Sleep mode, the data bus(SD[15:0] or RD[15:0] can be set as Hi-Z and Output ‘0’ state. But, because of the characteristics of IO pad, the data bus pull-up/down resisters have to be turned on or off to reduce the power consumption.
Page 264: Dclk Control Registers (Dclkcon)
I/O PORTS S3C2416 RISC MICROPROCESSOR 3.13 DCLK CONTROL REGISTERS (DCLKCON) Register Address Description Reset Value DCLKCON 0x56000084 DCLK0/1 control register DCLKCON Description Reserved [31:28] Reserved DCLK1CMP [27:24] DCLK1 compare value clock toggle value. ( < DCLK1DIV) If the DCLK1CMP is n, Low level duration is( n + 1), High level duration is((DCLK1DIV + 1) –( n +1))
Page 265: Extintn (External Interrupt Control Register N)
S3C2416 RISC MICROPROCESSOR I/O PORTS 3.14 EXTINTn (External Interrupt Control Register n) The 8 external interrupts can be requested by various Signalling methods. The EXTINT register configures the Signalling method between the level trigger and edge trigger for the external interrupt request, and also configures the signal polarity.
Page 266 I/O PORTS S3C2416 RISC MICROPROCESSOR EXTINT0 Description EINT3 [14:12] Setting the signalling method of the EINT3. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Reserved...
Page 267 S3C2416 RISC MICROPROCESSOR I/O PORTS Reserved [19] Reserved EINT12 [18:16] Setting the signaling method of the EINT12. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered...
Page 268: Eintmask (External Interrupt Mask Register)
I/O PORTS S3C2416 RISC MICROPROCESSOR 3.15 EINTMASK (External Interrupt Mask Register) Register Address Description Reset Value EINTMASK 0x560000a4 External interrupt mask register 0x00fffff0 EINTMASK Description Reserved [31:24] Reserved Reserved [23] Reserved Reserved [22] Reserved Reserved [21] Reserved Reserved [20] Reserved...
Page 269: Eintpend (External Interrupt Pending Register)
S3C2416 RISC MICROPROCESSOR I/O PORTS 3.16 EINTPEND (External Interrupt Pending Register) Register Address Description Reset Value EINTPEND 0x560000a8 External interrupt pending register EINTPEND Description Reset Value Reserved [31:24] Reserved Reserved [23] Reserved Reserved Reserved [22] Reserved [21] Reserved Reserved Reserved...
Page 270: Gstatusn (General Status Registers)
I/O PORTS S3C2416 RISC MICROPROCESSOR 3.17 GSTATUSn (General Status Registers) Register Address Description Reset Value GSTATUS0 0x560000ac External pin status Not define GSTATUS1 0x560000b0 Software Platform ID register 0x32416X001 GSTATUS0 Description Reserved [31:4] Reserved nWAIT Status of nWAIT pin NCON...
Page 271: Dscn (Drive Strength Control)
S3C2416 RISC MICROPROCESSOR I/O PORTS 3.18 DSCn (Drive Strength Control) Control the Memory I/O drive strength Register Address Description Reset Value DSC0 0x560000c0 Strength control register 0 0x2aaa_aaaa DSC1 0x560000c4 Strength control register 1 0xaaa_aaaa DSC2 0x560000c8 Strength control register 2...
Page 272 I/O PORTS S3C2416 RISC MICROPROCESSOR DSC1 Description Reset Value Reserved [31:28] Reserved DSC_nSCLK [27:26] nSCLK drive strength. 00 = 4.9mA 01 = 9.8mA 10 = 14.8mA 11 = 19.7mA DSC_SCLK [25:24] SCLK drive strength. 00 = 4.9mA 01 = 9.8mA 10 = 14.8mA...
Page 273 S3C2416 RISC MICROPROCESSOR I/O PORTS DSC2 Description Reset Value Reserved [31:28] Reserved DSC_nFCE [27:26] nFCE drive strength. 00 = 5.2mA 01 = 10.5mA 10 = 15.7mA 11 = 21.0mA DSC_nFRE [25:24] nFRE drive strength. 00 = 5.2mA 01 = 10.5mA 10 = 15.7mA...
Page 274 I/O PORTS S3C2416 RISC MICROPROCESSOR DSC3 Description Reset Value Reserved [31:10] Reserved DSC_LCD2 [9:8] LCD_VD[23:16] drive strength. 00 = 2.6mA 01 = 5.2mA 10 = 7.8mA 11 = 10.5mA DSC_LCD1 [7:6] LCD_VD[15:8] drive strength. 00 = 2.6mA 01 = 5.2mA 10 = 7.8mA...
Page 275: Pddmcon (Power Down Sdram Control Register)
S3C2416 RISC MICROPROCESSOR I/O PORTS 3.19 PDDMCON (Power Down SDRAM Control Register) Register Address Description Reset Value PDDMCON 0x56000114 Memory I/F control register 0x00411540 PDDMCON Description Reset Value Reserved [31:24] Reserved nSCLK pin status (inactive :”1” ) PSC_nSCLK [23:22] 00 = output 0...
Page 276: Pdsmcon (Power Down Sram Control Register)
I/O PORTS S3C2416 RISC MICROPROCESSOR 3.20 PDSMCON (Power Down SRAM Control Register) Register Address Description Reset Value PDSMCON 0x56000118 Memory I/F control register 0x05451500 Description PDSMCON Reset Value Reserved [31:28] Reserved Reserved [27:26] Reserved Reserved [25:24] Reserved PSC_NF1 [23:22] nFCE/GPA[22], nFRE/GPA[20], nFWE/GPA[19] pin status (inactive : “1”)
Page 277 S3C2416 RISC MICROPROCESSOR I/O PORTS Description PDSMCON Reset Value RADDR[15:1] pin status (inactive : “0”) PSC_RADDRL [3:2] 00 = output 0 01 = output 1 10 = Hi-Z 11 = Not-Available RADDR[0]/GPA[0] pin status (inactive : “0”) PSC_RADDR0 [1:0] 00 = output 0...
Page 278: Gpio Alive & Sleep Part
I/O PORTS S3C2416 RISC MICROPROCESSOR 4 GPIO ALIVE & SLEEP PART Alive Sleep GPF[7:0], GPG[7:0] GPA, GPB, GPC, GPD, GPE, GPG[15:8], GPH, GPK, GPL ,GPM GPACON[27;0], GPADAT[27:0] All registers except alive SFR GPFCON[15;0], GPFDAT[7:0], GPFUDP[15:0] GP*CON, GP*DAT, GP*UDP GPGCONL[15:0], GPGDATL[7:0], GPGUDPL[15:0]...
Page 279: Chapter 11 Watchdog Timer
1 OVERVIEW The S3C2416 watchdog timer is used to resume the controller operation whenever it is disturbed by malfunctions such as noise and system errors. The watchdog timer generates the reset signal. It can be used as a normal 16- bit interval timer to request interrupt service.
Page 280: Watchdog Timer Operation
WATCHDOG TIMER S3C2416X RISC MICROPROCESSOR 2 WATCHDOG TIMER OPERATION 2.1 BLOCK DIAGRAM Figure 11-1 shows the functional block diagram of the watchdog timer. The watchdog timer uses only PCLK as its source clock. The PCLK frequency is prescaled to generate the corresponding watchdog timer clock, and the resulting frequency is divided again.
Page 281: Consideration Of Debugging Environment
2.3 CONSIDERATION OF DEBUGGING ENVIRONMENT When the S3C2416 is in debug mode using Embedded ICE, the watchdog timer must not operate. The watchdog timer can determine whether or not it is currently in the debug mode from the CPU core signal (DBGACK signal).
Page 282: Watchdog Timer Special Registers
0 = Disable the reset function of the watchdog timer. NOTE: Initial state of ‘Reset enable/disable’ is 1(reset enable). If user do not disable this bit, S3C2416 will be rebooted in about 5.63sec (In the case of PCLK is 12MHz). So at boot loader, this bit should be disabled before under control of Operating System, or Firmware.
Page 283: Watchdog Timer Data (Wtdat) Register
S3C2416X RISC MICROPROCESSOR WATCHDOG TIMER 3.2 WATCHDOG TIMER DATA (WTDAT) REGISTER The WTDAT register is used to specify the time-out duration. The content of WTDAT cannot be automatically loaded into the timer counter at initial watchdog timer operation. However, using 0x8000 (initial value) will drive the first time-out.
Page 284 WATCHDOG TIMER S3C2416X RISC MICROPROCESSOR NOTES 11-6...
Page 285: Chapter 12 Pwm Timer
1 OVERVIEW The S3C2416 has five 16-bit timers. Timer 0, 1, 2, and 3 have Pulse Width Modulation (PWM) function. Timer 4 has an internal timer only with no output pins. The timer 0 has a dead-zone generator, which is used with a large current device.
Page 286: Bit Pwm Timer Block Diagram
PWM TIMER S3C2416X RISC MICROPROCESSOR TOUT0 TCMPB0 TCNTB0 Dead Zone Generator Dead Zone Control Logic0 PCLK 8-Bit TCMPB1 TCNTB1 Prescaler 1/16 TOUT1 TCLK Control Clock Logic1 Divider Dead Zone TCMPB2 TCNTB2 TOUT2 Control Logic2 8-Bit TCMPB3 TCNTB3 Prescaler 1/16 TCLK TOUT3 Control Clock...
Page 287: Pwm Timer Operation
S3C2416X RISC MICROPROCESSOR PWM TIMER 2 PWM TIMER OPERATION 2.1 PRESCALER & DIVIDER An 8-bit prescaler and a 4-bit divider make the following output frequencies: 4-bit Divider Minimum Resolution Maximum Resolution Min. Interval Max. Interval Settings (prescaler = 0) (prescaler = 255) (TCNTBn = 1) (TCNTBn = 65535) 0.0400 us (25.000 MHz) 10.2400 us (97.6562 kHz)
Page 288: Basic Timer Operation
PWM TIMER S3C2416X RISC MICROPROCESSOR 2.2 BASIC TIMER OPERATION Figure 12-2. Timer Operations A timer (except the timer ch-4) has TCNTBn, TCNTn, TCMPBn and TCMPn. The TCNTBn and the TCMPBn are loaded into the TCNTn and the TCMPn when the timer reaches 0. When the TCNTn reaches 0, an interrupt request will occur if the interrupt is enabled.
Page 289: Auto Reload & Double Buffering
2.3 AUTO RELOAD & DOUBLE BUFFERING S3C2416 PWM Timers have a double buffering function, enabling the reload value changed for the next timer operation without stopping the current timer operation. So, although the new timer value is set, a current timer operation is completed successfully.
Page 290: Timer Initialization Using Manual Update Bit And Inverter Bit
PWM TIMER S3C2416X RISC MICROPROCESSOR 2.4 TIMER INITIALIZATION USING MANUAL UPDATE BIT AND INVERTER BIT An auto reload operation of the timer occurs when the internal down-counter(TCNTn) reaches 0. So, a starting value of the TCNTn has to be defined by the user in advance. In this case, the starting value has to be loaded by the manual update bit.
Page 291: Timer Operation
S3C2416X RISC MICROPROCESSOR PWM TIMER 2.5 TIMER OPERATION TOUTn Figure 12-4. Example of a Timer Operation The above Figure 12-4 shows the result of the following procedure: 1. Enable the auto re-load function. Set the TCNTBn to 160 (50+110) and the TCMPBn to 110. Set the manual update bit and configure the inverter bit (on/off).
Page 292: Pulse Width Modulation (Pwm)
PWM TIMER S3C2416X RISC MICROPROCESSOR 2.6 PULSE WIDTH MODULATION (PWM) Write Write Write TCMPBn = 60 TCMPBn = 40 TCMPBn = 30 Write Write Write TCMPBn = 50 TCMPBn = 30 TCMPBn = Next PWM Value Figure 12-5. Example of PWM PWM function can be implemented by using the TCMPBn.
Page 293: Output Level Control
S3C2416X RISC MICROPROCESSOR PWM TIMER 2.7 OUTPUT LEVEL CONTROL Inverter off Inverter on Initial State Period 1 Period 2 Timer Stop Figure 12-6. Inverter On/Off The following procedure describes how to maintain TOUT as high or low (assume the inverter is off): 1.
Page 294: Dead Zone Generator
PWM TIMER S3C2416X RISC MICROPROCESSOR 2.8 DEAD ZONE GENERATOR The Dead Zone is for the PWM control in a power device. This function enables the insertion of the time gap between a turn-off of a switching device and a turn on of another switching device. This time gap prohibits the two switching devices from being turned on simultaneously, even for a very short time.
Page 295: Dma Request Mode
S3C2416X RISC MICROPROCESSOR PWM TIMER 2.9 DMA REQUEST MODE The PWM timer can generate a DMA request at every specific time. The timer keeps DMA request signals (nDMA_REQ) low until the timer receives an ACK signal. When the timer receives the ACK signal, it makes the request signal inactive.
Page 296: Pwm Timer Control Registers
PWM TIMER S3C2416X RISC MICROPROCESSOR 3 PWM TIMER CONTROL REGISTERS 3.1 TIMER CONFIGURATION REGISTER0 (TCFG0) Timer input clock Frequency = PCLK / {prescaler value+1} / {divider value} {prescaler value} = 0~255 {divider value} = 2, 4, 8, 16 Register Address Description Reset Value TCFG0...
Page 297: Timer Configuration Register1 (Tcfg1)
S3C2416X RISC MICROPROCESSOR PWM TIMER 3.2 TIMER CONFIGURATION REGISTER1 (TCFG1) Register Address Description Reset Value TCFG1 0x51000004 5-MUX & DMA mode selection register 0x00000000 TCFG1 Description Initial State Reserved [31:24] 00000000 DMA mode [23:20] Select DMA request channel 0000 0000 = No select (all interrupt) 0001 = Timer0 0010 = Timer1 0011 = Timer2 0100 = Timer3...
Page 298: Timer Control (Tcon) Register
PWM TIMER S3C2416X RISC MICROPROCESSOR 3.3 TIMER CONTROL (TCON) REGISTER Register Address Description Reset Value TCON 0x51000008 Timer control register 0x00000000 TCON Description Initial state Timer 4 auto reload [22] Determine auto reload on/off for Timer 4. on/off 0 = One-shot 1 = Interval mode (auto reload) Timer 4 manual [21]...
Page 299 S3C2416X RISC MICROPROCESSOR PWM TIMER TCON Description Initial state Reserved [7:5] Reserved Dead zone enable Determine the dead zone operation. 0 = Disable 1 = Enable Timer 0 auto reload Determine auto reload on/off for Timer 0. on/off 0 = One-shot 1 = Interval mode(auto reload) Timer 0 output Determine the output inverter on/off for Timer 0.
Page 300: Timer 0 Count Buffer Register & Compare Buffer Register (Tcntb0/Tcmpb0)
PWM TIMER S3C2416X RISC MICROPROCESSOR 3.4 TIMER 0 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB0/TCMPB0) Register Address Description Reset Value TCNTB0 0x5100000C Timer 0 count buffer register 0x00000000 TCMPB0 0x51000010 Timer 0 compare buffer register 0x00000000 TCMPB0 Description Initial State Timer 0 compare buffer register [15:0] Set compare buffer value for Timer 0...
Page 301: Timer 1 Count Buffer Register & Compare Buffer Register (Tcntb1/Tcmpb1)
S3C2416X RISC MICROPROCESSOR PWM TIMER 3.6 TIMER 1 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB1/TCMPB1) Register Address Description Reset Value TCNTB1 0x51000018 Timer 1 count buffer register 0x00000000 TCMPB1 0x5100001C Timer 1 compare buffer register 0x00000000 TCMPB1 Description Initial State Timer 1 compare buffer register [15:0] Set compare buffer value for Timer 1...
Page 302: Timer 2 Count Buffer Register & Compare Buffer Register (Tcntb2/Tcmpb2)
PWM TIMER S3C2416X RISC MICROPROCESSOR 3.8 TIMER 2 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB2/TCMPB2) Register Address Description Reset Value TCNTB2 0x51000024 Timer 2 count buffer register 0x00000000 TCMPB2 0x51000028 Timer 2 compare buffer register 0x00000000 TCMPB2 Description Initial State Timer 2 compare buffer register [15:0] Set compare buffer value for Timer 2...
Page 303: Timer 3 Count Buffer Register & Compare Buffer Register (Tcntb3/Tcmpb3)
S3C2416X RISC MICROPROCESSOR PWM TIMER 3.10 TIMER 3 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB3/TCMPB3) Register Address Description Reset Value TCNTB3 0x51000030 Timer 3 count buffer register 0x00000000 TCMPB3 0x51000034 Timer 3 compare buffer register 0x00000000 TCMPB3 Description Initial State Timer 3 compare buffer register [15:0] Set compare buffer value for Timer 3...
Page 304: Timer 4 Count Buffer Register (Tcntb4)
PWM TIMER S3C2416X RISC MICROPROCESSOR 3.12 TIMER 4 COUNT BUFFER REGISTER (TCNTB4) Register Address Description Reset Value TCNTB4 0x5100003C Timer 4 count buffer register 0x00000000 TCNTB4 Description Initial State Timer 4 count buffer register [15:0] Set count buffer value for Timer 4 0x00000000 3.13 TIMER 4 COUNT OBSERVATION REGISTER (TCNTO4) Register...
Page 305: Chapter 13 Real Time Clock (Rtc)
REAL TIME CLOCK REAL TIME CLOCK (RTC) This chapter describes the functions and usage of Real Time Clock (RTC) in S3C2416 RISC microprocessor. 1 OVERVIEW The Real Time Clock (RTC) unit can be operated by the backup battery when the system power is off. The data include the time by second, minute, hour, date, day, month, and year.
Page 306: Real Time Clock Operation Description
For example, it cannot discriminate between 1900 and 2000. To solve this problem, the RTC block in S3C2416 has hard-wired logic to support the leap year in 2000. Note 1900 is not leap year while 2000 is leap year in general Gregorian calendar.
Page 307 S3C2416X RISC MICROPROCESSOR REAL TIME CLOCK 1.2.2 Read/Write Register Bit 0 of the RTCCON register must be set high in order to write the BCD register in RTC block. To display the second, minute, hour, day, date, month, and year, the CPU must read the data in BCDSEC, BCDMIN, BCDHOUR, BCDDATE, BCDDAY, BCDMON, and BCDYEAR registers respectively in the RTC block.
Page 308 REAL TIME CLOCK S3C2416X RISC MICROPROCESSOR 1.2.5 Tick time interrupt The RTC tick time is used for interrupt request. The TICNT register has an interrupt enable bit and the count value for the interrupt. The count value reaches ‘0’ when the tick time interrupt occurs. Then the period of interrupt is as follows: •...
Page 309: Rtc Tick Interrupt Clock Scheme
S3C2416X RISC MICROPROCESSOR REAL TIME CLOCK Figure 13-2. RTC Tick Interrupt Clock Scheme Example) For 1 ms Tick interrupt generation. RTCCON[0]= 1’b1 ( RTC enable ) RTCCON[3]=1’b1 ( RTC clock counter reset). RTCCON[3] = 1’b0 ( RTC clock counter enable) RTCCON[8:5] = 4’b0011 ( RTC divide clock selection.) TICNT1[6:0] = 7’h1 (Tick counter value setting).
Page 310: External Interface
REAL TIME CLOCK S3C2416X RISC MICROPROCESSOR 1.2.6 32.768 kHz X-TAL Connection EXAMPLE The Figure 13-3 shows a circuit of the RTC unit oscillation at 32.768 kHz. VDD_RTC 15~22pF XTIRTC XTIRTC 32768Hz 5Mohm XTORTC XTORTC 15~22pF B) RTC Block is not used A) RTC Block is used Figure 13-3.
Page 311: Register Description
S3C2416X RISC MICROPROCESSOR REAL TIME CLOCK 1.4 REGISTER DESCRIPTION 1.4.1 Memory Map Table 13-1. RTC Register summary Register Address Description Reset Value RTCCON 0x57000040 RTC control Register 0x00 TICNT0 0x57000044 Tick time count Register0 TICNT1 0x5700004C Tick time count Register1 TICNT2 0x57000048 Tick time count Register2...
Page 312: Individual Register Descriptions
REAL TIME CLOCK S3C2416X RISC MICROPROCESSOR 1.5 INDIVIDUAL REGISTER DESCRIPTIONS 1.5.1 REAL TIME CLOCK CONTROL (RTCCON) REGISTER The RTCCON register consists of 9 bits. It controls the read/write enable of the CLKSEL, CNTSEL and CLKRST for testing. RTCEN bit can control all interfaces between the CPU and the RTC, Therefore it must be set to 1 in an RTC control routine to enable data read/write after a system reset.
Page 313 1.5.2 Tick Time Count Register 0 (TICNT0) The TICNT0 register determines tick interrupt enable and tick counter value S3C2416 supports 32bits tic time counter. So, from 14 to 8bits of 32bit tick time count value is selected at TICNT0 register (TICNT0[6:0]).
Page 314 REAL TIME CLOCK S3C2416X RISC MICROPROCESSOR 1.5.4 Tick Time Count Register 2 (TICNT2) Register Address Description Reset Value TICNT2 0x57000048 Tick time count register 2 0x00 TICNT2 Description Initial State TICK TIME COUNT 2 [16:0] High 17 bits of 32bit tick time count value b’000000 1.5.5 RTC ALARM Control (RTCALM) Register The RTCALM register determines the alarm enable and the alarm time.
Page 315 S3C2416X RISC MICROPROCESSOR REAL TIME CLOCK 1.5.6 ALARM Second Data (ALMSEC) Register Register Address Description Reset Value ALMSEC 0x57000054 Alarm second data Register ALMSEC Description Initial State Reserved SECDATA [6:4] BCD value for alarm second. 0 ~ 5 [3:0] 0 ~ 9 0000 1.5.7 ALARM MIN Data (ALMMIN) Register Register...
Page 316 REAL TIME CLOCK S3C2416X RISC MICROPROCESSOR 1.5.9 ALARM DATE Data (ALMDATE) Register Register Address Description Reset Value ALMDATE 0x57000060 Alarm day data Register 0x01 ALMDATE Description Initial State Reserved [7:6] DATEDATA [5:4] BCD value for alarm date, from 0 to 28, 29, 30, 31. 0 ~ 3 [3:0] 0 ~ 9...
Page 317 S3C2416X RISC MICROPROCESSOR REAL TIME CLOCK 1.5.12 BCD SECOND (BCDSEC) Register Register Address Description Reset Value BCDSEC 0x57000070 BCD second Register Undefined BCDSEC Description Initial State SECDATA [6:4] BCD value for second. − 0 ~ 5 [3:0] 0 ~ 9 −...
Page 318 REAL TIME CLOCK S3C2416X RISC MICROPROCESSOR 1.5.15 BCD DATE (BCDDATE) Register Register Address Description Reset Value BCDDATE 0x5700007C BCD DATE Register Undefined BCDDAY Description Initial State Reserved [7:6] − DATEDATA [5:4] BCD value for date. − 0 ~ 3 [3:0] 0 ~ 9 −...
Page 319 S3C2416X RISC MICROPROCESSOR REAL TIME CLOCK 1.5.18 BCD YEAR (BCDYEAR) Register Register Address Description Reset Value BCDYEAR 0x57000088 BCD year Register Undefined BCDYEAR Description Initial State YEARDATA [7:4] BCD value for year. [3:0] NOTE: For setting BCD registers, RTCEN(RTCCON[0] bit) must be ebable. But at no setting BCD registers, RTCEN must be disable for reducing power comsumption.
Page 320 REAL TIME CLOCK S3C2416X RISC MICROPROCESSOR NOTES 13-16...
Page 321: Chapter 14 Uart
3Mbps bps. Each UART channel contains two 64-byte FIFOs for receiver and transmitter. The S3C2416 UART includes programmable baud rates, infrared (IR) transmit/receive, one or two stop bit insertion, 5-bit, 6-bit, 7-bit or 8-bit data width and parity checking.
Page 322: Block Diagram
UART S3C2416X RISC MICROPROCESSOR 2 BLOCK DIAGRAM Peripheral BUS Transmitter Transmit FIFO Register (FIFO mode) Transmit Buffer Register(64 Byte) Transmit Holding Register (Non-FIFO mode) Transmit Shifter TXDn Control Buad-rate Clock Source Unit Generator (PCLK, EXTUARTCLK, EPLL clock/n) Receiver Receive Shifter RXDn Receive Holding Register (Non-FIFO mode only)
Page 323: Uart Operation
S3C2416X RISC MICROPROCESSOR UART 2.1 UART OPERATION The following sections describe the UART operations that include data transmission, data reception, auto flow control, interrupt generation, Loopback mode, Infrared mode, and baud-rate generation. 2.1.1 Data Transmission The data frame for transmission is programmable. It consists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 stop bits, which can be specified by the line control register (ULCONn).
Page 324: Uart Afc Interface
Figure 14-2. UART AFC Interface NOTE UART 3 does not support AFC function, because the S3C2416 has no nRTS 3 and nCTS 3. S3C2416’s AFC does not support the RS-232C interface. Table 14-1. Example of nRTS signal change by FIFO Spare size...
Page 325 S3C2416X RISC MICROPROCESSOR UART 2.1.4 Non Auto-Flow Control (Controlling nRTS and nCTS by Software) If users want to connect a UART to a Modem, disable auto flow control bit in UMCONn register and control the signal of nRTS by software. Example: Rx Operation with FIFO 1.
Page 326: Interrupts In Connection With Fifo
S3C2416X RISC MICROPROCESSOR 2.1.6 Interrupt/DMA Request Generation Each UART of the S3C2416 has seven status (Tx/Rx/Error) signals: Overrun error, Parity error, Frame error, Break, Receive buffer data ready, Transmit buffer empty, and Transmit shifter empty, all of which are indicated by the corresponding UART status register (UTRSTATn/UERSTATn).
Page 327: Example Showing Uart Receiving 5 Characters With 2 Errors
S3C2416X RISC MICROPROCESSOR UART 2.1.7 UART Error Status FIFO UART has the error status FIFO besides the Rx FIFO register. The error status FIFO indicates which data, among FIFO registers, is received with an error. The error interrupt will be issued only when the data, which has an error, is ready to read out.
Page 328: Irda Function Block Diagram
2.1.8 Loopback Mode The S3C2416 UART provides a test mode referred to as the Loopback mode, to aid in isolating faults in the communication link. This mode structurally enables the connection of RXD and TXD in the UART. In this mode, therefore, transmitted data is received to the receiver, via RXD.
Page 329: Serial I/O Frame Timing Diagram (Normal Uart)
S3C2416X RISC MICROPROCESSOR UART Figure 14-5. Serial I/O Frame Timing Diagram (Normal UART) Figure 14-6. Infrared Transmit Mode Frame Timing Diagram Figure 14-7. Infrared Receive Mode Frame Timing Diagram 14-9...
Page 330 Each UART's baud-rate generator provides the serial clock for the transmitter and the receiver. The source clock for the baud-rate generator can be selected with the S3C2416's internal system clock(PCLK or divided EPLL clock) or EXTUARTCLK. UARTCLK (Clock frequencies of 16 times the baud rate) are used for sampling serial data to minimize error.
Page 331: Clock, Epll Speed Guide
S3C2416X RISC MICROPROCESSOR UART 2.1.11 Baud-Rate Error Tolerance UART Frame error should be less than 1.87%(3/160). UART Frame error = { |Real Frame Length − Ideal Frame Length| / Ideal Frame Length } x 100% = { |Ideal baudrate − Real baudrate| / Real baudrate } x 100% Real Frame Length = 1 Frame / Real UART baudrate = 1 Frame x (DIV_VAL+1) x 16 / SRCCLK Where Real UART baudrate = { SRCCLK / (DIV_VAL+1) } / 16 Ideal Frame Length = 1 Frame / Ideal UART baudrate...
Page 332: Uart Special Registers
UART S3C2416X RISC MICROPROCESSOR 3 UART SPECIAL REGISTERS 3.1 UART LINE CONTROL REGISTER There are four UART line control registers including ULCON0, ULCON1, ULCON2 and ULCON3 in the UART block. Register Address Description Reset Value ULCON0 0x50000000 UART channel 0 line control register 0x00 ULCON1 0x50004000...
Page 333: Uart Control Register
S3C2416X RISC MICROPROCESSOR UART 3.2 UART CONTROL REGISTER There are four UART control registers including UCON0, UCON1, UCON2 and UCON3 in the UART block. Register Address Description Reset Value UCON0 0x50000004 UART channel 0 control register 0x00 UCON1 0x50004004 UART channel 1 control register 0x00 UCON2 0x50008004...
Page 334 UART S3C2416X RISC MICROPROCESSOR UCONn Description Initial State Transmit Mode [3:2] Determine which function is currently able to write Tx data to the UART transmit buffer register. (note 3) 00 = Disable 01 = Interrupt request or polling mode (note 6) 10 = DMA request( request signal 0) 11 = DMA request( request signal 1) Receive Mode...
Page 335: Uart Fifo Control Register
S3C2416X RISC MICROPROCESSOR UART 3.3 UART FIFO CONTROL REGISTER There are four UART FIFO control registers including UFCON0, UFCON1, UFCON2 and UFCON3 in the UART block. Register Address Description Reset Value UFCON0 0x50000008 UART channel 0 FIFO control register UFCON1 0x50004008 UART channel 1 FIFO control register UFCON2...
Page 336: Uart Modem Control Register
1 = 'L' level (Activate nRTS) NOTES: UART 3 does not support AFC function, because the S3C2416 has no nRTS3 and nCTS3. If AFC bit is enabled and Time-out bit is disabled, RTS trigger level must be lager than Rx FIFO trigger level.
Page 337: Uart Tx/Rx Status Register
S3C2416X RISC MICROPROCESSOR UART 3.5 UART TX/RX STATUS REGISTER There are four UART Tx/Rx status registers including UTRSTAT0, UTRSTAT1, UTRSTAT2 and UTRSTAT3 in the UART block. Register Address Description Reset Value UTRSTAT0 0x50000010 UART channel 0 Tx/Rx status register UTRSTAT1 0x50004010 UART channel 1 Tx/Rx status register UTRSTAT2...
Page 338: Uart Error Status Register
UART S3C2416X RISC MICROPROCESSOR 3.6 UART ERROR STATUS REGISTER There are four UART Rx error status registers including UERSTAT0, UERSTAT1, UERSTAT2 and UERSTAT3 in the UART block. Register Address Description Reset Value UERSTAT0 0x50000014 UART channel 0 Rx error status register UERSTAT1 0x50004014 UART channel 1 Rx error status register...
Page 339: Uart Fifo Status Register
S3C2416X RISC MICROPROCESSOR UART 3.7 UART FIFO STATUS REGISTER There are four UART FIFO status registers including UFSTAT0, UFSTAT1 UFSTAT2 and UFSTAT3 in the UART block. Register Address Description Reset Value UFSTAT0 0x50000018 UART channel 0 FIFO status register 0x00 UFSTAT1 0x50004018 UART channel 1 FIFO status register...
Page 340: Uart Modem Status Register
UART channel 2 modem status register UMSTAT0 Description Initial State Delta CTS Indicate that the nCTS input to the S3C2416 has changed state since the last time it was read by CPU. (Refer to Figure 14-8.) 0 = Has not changed 1 = Has changed...
Page 341: Uart Transmit Buffer Register (Holding Register & Fifo Register)
S3C2416X RISC MICROPROCESSOR UART 3.9 UART TRANSMIT BUFFER REGISTER (HOLDING REGISTER & FIFO REGISTER) There are four UART transmit buffer registers including UTXH0, UTXH1, UTXH2 and UTXH3 in the UART block. UTXHn has an 8-bit data for transmission data. Register Address Description Reset Value...
Page 342: Uart Baud Rate Divisor Register
UART S3C2416X RISC MICROPROCESSOR 3.11 UART BAUD RATE DIVISOR REGISTER There are four UART baud rate divisor registers including UBRDIV0, UBRDIV1, UBRDIV2 and UBRDIV3 in the UART block. Register Address Description Reset Value UBRDIV0 0x50000028 Baud rate divisior(integer place) register 0 −...
Page 343: Uart Dividing Slot Register
S3C2416X RISC MICROPROCESSOR UART 3.12 UART DIVIDING SLOT REGISTER There are four UART dividing slot registers including UDIVSLOT0, UDIVSLOT 1, UDIVSLOT 2 and UDIVSLOT in the UART block. Register Address Description Reset Value UDIVSLOT0 0x5000002C Baud rate divisior(decimal place) register 0 0x0000 UDIVSLOT1 0x5000402C...
Page 344 UART S3C2416X RISC MICROPROCESSOR NOTES 14-24...
Page 345: Chapter 15 Usb Host Controller
S3C2416X RISC MICROPROCESSOR USB HOST CONTROLLER USB HOST CONTROLLER 1 OVERVIEW S3C2416 supports 2-port USB host interface as follows: • OHCI Rev 1.0 compatible • USB Rev1.1 compatible Two down stream ports • • Support for both LowSpeed and FullSpeed USB devices...
Page 346: Usb Host Controller Special Registers
USB HOST CONTROLLER S3C2416X RISC MICROPROCESSOR 1.1 USB HOST CONTROLLER SPECIAL REGISTERS The S3C2416 USB host controller complies with OHCI Rev 1.0. Refer to Open Host Controller Interface Rev 1.0 specification for detail information. Table 15-1. OHCI Registers for USB Host Controller...
Page 347: Chapter 16 Usb 2.0 Function
USB 2.0 FUNCTION 1 OVERVIEW The Samsung USB 2.0 Controller is designed to aid the rapid implementation of the USB 2.0 peripheral device. The controller supports both High and Full speed mode. Using the standard UTMI interface and AHB interface the USB 2.0 Controller can support up to 9 Endpoints (including Endpoint0) with programmable Interrupt, Bulk mode.
Page 348: Block Diagram
Status Registers. And also Function has an AHB Master to enable the link to transfer data on the AHB. The S3C2416 USB system shown as Figure 16-1, can be configured as following : 1. USB 1.1 Host 1 Port & USB 2.0 Device 1 Port 2.
Page 349: To Activate Usb Port1 For Usb 2.0 Function
USB2.0 DEVICE 3 TO ACTIVATE USB PORT1 FOR USB 2.0 FUNCTION USB Function block of S3C2416 shares USB PORT1 with USB Host block. To activate USB PORT1 for USB Function, see USB control registers in System Controller Guide AHB Slave Interface...
Page 350: Sie (Serial Interface Engine)
USB2.0 DEVICE S3C2416X RISC MICROPROCESSOR 4 SIE (SERIAL INTERFACE ENGINE) This block handles NRZI decoding/encoding, CRC generation and checking, and bit-stuffing. It also provides the interface signals for USB Transceiver. 5 UPH (UNIVERSAL PROTOCOL HANDLER) This block includes state machines and FIFO control, control/status register and DMA control block of each direction endpoint.
Page 351: Usb 2.0 Function Controller Special Registers
S3C2416X RISC MICROPROCESSOR USB2.0 DEVICE 7 USB 2.0 FUNCTION CONTROLLER SPECIAL REGISTERS The USB 2.0 controller includes several 16-bit registers for the endpoint programming and debugging. The registers can be grouped into two categories. Few of the indexed registers are related to endpoint 0, but most of them are utilized for the control and status monitoring of each data endpoint, including FIFO control and packet size configuration.
Page 352: Indexed Registers
USB2.0 DEVICE S3C2416X RISC MICROPROCESSOR Table 16-2. Indexed Registers Register Address Description 0x4980_002C Endpoints Status Register 0x4980_0030 Endpoints Control Register BRCR 0x4980_0034 Byte Read Count Register BWCR 0x4980_0038 Byte Write Count Register 0x4980_003C Max Packet Register 0x4980_0040 DMA Control Register DTCR 0x4980_0044 DMA Transfer Counter Register...
Page 353: Registers
S3C2416X RISC MICROPROCESSOR USB2.0 DEVICE 8 REGISTERS 8.1 INDEX REGISTER (IR) The index register is used for indexing a specific endpoint. In most cases, setting the index register value should precede any other operation. Register Address Description Reset Value 0x4980_0000 Index Register 0x00 Description...
Page 354: Endpoint Interrupt Register (Eir)
USB2.0 DEVICE S3C2416X RISC MICROPROCESSOR 8.2 ENDPOINT INTERRUPT REGISTER (EIR) The endpoint interrupt register lets the MCU knows what endpoint generates the interrupt. The source of an interrupt could be various, but, when an interrupt is detected, the endpoint status register should be checked to identify if it’s related to specific endpoint.
Page 355: Endpoint Interrupt Enable Register (Eier)
S3C2416X RISC MICROPROCESSOR USB2.0 DEVICE 8.3 ENDPOINT INTERRUPT ENABLE REGISTER (EIER) Pairing with interrupt register, this register enables interrupt for each endpoints. Register Address Description Reset Value EIER 0x4980_0008 Endpoint interrupt enable register 0x00 EIER Description Initial State [31:9] Reserved −...
Page 356: Function Address Register (Far)
USB2.0 DEVICE S3C2416X RISC MICROPROCESSOR 8.4 FUNCTION ADDRESS REGISTER (FAR) This register holds the address of USB device. Register Address Description Reset Value 0x4980_000C Function address register Description Initial State [31:7] Reserved − [6:0] MCU can read a unique USB function address from this 7’h0 register.
Page 357: Endpoint Direction Register (Edr)
S3C2416X RISC MICROPROCESSOR USB2.0 DEVICE 8.5 ENDPOINT DIRECTION REGISTER (EDR) USB 2.0 Core supports IN/OUT direction control for each endpoint. This direction can’t be changed dynamically. Only by new enumeration, the direction can be altered. Since the endpoint 0 is bi-directional, there is no direction bit assigned to it.
Page 358: Test Register (Tr)
USB2.0 DEVICE S3C2416X RISC MICROPROCESSOR 8.6 TEST REGISTER (TR) The test register is used for the diagnostics. All bit are activated when 1 is written to and is cleared by 0 on them. Bit[3:0] are for the high speed device only. Register Address Description...
Page 359: System Status Register (Ssr)
S3C2416X RISC MICROPROCESSOR USB2.0 DEVICE 8.7 SYSTEM STATUS REGISTER (SSR) This register reports operational status of the USB 2.0 Function Core, especially about error status and power saving mode status. Except the line status, every status bits in the System Status Register could be an interrupt sources.
Page 360 USB2.0 DEVICE S3C2416X RISC MICROPROCESSOR Description Initial State Speed Detection End. SDE is set by the core when the HS Detect Handshake process is ended. HFRM Host Forced Resume. HFRM is set by the core in suspend state when host sends resume signaling.
Page 361: System Control Register (Scr)
S3C2416X RISC MICROPROCESSOR USB2.0 DEVICE 8.8 SYSTEM CONTROL REGISTER (SCR) This register enables top-level control of the core. MCU should access this register for controls such as Power saving mode enable/disable. Register Address Description Reset Value 0x4980_0020 System control register Description Initial State [31:15]...
Page 362: Ep0 Status Register (Ep0Sr)
USB2.0 DEVICE S3C2416X RISC MICROPROCESSOR 8.9 EP0 STATUS REGISTER (EP0SR) This register stores status information of the Endpoint 0. These status information are set automatically by the core when corresponding conditions are met. After reading the bits, MCU should write 1 to clear them. Register Address Description...
Page 363: Ep0 Control Register (Ep0Cr)
S3C2416X RISC MICROPROCESSOR USB2.0 DEVICE 8.10 EP0 CONTROL REGISTER (EP0CR) EP0 control register is used for the control of endpoint 0. Controls such as enabling ep0 related interrupts and toggle controls can be handled by EP0 control register. Register Address Description Reset Value EP0CR...
Page 364: Endpoint# Buffer Register (Ep#Br)
USB2.0 DEVICE S3C2416X RISC MICROPROCESSOR 8.11 ENDPOINT# BUFFER REGISTER (EP#BR) The buffer register is used to hold data for TX/RX transfer. Register Address Description Reset Value EP0BR 0x4980_0060 EP0 Buffer Register EP1BR 0x4980_0064 EP1 Buffer Register EP2BR 0x4980_0068 EP2 Buffer Register EP3BR 0x4980_006C EP3 Buffer Register...
Page 365: Endpoint Status Register (Esr)
S3C2416X RISC MICROPROCESSOR USB2.0 DEVICE 8.12 ENDPOINT STATUS REGISTER (ESR) The endpoint status register reports current status of an endpoint (except EP0) to the MCU Register Address Description Reset Value 0x4980_002C Endpoint status register Description Initial State [31:12] Reserved FPID [11] First OUT Packet interrupt Disable in OUT DMA operation.
Page 366 USB2.0 DEVICE S3C2416X RISC MICROPROCESSOR Description Initial State PSIF [3:2] Packet Status In FIFO. 00 = No packet in FIFO 01 = One packet in FIFO 10 = Two packet in FIFO 11 = Invalid value Tx Packet Success TPS is used for Single or Dual transfer mode. TPS is activated when one packet data in FIFO was successfully transferred to Host and received ACK from Host.
Page 367: Endpoint Control Register (Ecr)
S3C2416X RISC MICROPROCESSOR USB2.0 DEVICE 8.13 ENDPOINT CONTROL REGISTER (ECR) The endpoint control register is useful for controlling an endpoint both in normal operation and test case. Putting an endpoint in specific operation mode can be accomplished through the endpoint control register. Register Address Description...
Page 368: Byte Read Count Register (Brcr)
USB2.0 DEVICE S3C2416X RISC MICROPROCESSOR 8.14 BYTE READ COUNT REGISTER (BRCR) The byte read count register keeps byte (half word) counts of a RX packet from USB host. Register Address Description Reset Value BRCR 0x4980_0034 Byte Read Count Register BRCR Description Initial State [31:10]...
Page 369: Byte Write Count Register (Bwcr)
S3C2416X RISC MICROPROCESSOR USB2.0 DEVICE 8.15 BYTE WRITE COUNT REGISTER (BWCR) The byte write count register keeps the byte (half word) count value of a TX packet from MCU. The counter value will be used to determine the end of TX packet. Register Address Description...
Page 370: Max Packet Register (Mpr)
USB2.0 DEVICE S3C2416X RISC MICROPROCESSOR 8.16 MAX PACKET REGISTER (MPR) The byte write count register keeps the byte (half word) count value of a TX packet from MCU. The counter value will be used to determine the end of TX packet. Register Address Description...
Page 371: Dma Control Register (Dcr)
S3C2416X RISC MICROPROCESSOR USB2.0 DEVICE 8.17 DMA CONTROL REGISTER (DCR) The AHB Master Operation is controlled by the programming DMA Control Register and DMA IF Control Register. Register Address Description Reset Value 0x4980_0040 DMA Control Register Description Initial State [31:6] Reserved −...
Page 372: Dma Transfer Counter Register (Dtcr)
USB2.0 DEVICE S3C2416X RISC MICROPROCESSOR 8.18 DMA TRANSFER COUNTER REGISTER (DTCR) The byte write count register keeps the byte (half word) count value of a TX packet from MCU. The counter value will be used to determine the end of TX packet. Register Address Description...
Page 373: Dma Fifo Counter Register (Dfcr)
S3C2416X RISC MICROPROCESSOR USB2.0 DEVICE 8.19 DMA FIFO COUNTER REGISTER (DFCR) This register has the byte number of data per DMA operation. The max packet size is loaded in this register. Register Address Description Reset Value DFCR 0x4980_0048 DMA FIFO Counter Register MFCR Description Initial State...
Page 374: Dma Total Transfer Counter Register 1/2 (Dttcr 1/2)
USB2.0 DEVICE S3C2416X RISC MICROPROCESSOR 8.20 DMA TOTAL TRANSFER COUNTER REGISTER 1/2 (DTTCR 1/2) This register has the total byte number of data to transfer using DMA Interface. When this counter register value is zero, DMA operation is ended. Register Address Description Reset Value...
Page 375: Dma Interface Control Register (Dicr)
S3C2416X RISC MICROPROCESSOR USB2.0 DEVICE 8.21 DMA INTERFACE CONTROL REGISTER (DICR) The AHB Master Operation is controlled by the programming DMA Control Register and DMA IF Control Register. Register Address Description Reset Value DICR 0x4980_0084 DMA Interface Counter Register DICR Description Initial State Reserved...
Page 376: Memory Base Address Register (Mbar)
USB2.0 DEVICE S3C2416X RISC MICROPROCESSOR 8.22 MEMORY BASE ADDRESS REGISTER (MBAR) Register Address Description Reset Value MBAR 0x4980_0088 Memory Base Address Register MBAR# Description Initial State MBAR [31:0] This register should have memory base address to be 32’h0 transferred using DMA Interface. 16-30...
Page 377: Memory Current Address Register (Mcar)
S3C2416X RISC MICROPROCESSOR USB2.0 DEVICE 8.23 MEMORY CURRENT ADDRESS REGISTER (MCAR) Register Address Description Reset Value MCAR 0x4980_008C Memory Current Address Register MCAR# Description Initial State MCAR [31:0] This register should have memory current address to be transferred using DMA Interface. 8.24 BURST FIFO CONTROL REGISTER(FCON) Register Address...
Page 378: Ahb Master(Dma) Operation Flow Chart
USB2.0 DEVICE S3C2416X RISC MICROPROCESSOR 8.26 AHB MASTER(DMA) OPERATION FLOW CHART 8.26.1 A. OUT Transfer Operation Flow AHB Master IF Registers (Unit Counter, Total Transfer Counter, Control) are set in initial state or Interrupt service routine. AHB Master IF Registers are to be set after MCU reads all data packets from USB OUT FIFO to operate a AHB Master operation after interrupt service mode.
Page 379: In Transfer Operation Flow
S3C2416X RISC MICROPROCESSOR USB2.0 DEVICE 8.26.2 B. IN Transfer Operation Flow AHB Master Registers( Unit Counter, Total Transfer Counter, Control) are set in intial state or Interrupt service routine. AHB Master Registers are to be set after MCU writes one packet data to USB IN FIFO to operate a AHB Master operation after interrupt service mode USB Core receives IN TOKEN from Host PC and sends IN data to...
Page 380 USB2.0 DEVICE S3C2416X RISC MICROPROCESSOR NOTES 16-34...
Page 381: Overview
In multi-master IIC-bus mode, multiple S3C2416 RISC microprocessors can receive or transmit serial data to or from slave devices. The master S3C2416 can initiate and terminate a data transfer over the IIC-bus. The IIC-bus in the S3C2416 uses Standard bus arbitration procedure.
Page 382: Iic-Bus Block Diagram
IIC-BUS INTERFACE S3C2416X RISC MICROPROCESSOR Address Register Comparator IIC-Bus Control Logic IICCON IICSTAT PCLK 4-bit Prescaler Shift Register Shift Register (IICDS) Data Bus Figure 17-1. IIC-Bus Block Diagram 17-2...
Page 383: Start And Stop Conditions
S3C2416X RISC MICROPROCESSOR IIC-BUS INTERFACE 1.1 IIC-BUS INTERFACE The S3C2416 IIC-bus interface has four operation modes: • Master transmitter mode • Master receive mode • Slave transmitter mode • Slave receive mode Functional relationships among these operating modes are described below.
Page 384: Data Transfer Format
IIC-BUS INTERFACE S3C2416X RISC MICROPROCESSOR 1.3 DATA TRANSFER FORMAT Every byte placed on the SDA line should be eight bits in length. The bytes can be unlimitedly transmitted per transfer. The first byte following a Start condition should have the address field. The address field can be transmitted by the master when the IIC-bus is operating in Master mode.
Page 385: Ack Signal Transmission
S3C2416X RISC MICROPROCESSOR IIC-BUS INTERFACE Acknowledgement Acknowledgement Signal from Receiver Signal from Receiver Byte Complete, Interrupt Clock Line Held Low by within Receiver receiver and/or transmitter Figure 17-4. Data Transfer on the IIC-Bus 1.4 ACK SIGNAL TRANSMISSION To complete a one-byte transfer operation, the receiver should send an ACK bit to the transmitter. The ACK pulse should occur at the ninth clock of the SCL line.
Page 386: Read-Write Operation
In Receive mode, when data is received, the IIC-bus interface will wait until IICDS register is read. Before the new data is read out, the SCL line will be held low and then released after it is read. The S3C2416 should hold the interrupt to identify the completion of the new data reception.
Page 387: Flowcharts Of Operations In Each Mode
S3C2416X RISC MICROPROCESSOR IIC-BUS INTERFACE 1.9 FLOWCHARTS OF OPERATIONS IN EACH MODE The following steps must be executed before any IIC Tx/Rx operations. 1. Write own slave address on IICADD register, if needed. 2. Set IICCON register. a) Enable interrupt b) Define SCL period 3.
Page 388: Operations For Master/Receiver Mode
IIC-BUS INTERFACE S3C2416X RISC MICROPROCESSOR START Master Rx mode has been configured. Write slave address to IICDS. Write 0xB0 (M/R Start) to IICSTAT. The data of the IICDS (slave address) is transmitted. ACK period and then interrupt is pending. Stop? Read a new data from Write 0x90 (M/R Stop) to IICDS.
Page 389: Operations For Slave/Transmitter Mode
S3C2416X RISC MICROPROCESSOR IIC-BUS INTERFACE START Slave Tx mode has been configured. IIC detects start signal. and, IICDS receives data. IIC compares IICADD and IICDS (the received slave address). Matched? The IIC address match interrupt is generated. Write data to IICDS. Clear pending bit to resume.
Page 390: Operations For Slave/Receiver Mode
IIC-BUS INTERFACE S3C2416X RISC MICROPROCESSOR START Slave Rx mode has been configured. IIC detects start signal. and, IICDS receives data. IIC compares IICADD and IICDS (the received slave address). Matched? The IIC address match interrupt is generated. Read data from IICDS. Clear pending bit to resume.
Page 391: Iic-Bus Interface Special Registers
S3C2416X RISC MICROPROCESSOR IIC-BUS INTERFACE 2 IIC-BUS INTERFACE SPECIAL REGISTERS 2.1 MULTI-MASTER IIC-BUS CONTROL (IICCON) REGISTER Register Address Description Reset Value IICCON0 0x54000000 IIC0-Bus control register 0x0X IICCON0 Description Initial State IICCON1 Acknowledge IIC-bus acknowledge enable bit. generation 0 = Disable 1 = Enable (note 1) In Tx mode, the IICSDA is free in the ack time.
Page 392: Multi-Master Iic-Bus Control/Status (Iicstat) Register
IIC-BUS INTERFACE S3C2416X RISC MICROPROCESSOR 2.2 MULTI-MASTER IIC-BUS CONTROL/STATUS (IICSTAT) REGISTER Register Address Description Reset Value IICSTAT0 0x54000004 IIC0-Bus control/status register IICSTAT0 Description Initial State IICSTAT1 Mode selection [7:6] IIC-bus master/slave Tx/Rx mode select bits. 00 = Slave receive mode 01 = Slave transmit mode 10 = Master receive mode 11 = Master transmit mode...
Page 393: Multi-Master Iic-Bus Address (Iicadd) Register
S3C2416X RISC MICROPROCESSOR IIC-BUS INTERFACE 2.3 MULTI-MASTER IIC-BUS ADDRESS (IICADD) REGISTER Register Address Description Reset Value IICADD0 0x54000008 IIC0-Bus address register 0xXX IICADD0 Description Initial State IICADD1 Slave address [7:0] 7-bit slave address, latched from the IIC-bus. XXXXXXXX When serial output enable = 0 in the IICSTAT, IICADD is write- enabled.
Page 394: Multi-Master Iic-Bus Line Control(Iiclc) Register
IIC-BUS INTERFACE S3C2416X RISC MICROPROCESSOR 2.5 MULTI-MASTER IIC-BUS LINE CONTROL(IICLC) REGISTER Register Address Description Reset Value IICLC0 0x54000010 IIC0-Bus multi-master line control register 0x00 IICLC0 Description Initial State IICLC1 Filter enable IIC-bus filter enable bit. When SDA port is operating as input, this bit should be High. This filter can prevent from occurred error by a glitch during double of PCLK time.
Page 395: Chapter 18 1 Introduction
S3C2416X RISC MICROPROCESSOR 1 INTRODUCTION 2D graphics accelerator supports three types of primitive drawings: Line/Point Drawing, Bit Block Transfer (BitBLT) and Color Expansion (Text Drawing). Rendering a primitive takes two steps: 1) configure the rendering parameters, such as foreground color and the coordinate data, by setting the drawing-context registers;...
Page 396: Color Format Conversion
S3C2416X RISC MICROPROCESSOR 2 COLOR FORMAT CONVERSION 2D supports seven color formats: RGB_565, RGBA_5551, ARGB_1555, RGBA_8888, ARGB_8888, XRGB_8888, and RGBX_8888. The structure of each color format is illustrated in Figure 18-1. RGB_565 RGBA_5551 15 14 ARGB_1555 RGBA_8888 ARGB_8888 XRGB_8888 0xFF RGBX_8888 0xFF Figure 18-1.
Page 397: Command Fifo
S3C2416X RISC MICROPROCESSOR YUV422 2-Planar Figure 18-2. YUV 2-Planar Format 3 COMMAND FIFO 2D has a 32-word command FIFO. Every data written to command registers and parameter setting registers will be written to the FIFO first. If the graphics engine is idle (no command is being executed), the data will be written to the designated register in one cycle;...
Page 398: Rendering Pipeline
S3C2416X RISC MICROPROCESSOR 4 RENDERING PIPELINE The rendering pipeline of 2D is illustrated in Figure 18-3. The functionality and related registers of each stage are introduced in detail in the rest of this chapter. Figure 18-3. 2D Rendering Pipeline 4.1 PRIMITIVE DRAWING Primitive Drawing determines the pixels to fill, and pass their coordinates to the next stage for further operations.
Page 399 S3C2416X RISC MICROPROCESSOR 4.1.2 Related Registers COORD_0 Coordinate of the starting point COORD_2 Coordinate of the ending point (ignored if a point is rendered). X increment value ( ignored if x-axis is the Major Axis or a point is rendered). X-INCR X-INCR = (ex-sx)/ |ey - sy| Y increment value (ignored if y-axis is the Major Axis or a point is rendered).
Page 400: Transparent Mode
S3C2416X RISC MICROPROCESSOR 4.1.6 Transparent Mode 2D can render image in Transparent Mode. In this mode, the pixels having the same color with background color (BG_COLOR) are discarded, resulting in a transparent effect. The function of Transparent Mode is illustrated in the images below, in which the BG_COLOR is set to white.
Page 401 S3C2416X RISC MICROPROCESSOR 4.1.8 Related Registers COORD_0 Coordinate of the leftmost topmost coordinate of the source image COORD_1 Coordinate of the rightmost bottommost coordinate of the source image COORD_2 Coordinate of the leftmost topmost coordinate of the destination image COORD_3 Coordinate of the rightmost bottommost coordinate of the destination image X increment value of the source image coordinates.
Page 402: Color Expansion
S3C2416X RISC MICROPROCESSOR 4.1.9 Color Expansion (Font Drawing) Color Expansion expands the monochrome color to either background (BG_COLOR) or foreground (FG_COLOR) color. Each bit of the source data presents a pixel, with ‘1’ indicating the foreground color and ‘0’ the background color.
Page 403: Rotation
S3C2416X RISC MICROPROCESSOR 4.1.10 Related Registers COORD_0 Coordinate of the leftmost topmost coordinate of the destination window COORD_1 Coordinate of the rightmost bottommost coordinate of the destination window FG_COLOR Foreground Color BG_COLOR Background Color ROP_REG Enable/disable Transparent Mode The base address of the font data. Note that writing to this register starts the CMD7_REG rendering process in the memory-to-screen mode.
Page 404: Rotation Example
S3C2416X RISC MICROPROCESSOR 4.2.2 Rotation Effect 0° 90° 180° 270° X-flip Y-flip -dcy + (ox+oy) -dcx + 2ox dcy + (ox-oy) -dcx + 2ox dcx - (ox-oy) -dcy + 2oy -dcx + (ox+oy) -dcy + 2oy 90 ° 180 ° Original image FIMG - 2D 270 °...
Page 405: Clipping
S3C2416X RISC MICROPROCESSOR 4.3 CLIPPING Clipping discards the pixels (after rotation) outside the clipping window. The discarded pixels will not go through the rest of rendering pipelines. Note that the clipping windows must reside totally inside the screen. Setting the clipping window the same size with the screen will disable the clipping effect, and a clipping window bigger than the screen size is not allowed.
Page 406 S3C2416X RISC MICROPROCESSOR The third operand can be pattern or foreground color, configurable by the OS bit in the ROP_REG. Pattern is a user-specified 8x8x16-bpp image; the pattern data should be given in RGB565 format. The following equation is used to calculate the pattern index of pixel (x, y): index = ( ((patternOffsetY + y) &...
Page 407: Alpha Blending
S3C2416X RISC MICROPROCESSOR 4.6 ALPHA BLENDING Alpha Blending combines the source color and the destination color in the frame buffer to get the new destination color. The conventional alpha blending equation is: final data = src * alpha + dest * (1.0 − alpha). 2D uses 8-bit integer to represent the alpha value, with 0 indicating 1/256 and 255 indicating 1.0.
Page 408: Register Descriptions
S3C2416X RISC MICROPROCESSOR 5 REGISTER DESCRIPTIONS Register Offset Description Reset Value General Registers CONTROL_REG 0x0000 Control register. 0x0000_0000 INTEN_REG 0x0004 Interrupt Enable register. 0x0000_0000 FIFO_INTC_REG 0x0008 Interrupt Control register. 0x0000_0018 INTC_PEND_REG 0x000C Interrupt Control Pending register. 0x0000_0000 FIFO_STAT_REG 0x0010 Command FIFO Status register. 0x0000_0600 Command Registers CMD0_REG...
Page 409 S3C2416X RISC MICROPROCESSOR Register Offset Description Reset Value COORD1_Y_REG 0x0318 Y coordinate of Coordinates 1. 0x0000_0000 COORD2_REG 0x0320 Coordinates 2 register. 0x0000_0000 COORD2_X_REG 0x0324 X coordinate of Coordinates 2. 0x0000_0000 COORD2_Y_REG 0x0328 Y coordinate of Coordinates 2. 0x0000_0000 COORD3_REG 0x0330 Coordinates 3 register.
Page 410: General Registers
S3C2416X RISC MICROPROCESSOR 5.1 GENERAL REGISTERS 5.1.1 Control Register (CONTROL_REG) Register Address Description Reset Value CONTROL_REG 0x4D408000 Control register Field Description Initial State Reserved [31:1] − Software Reset Write to this bit results in a one-cycle reset signal to FIMG2D graphics engine.
Page 411 S3C2416X RISC MICROPROCESSOR 5.1.3 FIFO Interrupt Control Register (FIFO_INTC_REG) Register Address Description Reset Value FIFO_INTC_REG 0x4D408008 FIFO Interrupt Control 0x18 Field Description Initial State Reserved [31:6] − FIFO_INT_LEVEL [5:0] If FIFO_INT_E (in INTEN_REG) is set, when FIFO_USED (in 0x18 FIFO_STAT_REG) is greater or equal to FIFO_INT_LEVEL, an interrupt occurs.
Page 412 S3C2416X RISC MICROPROCESSOR 5.1.5 FIFO Statue Register (FIFO_STAT_REG) Register Address Description Reset Value FIFO_STAT_REG 0x4D408010 FIFO Status Register 0x600 Field Description Initial State Reserved [31:11] − − CMD_FIN [10] 1 = The graphics engine finishes the execution of current command. 0 = In the middle of rendering process.
Page 413: Command Registers
S3C2416X RISC MICROPROCESSOR 5.2 COMMAND REGISTERS 5.2.1 LINE Drawing Register (CMD0_REG) Register Address Description Reset Value CMD0_REG 0x4D408100 Line Drawing Register Field Description Initial State Reserved [31:10] − − 0 = Draw Last Point − 1 = Do-not-Draw Last Point. 0 = Major axis is Y.
Page 414 S3C2416X RISC MICROPROCESSOR 5.2.4 Host to Screen Continue BitBLT Register (CMD3_REG) Register Address Description Reset Value CMD3_REG 0x4D40810C Host to Screen Continue BitBLT Register Field Description Initial State Data [31:0] BitBLT data (Continue) − Note that the data written to this register represents only one pixel, regardless of the source color mode.
Page 415: Parameter Setting Registers
S3C2416X RISC MICROPROCESSOR 5.3 PARAMETER SETTING REGISTERS Resolution 5.3.1 Source Image Resolution Register (SRC_RES_REG) Register Address Description Reset Value SRC_RES_REG 0x4D408200 Source Image Resolution Register Field Description Initial State Reserved [31:27] VertRes [26:16] Vertical resolution of source image. Range: 1 ~ 2040 Reserved [15:11] HoriRes...
Page 416 S3C2416X RISC MICROPROCESSOR 5.3.4 Screen Resolution Register (SC_RES_REG) Register Address Description Reset Value SC_RES_REG 0x4D408210 Screen Resolution Register Field Description Initial State Reserved [31:27] − VertRes [26:16] Vertical resolution of the screen. Range: 1 ~ 2040 Reserved [15:11] − HoriRes [10:0] Horizontal resolution of the screen.
Page 417 S3C2416X RISC MICROPROCESSOR Clipping Window 5.3.7 LeftTop Clipping Window Register (CW_LT_REG) Register Address Description Reset Value CW_LT_REG 0x4D408220 LeftTop Clipping Window Register Field Description Initial State Reserved [31:27] − TopCW_Y [26:16] Top Y Clipping Window Requirement: TopCW_Y < BottomCW_Y Reserved [15:11] −...
Page 418 S3C2416X RISC MICROPROCESSOR 5.3.10 RightBottom Clipping Window Register (CW_RB_REG) Register Address Description Reset Value CW_RB_REG 0x4D408230 RightBottom Clipping Window Register Field Description Initial State Reserved [31:27] − BottomCW_Y [26:16] Bottom Y Clipping Window Requirement: BottomCW_Y < VeriRes (SC_VERI_RES_REG) Reserved [15:11] −...
Page 419 S3C2416X RISC MICROPROCESSOR Coordinates 5.3.13 COORDINATE_0 Register (COORD0_REG) Register Address Description Reset Value COORD0_REG 0x4D408300 Coordinate_0 Register Field Description Initial State Reserved [31:27] − [26:16] Coordinate_0 Y Range: 0 ~ 2039 Reserved [15:11] − [10:0] Coordinate_0 X Range: 0 ~ 2039 5.3.14 COORDINATE_0 X Register (COORD0_X_REG) Register Address...
Page 420 S3C2416X RISC MICROPROCESSOR 5.3.16 COORDINATE_1 Register (COORD1_REG) Register Address Description Reset Value COORD1_REG 0x4D408310 Coordinate_1 Register Field Description Initial State Reserved [31:27] − [26:16] Coordinate_1 Y Range: 0 ~ 2039 Reserved [15:11] − [10:0] Coordinate_1 X Range: 0 ~ 2039 5.3.17 COORDINATE_1 X Register (COORD1_X_REG) Register Address...
Page 421 S3C2416X RISC MICROPROCESSOR 5.3.19 COORDINATE_2 Register (COORD2 _REG) Register Address Description Reset Value COORD2_REG 0x4D408320 Coordinate_2 Register Field Description Initial State Reserved [31:27] − [26:16] Coordinate_2 Y Range: 0 ~ 2039 Reserved [15:11] − [10:0] Coordinate_2 X Range: 0 ~ 2039 5.3.20 COORDINATE_2 X Register (COORD2_X_REG) Register Address...
Page 422 S3C2416X RISC MICROPROCESSOR 5.3.22 COORDINATE_3 REGISTER (COORD3 _REG) Register Address Description Reset Value COORD3_REG 0x4D408330 Coordinate_3 Register Field Description Initial State Reserved [31:27] − [26:16] Coordinate_3 Y Range: 0 ~ 2039 Reserved [15:11] − [10:0] Coordinate_3 X Range: 0 ~ 2039 5.3.23 COORDINATE_3 X Register (COORD3_X_REG) Register Address...
Page 423 S3C2416X RISC MICROPROCESSOR Rotation 5.3.25 Rotation Origin Coordinate Register (ROT_OC_REG) Register Address Description Reset Value ROT_OC_REG 0x4D408340 Rotation Origin Coordinate Register Field Description Initial State Reserved [31:27] − [26:16] X coordinate of the reference point of rotation Range: 0 ~ 2039 Reserved [15:11] −...
Page 424 S3C2416X RISC MICROPROCESSOR 5.3.28 Rotation Register (ROTATE_REG) Register Address Description Reset Value ROTATE_REG 0x4D40834C Rotation Register Field Description Initial State Reserved [31:6] Y-flip X-flip 270° Rotation 180° Rotation 90° Rotation 0° Rotation If the two or more of Rn are set to 1 at the same time, drawing engine operates unpredictably. 18-30...
Page 425 S3C2416X RISC MICROPROCESSOR X,Y Increment Setting 5.3.29 X Increment Register (X_INCR_REG) Register Address Description Reset Value X_INCR_REG 0x4D408400 X Increment Register Field Description Initial State Reserved [31:22] − X_INCR [21:0] X increment value (2’s complement, 11-digit fraction) 5.3.30 Y Increment Register (Y_INCR_REG) Register Address Description...
Page 426 S3C2416X RISC MICROPROCESSOR ROP & Alpha Setting 5.3.31 Raster Operation Register (ROP_REG) Register Address Description Reset Value ROP_REG 0x4D408410 Raster Operation Register Field Description Initial State Reserved [31:14] − [13] Third Operand Select : 1’b0 = Pattern 1’b1 = Foreground Color [12:10] Alpha Mode : 3’b000 = No Alpha Blending...
Page 427 S3C2416X RISC MICROPROCESSOR Color 5.3.33 Foreground Color Register (FG_COLOR_REG) Register Address Description Reset Value FG_COLOR_REG 0x4D408500 Foreground Color Register Field Description Initial State ForegroundColor [31:0] Foreground Color Value. The alpha field of the foreground color will be discarded. 5.3.34 Backround Color Register (BG_COLOR_REG) Register Address Description...
Page 428 S3C2416X RISC MICROPROCESSOR 5.3.36 Source Image Color Mode Register (SRC_COLOR_MODE_REG) Register Address Description Reset Value SRC_COLOR_ 0x4D408510 Source Image Color Mode Register MODE_REG Field Description Initial State Reserved [31:5] − Narrow 1 = YUV narrow range (Y:16-235, UV: 16-240) 0 = YUV wide range (YUV: 0-255) 1 = YUV mode 0 = RGB mode This bit should be set to 0 in point/line drawing mode and color...
Page 429 S3C2416X RISC MICROPROCESSOR Pattern 5.3.38 Pattern Register (PAT_REG) Register Address Description Reset Value PAT_REG 0x4D408600 ~ 67C Pattern Register Field Description Initial State PAT_REG [31:0] Pattern Register 5.3.39 Pattern Offset Register (PATOFF_REG) Register Address Description Reset Value PATOFF_REG 0x4D408700 Pattern Offset Register Field Description Initial State...
Page 430 S3C2416X RISC MICROPROCESSOR Stencil Test 5.3.42 Colorkey Control Register (COLORKEY_CTRL_REG) Register Address Description Reset Value COLORKEY_CTRL 0x4D408720 Colorkey Control Register _REG Field Description Initial State Reserved [31:5] − StencilInverse 0 = Normal stencil test 1 = Inversed stencil test This bit should be set to 0 if the stencil test of every color field is disabled.
Page 431 S3C2416X RISC MICROPROCESSOR 5.3.44 COLORKEY DECISION REFERENCE MAXIMUM REGISTER (COLORKEY_DR_MAX_REG) Register Address Description Reset Value COLORKEY_DR_ 0x4D408728 Colorkey Decision Reference Maximum Register 0xFFFF_FFFF MAX_REG Field Description Initial State A_DR(max) [31:24] Alpha DR MAX value R_DR(max) [23:16] RED DR MAX value G_DR(max) [15:8] GREEN DR MAX value...
Page 432 S3C2416X RISC MICROPROCESSOR NOTES 18-38...
Page 433: Chapter 19 Hs_Spi Controller
S3C2416X RISC MICROPROCESSOR HS_SPI CONTROLLER HS_SPI CONTROLLER 1 OVERVIEW The High Speed Serial Peripheral Interface (HS_SPI) can interface the serial data transfer. HS_SPI has two 8/16/32-bit shift registers for transmission and receiving, respectively. During an HS_SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). HS_SPI supports the protocols for National Semiconductor Microwire and Motorola Serial Peripheral Interface.
Page 434: Signal Descriptions
HS_SPI CONTROLLER S3C2416X RISC MICROPROCESSOR 3 SIGNAL DESCRIPTIONS The following table lists the external signals between the HS_SPI and external device. All ports of the HS_SPI can be used as General Purpose I/O ports when disable. See “General Purpose I/O” chapter for detailed pin configuration.
Page 435: Operation Mode
4.2 FIFO ACCESS The HS_SPI in S3C2416 supports CPU access and DMA access to FIFOs. Data size of CPU access and DMA access to FIFOs can be selected 8-bit/16-bit/32-bit data. If 8-bit data size is chosen, valid bits are from 0 bit to 7 bit.
Page 436: Hs_Spi Transfer Format
HS_SPI CONTROLLER S3C2416X RISC MICROPROCESSOR 4.6 HS_SPI TRANSFER FORMAT The S3C2416 supports 4 different format to transfer the data. Figure 20-1 shows four waveforms for HS_SPICLK. CPOL = 0, CPHA = 0 (Format A) Cycle SPICLK MOSI MISO *MSB *MSB : MSB of previous frame...
Page 437: Special Function Register Descriptions
S3C2416X RISC MICROPROCESSOR HS_SPI CONTROLLER 5 SPECIAL FUNCTION REGISTER DESCRIPTIONS 5.1 SETTING SEQUENCE OF SPECIAL FUNCTION REGISTER Special Function Register should be set as the following sequence. (nCS manual mode) 1. Set Transfer Type. (CPOL & CPHA set) 2. Set Clock configuration register. 3.
Page 438: Special Function Register
HS_SPI CONTROLLER S3C2416X RISC MICROPROCESSOR 5.2 SPECIAL FUNCTION REGISTER Register Address Description Reset Value CH_CFG(Ch0) 0x52000000 HS_SPI configuration register 0x0000_0040 CH_CFG Description Initial State Reserved [31:7] 26’b0 − High_speed_en 0 = Low speed operation support at slave mode. 1’b1 1 = High speed operation support at slave mode. SW_RST Software reset 1’b0...
Page 439 S3C2416X RISC MICROPROCESSOR HS_SPI CONTROLLER Register Address Description Reset Value Clk_CFG(Ch0) 0x52000004 Clock configuration register Clk_CFG Description Initial State ClkSel [10:9] Clock source selection to generate HS_SPI clock-out 2’b0 00 = PCLK 01 = USBCLK 10 = Epll clock 11 = Reserved For using USBCLK source, The USB_SIG_MASK at system controller should be set to on.
Page 440 HS_SPI CONTROLLER S3C2416X RISC MICROPROCESSOR Register Address Description Reset Value MODE_CFG(Ch0) 0x52000008 HS_SPI FIFO control register MODE_CFG Description Initial State Ch_tran_size [30:29] 00 = Byte 2’b0 01 = Halfword 10 = Word 11 = Reserved Trailing Count [28:19] Count value from writing the last data in RX FIFO to flush 10’b0 trailing bytes in FIFO 00 = Byte...
Page 441 S3C2416X RISC MICROPROCESSOR HS_SPI CONTROLLER Register Address Description Reset Value Slave_slection_reg(Ch0) 0x5200000C Slave selection signal Slave_slection_reg Description Initial State nSSout inactive time = nCS_time_count [9:4] 6’b0 ((nCS_time_count+3)/2) x HS_SPICLKout) reserved [3:2] Reserved − Chip select toggle manual or auto selection Auto_n_Manual 1’b0 0 = Manual...
Page 442 HS_SPI CONTROLLER S3C2416X RISC MICROPROCESSOR Register Address Description Reset Value HS_SPI_STATUS(Ch0 0x52000014 HS_SPI status register HS_SPI_STATUS Description Initial State Indication of transfer done in Shift register 0 = all case except blow case TX_done [21] 1’b0 1 = when tx fifo and shift register are empty * Master mode only Trailing_count_done [20]...
Page 443 S3C2416X RISC MICROPROCESSOR HS_SPI CONTROLLER Register Address Description Reset Value HS_SPI_TX_DATA(Ch0) 0x52000018 HS_SPI TX DATA register HS_SPI_TX_DATA Description Initial State This field contains the data to be transmitted over the TX_DATA [31:0] 32’b0 HS_SPI channel. Register Address Description Reset Value HS_SPI_RX_DATA(Ch0) 0x5200001C HS_SPI RX DATA register...
Page 444 HS_SPI CONTROLLER S3C2416X RISC MICROPROCESSOR Register Address Description Reset Value Pending_clr_reg(Ch0) 0x52000024 R/W Pending clear register Status_Pending_ Description Initial State clear_reg TX underrun pending clear bit TX_underrun_clr 1’b0 0 = Non-clear 1 = Clear TX overrun pending clear bit TX_overrun_clr 1’b0 0 = Non-clear 1 = Clear...
Page 445 S3C2416X RISC MICROPROCESSOR HS_SPI CONTROLLER Register Address Description Reset Value SWAP_CFG(Ch0) 0x52000028 R/W SWAP config register SWAP_CFG Description Initial State RX_Half-word swap 0 = off 1 = swap 1’b0 RX_Byte swap 0 = off 1 = swap 1’b0 RX_Bit swap 0 = off 1 = swap 1’b0...
Page 446 HS_SPI CONTROLLER S3C2416X RISC MICROPROCESSOR NOTES 19-14...
Page 447: Chapter 20 Sd/Mmc Host Controller
S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER SD/MMC HOST CONTROLLER This chapter describes the SD/SDIO/MMC/CE-ATA host controller and related registers supported by S3C2416X RISC microprocessor. 1 OVERVIEW The HSMMC (High-speed MMC) SDMMC is a combo host for Secure Digital card and MultiMedia Card. This host is compatible for SD Association’s (SDA) Host Standard Specification.
Page 448: Block Diagram
HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR 3 BLOCK DIAGRAM BaseCLK HCLK SDCLK Domain Domain Status Clock Control INTREQ Status CMDRSP System Bus packet (AHB) Line Control Control Control FIFO AHB slave I/F Control Control Status DPSRAM controller DATA AHB master packet Figure 20-1.
Page 449: Sequence
S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER 4 SEQUENCE This section defines basic sequence flow chart divided into several sub sequences. “Wait for interrupts” is used in the flow chart. This means the Host Driver waits until specified interrupts are asserted. If already asserted, then fall through that step in the flow chart.
Page 450: Sd Clock Supply Sequence
HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR 4.2 SD CLOCK SUPPLY SEQUENCE START Calculate a divisor for SD Clock frequency Set SDCLK frequency select and Internal Clock Enable Check Internal Clock Enable Set SD Clock ON Figure 20-3. SD Clock Supply Sequence The sequence for supplying SD Clock to a SD card is described in Figure 20-3.
Page 451: Sd Clock Stop Sequence
S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER 4.3 SD CLOCK STOP SEQUENCE START Set SD Clock OFF Stop SD Clock Figure 20-4. SD Clock Stop Sequence The flow chart for stopping the SD Clock is shown in Figure 20-4. The Host Driver shall not stop the SD Clock when a SD transaction is occurring on the SD Bus -- namely, when either Command Inhibit (DAT) or Command Inhibit (CMD) in the Present State register is set to 1.
Page 452: Sd Bus Power Control Sequence
HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR 4.5 SD BUS POWER CONTROL SEQUENCE START Get the support voltage of the Host Controller Set SD Bus voltage select with supported maximum voltage Set SD Bus Power Get OCR value of the SD Card no change SD Bus voltage changed ?
Page 453: Change Bus Width Sequence
S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER 4.6 CHANGE BUS WIDTH SEQUENCE START Disable Card Interrupt in Host SD Memory Only Card ? SD Memory Only Card ? Mask Card Interrupt in Card Enable Card Interrupt in Card Change Bit Mode in Card Enable Card Interrupt in Host Change Bit Mode for Host Figure 20-7.
Page 454: Timeout Setting For Dat Line
HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR 4.7 TIMEOUT SETTING FOR DAT LINE START Calculate a Divisor for detecting Timeout Set Timeout Detection Timer Figure 20-8. Timeout Setting Sequence In order to detect timeout errors on DAT line, the Host Driver shall execute the following two steps before any SD transaction.
Page 455: Sd Command Issue Sequence
S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER 4.9 SD COMMAND ISSUE SEQUENCE Figure 20-9. Timeout Setting Sequence 20-9...
Page 456: Command Complete Sequence
HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR (1) Check Command Inhibit (CMD) in the Present State register. Repeat this step until Command Inhibit (CMD) is 0. That is, when Command Inhibit (CMD) is 1, the Host Driver shall not issue a SD Command. (2) If the Host Driver issues a SD Command with busy signal, go to step (3).
Page 457: Command Complete Sequence
S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER START Wait for Command Complete Int Command Complete Int occur Clr Command Complete Status Get Response Data Command with Transfer Complete Int ? Wait for Transfer Complete Int Transfer Complete Int occur Clr Transfer Complete Status Error Check Response Data ? No error...
Page 458: Transaction Control With Data Transfer Using Dat Line
HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR 4.11 TRANSACTION CONTROL WITH DATA TRANSFER USING DAT LINE Depending on whether DMA (optional) is used or not, there are two execution methods. The sequence not using DMA is shown in Figure 20-11 and the sequence using DMA is shown in Figure 20-12. In addition, the sequences for SD transfers are basically classified into following three kinds according to how the number of blocks is specified : 1) Single Block Transfer:...
Page 459 S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER START Set Block Size Reg Set Command Reg Wait for Command Set Block Count Reg Complete Int Command Complete Int occur Set Argument Reg Clr Command Complete Status Set Transfer Mode Reg Get Response Data write read Write or Read ?
Page 460 HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR (1) Set the value corresponding to the executed data byte length of one block to Block Size register. (2) Set the value corresponding to the executed data block count to Block Count Register. (3) Set the value corresponding to the issued command to Argument register. (4) Set the value to Multi / Single Block Select and Block Count Enable.
Page 461: Transaction Control With Data Transfer Using Dat Line Sequence (Using Dma)
S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER START Set System Address Reg (10) Set Block Size Reg Wait for Transfer Complete Int and DMA Int Set Block Count Reg Transfer Complete Int (11) occur Check Interrupt Status Set Argument Reg DMA Int occur (12) Set Transfer Mode Reg Clr DMA Status Interrupt...
Page 462: Abort Transaction
HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR (10) Wait for the Transfer Complete Interrupt and DMA Interrupt. (11) If Transfer Complete(STATRANCMPLT) is set 1, go to Step (14) else if DMA Interrupt is set to 1, go to Step (12). Transfer Complete is higher priority than DMA Interrupt. (12) Write 1 to the DMA Interrupt in the Normal Interrupt Status register to clear this bit.
Page 463: Sdi Special Registers
S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER 5 SDI SPECIAL REGISTERS 5.1 CONFIGURATION REGISTER TYPES Configuration register fields are assigned one of the attributes described below : Register Description Attribute Read-only register: Register bits are read-only and cannot be altered by software or any reset operation.
Page 464: Sdma System Address Register
HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR 5.2 SDMA SYSTEM ADDRESS REGISTER Register Address Description Reset Value SYSAD0 0X4AC00000 System Address register (Channel 0) SYSAD1 0X4A800000 System Address register (Channel 1) This register contains the physical system memory address used for DMA transfers. Name Description Initial Value...
Page 465: Block Size Register
S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER 5.3 BLOCK SIZE REGISTER This register is used to configure the number of bytes in a data block. Register Address Description Reset Value BLKSIZE0 0X4AC00004 Host DMA Buffer Boundary and Transfer Block Size Register (Channel 0) BLKSIZE1 0X4A800004 Host DMA Buffer Boundary and Transfer Block Size...
Page 466 HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR Name Description Initial Value BLKSIZE [11:0] Transfer Block Size This register specifies the block size of data transfers for CMD17, CMD18, CMD24, CMD25, and CMD53. Values ranging from 1 up to the maximum buffer size can be set. In case of memory, it shall be set up to 512 bytes.
Page 467: Block Count Register
S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER 5.4 BLOCK COUNT REGISTER This register is used to configure the number of data blocks. Register Address Description Reset Value BLKCNT0 0X4AC00006 Blocks Count For Current Transfer (Channel 0) BLKCNT1 0X4A800006 Blocks Count For Current Transfer (Channel 1) Name Description Initial Value...
Page 468: Argument Register
HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR 5.5 ARGUMENT REGISTER This register contains the SD Command Argument. Register Address Description Reset Value ARGUMENT0 0X4AC00008 Command Argument Register (Channel 0) ARGUMENT1 0X4A800008 Command Argument Register (Channel 1) Name Description Initial Value ARGUMENT [31:0] Command Argument The SD Command Argument is specified as bit39-8 of Command- Format in the SD Memory Card Physical Layer Specification.
Page 469: Transfer Mode Register
S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER 5.6 TRANSFER MODE REGISTER This register is used to control the operation of data transfers. The Host Driver shall set this register before issuing a command which transfers data (see Data Present Select in the Command register), or before issuing a Resume command.
Page 470: Determination Of Transfer Type
HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR Name Description Initial Value ENBLKCNT Block Count Enable This bit is used to enable the Block Count register, which is only relevant for multiple block transfers. When this bit is 0, the Block Count register is disabled, which is useful in executing an infinite transfer.
Page 471: Command Register
S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER 5.7 COMMAND REGISTER This register contains the SD Command Argument. Register Address Description Reset Value CMDREG0 0X4AC0000E Command Register (Channel 0) CMDREG1 0X4A80000E Command Register (Channel 1) The Host Driver shall check the Command Inhibit (DAT) bit and Command Inhibit (CMD) bit in the Present State register before writing to this register.
Page 472: Relation Between Parameters And The Name Of Response Type
HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR Name Description Initial Value DATAPRNT Data Present Select This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line. It is set to 0 for the following: (1) Commands using only CMD line (ex.
Page 473: Response Register
S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER NOTES: In the SDIO specification, response type notation of R5b is not defined. R5 includes R5b in the SDIO specification. But R5b is defined in this specification to specify the Host Controller shall check busy after receiving response. For example, usually CMD52 is used as R5 but I/O abort command shall be used as R5b.
Page 474 HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR The Response Field indicates bit positions of “Responses” defined in the PHYSICAL LAYER SPECIFICATION Version 1.01. The Table (upper) shows that most responses with a length of 48 (R[47:0]) have 32 bits of the response data (R[39:8]) stored in the Response register at REP[31:0]. Responses of type R1b (Auto CMD12 responses) have response data bits R[39:8] stored in the Response register at REP[127:96].
Page 475: Buffer Data Port Register
S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER 5.9 BUFFER DATA PORT REGISTER 32-bit data port register to access internal buffer. Register Address Description Reset Value BDATA0 0X4AC00020 Buffer Data Register (Channel 0) − BDATA1 0X4A800020 Buffer Data Register (Channel 1) − Name Description Initial Value BUFDAT...
Page 476: Present State Register
HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR 5.10 PRESENT STATE REGISTER This register contains the SD Command Argument. Register Address Description Reset Value PRNSTS0 0X4AC00024 RO/ROC Present State Register (Channel 0) 0x000A0000 Present State Register (Channel 1) PRNSTS1 0X4A800024 RO/ROC 0x000A0000 Name Description Initial Value [31:25] Reserved...
Page 477 S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER Name Description Initial Value 0 = Reset or Debouncing INSCARD [16] Card Inserted (RO) This bit indicates whether a card has been inserted. The Host Controller shall debounce this signal so that the Host Driver will not need to wait for it to stabilize.
Page 478 HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR Name Description Initial Value BUFWTRDY [10] Buffer Write Enable (ROC) This status is used for non-DMA write transfers. The Host Controller can implement multiple buffers to transfer data efficiently. This read only flag indicates if space is available for write data. If this bit is 1, data can be written to the buffer.
Page 479 S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER Name Description Initial Value [7:3] Reserved DATLINEACT DAT Line Active (ROC) This bit indicates whether one of the DAT line on SD Bus is in use. (a) In the case of read transactions This status indicates if a read transfer is executing on the SD Bus. Changes in this value from 1 to 0 between data blocks generate a Block Gap Event interrupt in the Normal Interrupt Status register.
Page 480: Card Detect State
HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR Name Description Initial Value Changing from 1 to 0 generates a Transfer Complete interrupt in the Normal Interrupt Status register. Note: The SD Host Driver can save registers in the range of 000- 00Dh for a suspend transaction after this bit has changed from 1 to 1 = Cannot issue command which uses the DAT line 0 = Can issue command which uses the DAT line CMDINHCMD...
Page 481: Timing Of Command Inhibit (Dat) And Command Inhibit (Cmd) With Data Transfer
S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER Figure 20-14. Timing of Command Inhibit (DAT) and Command Inhibit (CMD) with data transfer Figure 20-15. Timing of Command Inhibit (DAT) for the case of response with busy Figure 20-16. Timing of Command Inhibit (CMD) for the case of no response command 20-35...
Page 482: Host Control Register
HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR 5.11 HOST CONTROL REGISTER This register contains the SD Command Argument. Register Address Description Reset Value HOSTCTL0 0X4AC00028 Present State Register (Channel 0) HOSTCTL1 0X4A800028 Present State Register (Channel 1) Name Description Initial Value CDSIGSEL Reserved This field should be fixed to LOW CDTESTLVL...
Page 483: Power Control Register
S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER 5.12 POWER CONTROL REGISTER This register contains the SD Command Argument. Register Address Description Reset Value PWRCON0 0X4AC00029 Present State Register (Channel 0) PWRCON1 0X4A800029 Present State Register (Channel 1) Name Description Initial Value [7:4] Reserved SELPWRLVL [3:1]...
Page 484: Block Gap Control Register
HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR 5.13 BLOCK GAP CONTROL REGISTER This register contains the SD Command Argument. Register Address Description Reset Value BLKGAP0 0X4AC0002A Block Gap Control Register (Channel 0) BLKGAP1 0X4A80002A Block Gap Control Register (Channel 1) Name Description Initial Value [7:4] Reserved...
Page 485 S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER Name Description Initial Value This bit is used to stop executing a transaction at the next block gap for both DMA and non-DMA transfers. Until the Transfer Complete is set to 1, indicating a transfer completion the Host Driver shall leave this bit set to 1.
Page 486: Wakeup Control Register
HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR 5.14 WAKEUP CONTROL REGISTER This register is mandatory for the Host Controller, but wakeup functionality depends on the Host Controller system hardware and software. The Host Driver shall maintain voltage on the SD Bus, by setting SD Bus Power to 1 in the Power Control register, when wakeup event via Card Interrupt is desired.
Page 487: Clock Control Register
S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER 5.15 CLOCK CONTROL REGISTER At the initialization of the Host Controller, the Host Driver shall set the SDCLK Frequency Select according to the Capabilities register. Register Address Description Reset Value CLKCON0 0X4AC0002C Command Register (Channel 0) CLKCON1 0X4A80002C Command Register (Channel 1)
Page 488 HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR Name Description Initial Value STBLEXTCLK External Clock Stable This bit is set to 1 when SD Clock output is stable after writing to SD Clock Enable in this register to 1. The SD Host Driver shall wait to issue command to start until this bit is set to 1.
Page 489: Timeout Control Register
S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER 5.16 TIMEOUT CONTROL REGISTER At the initialization of the Host Controller, the Host Driver shall set the Data Timeout Counter Value according to the Capabilities register. Register Address Description Reset Value TIMEOUTCON 0 0X4AC0002E Timeout Control Register (Channel 0) TIMEOUTCON 1 0X4A80002E Timeout Control Register (Channel 1) Name...
Page 490: Software Reset Register
HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR 5.17 SOFTWARE RESET REGISTER A reset pulse is generated when writing 1 to each bit of this register. After completing the reset, the Host Controller shall clear each bit. Because it takes some time to complete software reset, the SD Host Driver shall confirm that these bits are 0.
Page 491 S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER Name Description Initial Value RSTDAT Software Reset For All This reset affects the entire Host Controller except for the card detection circuit. Register bits of type ROC, RW, RW1C, RWAC are cleared to 0. During its initialization, the Host Driver shall set this bit to 1 to reset the Host Controller.
Page 492: Normal Interrupt Status Register
HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR 5.18 NORMAL INTERRUPT STATUS REGISTER The Normal Interrupt Status Enable affects reads of this register, but Normal Interrupt Signal Enable does not affect these reads. An interrupt is generated when the Normal Interrupt Signal Enable is enabled and at least one of the status bits is set to 1.
Page 493 S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER Name Description Initial Value detect the Card Interrupt without SD Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled during the interrupt cycle, so there are some sample delays between the interrupt signal from the SD card and the interrupt to the Host System.
Page 494 HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR Name Description Initial Value STADMAINT DMA Interrupt This status is set if the Host Controller detects the Host DMA Buffer boundary during transfer. Refer to the Host DMA Buffer Boundary in the Block Size register. Other DMA interrupt factors may be added in the future.
Page 495 S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER Name Description Initial Value The table below shows that Transfer Complete has higher priority than Data Timeout Error. If both bits are set to 1, the data transfer can be considered complete. Relation between Transfer Complete and Data Transfer Data Timeout Meaning of the status...
Page 496: Error Interrupt Status Register
HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR 5.19 ERROR INTERRUPT STATUS REGISTER Signals defined in this register can be enabled by the Error Interrupt Status Enable register, but not by the Error Interrupt Signal Enable register. The interrupt is generated when the Error Interrupt Signal Enable is enabled and at least one of the statuses is set to 1.
Page 497 S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER Name Description Initial Value Occurs when detecting one of following timeout conditions. (1) Busy timeout for R1b,R5b type (2) Busy timeout after Write CRC status (3) Write CRC Status timeout (4) Read Data timeout. 1 = Timeout 0 = No Error STACMDIDXERR Command Index Error...
Page 498: The Relation Between Command Crc Error And Command Timeout Error
HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR The relation between Command CRC Error and Command Timeout Error is shown in Table below. Table 21-4. The relation between Command CRC Error and Command Timeout Error Command CRC Error Command Timeout Error Kinds of error No Error Response Timeout Error Response CRC Error...
Page 499: Normal Interrupt Status Enable Register
S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER 5.20 NORMAL INTERRUPT STATUS ENABLE REGISTER Setting to 1 enables Interrupt Status. Register Address Description Reset Value NORINTSTSEN0 0X4AC00034 Normal Interrupt Status Enable Register (Channel 0) NORINTSTSEN1 0X4A800034 Normal Interrupt Status Enable Register (Channel 1) Name Description Initial Value...
Page 500 HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR Name Description Initial Value ENSTACARDNS Card Insertion Status Enable 1 = Enabled 0 = Masked ENSTABUFRDRDY Buffer Read Ready Status Enable 1 = Enabled 0 = Masked ENSTABUFWTRDY Buffer Write Ready Status Enable 1 = Enabled 0 = Masked ENSTADMA DMA Interrupt Status Enable...
Page 501: Error Interrupt Status Enable Register
S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER 5.21 ERROR INTERRUPT STATUS ENABLE REGISTER Setting to 1 enables Error Interrupt Status. Register Address Description Reset Value ERRINTSTSEN0 0X4AC00036 Error Interrupt Status Enable Register (Channel 0) ERRINTSTSEN1 0X4A800036 Error Interrupt Status Enable Register (Channel 1) Name Description Initial Value...
Page 502: Normal Interrupt Signal Enable Register
HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR 5.22 NORMAL INTERRUPT SIGNAL ENABLE REGISTER This register is used to select which interrupt status is indicated to the Host System as the interrupt. These status bits all share the same1 bit interrupt line. Setting any of these bits to 1 enables interrupt generation. Register Address Description...
Page 503 S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER Name Description Initial Value ENSIGBUFRDRDY Buffer Read Ready Signal Enable 1 = Enabled 0 = Masked ENSIGBUFWTRDY Buffer Write Ready Signal Enable 1 = Enabled 0 = Masked ENSIGDMA DMA Interrupt Signal Enable 1 = Enabled 0 = Masked ENSIGBLKGAP Block Gap Event Signal Enable...
Page 504: Error Interrupt Signal Enable Register
HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR 5.23 ERROR INTERRUPT SIGNAL ENABLE REGISTER This register is used to select which interrupt status is notified to the Host System as the interrupt. These status bits all share the same 1 bit interrupt line. Setting any of these bits to 1 enables interrupt generation. Register Address Description...
Page 505: Autocmd12 Error Status Register
S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER 5.24 AUTOCMD12 ERROR STATUS REGISTER When Auto CMD12 Error Status is set, the Host Driver shall check this register to identify what kind of error Auto CMD12 indicated. This register is valid only when the Auto CMD12 Error is set. Register Address Description...
Page 506: The Relation Between Command Crc Error And Command Timeout Error
HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR The relation between Auto CMD12 CRC Error and Auto CMD12 Timeout Error is shown below. Table 21-5. The Relation Between Command CRC Error and Command Timeout Error Auto CMD12 CRC Error Auto CMD12 Timeout Error Kinds of error No Error Response Timeout Error...
Page 507: Capabilities Register
S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER 5.25 CAPABILITIES REGISTER This register provides the Host Driver with information specific to the Host Controller implementation. The Host Controller may implement these values as fixed or loaded from flash memory during power on initialization. Refer to Software Reset for All in the Software Reset register for loading from flash memory and completion timing control.
Page 508 HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR Name Description Initial Value CAPAMAXBLKLEN [17:16] Max Block Length (HWInit) This value indicates the maximum block size that the Host Driver can read and write to the buffer in the Host Controller. The buffer shall transfer this block size without wait cycles. Three sizes can be defined as indicated below.
Page 509: Maximum Current Capabilities Register
S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER 5.26 MAXIMUM CURRENT CAPABILITIES REGISTER These registers indicate maximum current capability for each voltage. The value is meaningful if Voltage Support is set in the Capabilities register. If this information is supplied by the Host System via another method, all Maximum Current Capabilities register shall be 0.
Page 510: Control Register 2
HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR 5.27 CONTROL REGISTER 2 Register Address Description Reset Value CONTROL2_0 0X4AC00080 Control register 2 (Channel 0) CONTROL2_1 0X4A800080 Control register 2 (Channel 1) Name Description Initial Value [31] Write Status Clear Async Mode Enable This bit can make async-clear enable about Normal and Error interrupt status bit.
Page 511 S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER Name Description Initial Value Card Detect Pin Level does not simply reflect SDCD# pin, but chooses from SDCD, DAT[3], or CDTestlvl depending on CDSigSel and this field (SDCDSel) values 0 = nSDCD is used for SD Card Detect Signal 1 = DAT[3] is used for SD Card Detect Signal CDSYNCSEL [12]...
Page 512 HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR Name Description Initial Value PWRSYNC SD OP Power Sync Support with SD Card This field is used to enable input CMD and DAT referencing SD Bus Power bit in the “PWRCON register”, when being set. 0 = No Sync, no switch input enable signal (Command, Data) 1 = Sync, control input enable signal (Command, Data) Reserved...
Page 513 S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER 5.28 CONTROL REGISTER 3 Register Address Description Reset Value CONTROL3_0 0X4AC00084 FIFO Interrupt Control (Control Register 3) 0x7F5F3F1F (Channel 0) CONTROL3_1 0X4A800084 FIFO Interrupt Control (Control Register 3) 0x7F5F3F1F (Channel 1) Name Description Initial Value FCSEL3 [31] Feedback Clock Select [3]...
Page 514: Control Register 3
HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR 5.29 DEBUG REGISTER Register Address Description Reset Value DEBUG_0 0X4AC00088 DEBUG register (Channel 0) Not fixed DEBUG_1 0X4A800088 DEBUG register (Channel 1) Not fixed Name Description Initial Value DBGREG [31:0] Not fixed Debug Register Read Only Register for Debug Purpose (RO) 5.30 CONTROL REGISTER 4 Register Address...
Page 515: Force Event Register For Auto Cmd12 Error Status
S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER 5.31 FORCE EVENT REGISTER FOR AUTO CMD12 ERROR STATUS Register Address Description Reset Value FEAER0 0X4AC00050 Force Event Auto CMD12 Error Interrupt 0x0000 Register Error Interrupt (Channel 0) FEAER1 0X4A800050 Force Event Auto CMD12 Error Interrupt 0x0000 Register Error Interrupt (Channel 1) The Force Event Register is not a physically implemented register.
Page 516: Force Event Register For Error Interrupt Status
HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR 5.32 FORCE EVENT REGISTER FOR ERROR INTERRUPT STATUS Register Address Description Reset Value FEERR0 0X4AC00052 Force Event Error Interrupt Register Error Interrupt 0x0000 (Channel 0) FEERR1 0X4A800052 Force Event Error Interrupt Register Error Interrupt 0x0000 (Channel 1) The Force Event Register is not a physically implemented register.
Page 517: Adma Error Status Register
S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER 5.33 ADMA ERROR STATUS REGISTER When ADMA Error Interrupt is occurred, the ADMA Error States field in this register holds the ADMA state and the ADMA System Address Register holds the address around the error descriptor. For recovering the error, the Host Driver requires the ADMA state to identify the error descriptor address as follows: •...
Page 518 HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR Name Description Initial Value [1:0] ADMA Error State This field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates "10" because ADMA never stops in this state. D01 −...
Page 519: Adma System Address Register
S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER 5.34 ADMA SYSTEM ADDRESS REGISTER This register contains the physical Descriptor address used for ADMA data transfer. Register Address Description Reset Value ADMASYSADDR0 0X4AC00058 ADMA System Address Register (Channel 0) 0x00 ADMASYSADDR1 0X4A800058 ADMA System Address Register (Channel 1) 0x00 Name Description...
Page 520: Host Controller Version Register
HSMMC CONTROLLER S3C2416X RISC MICROPROCESSOR 5.35 HOST CONTROLLER VERSION REGISTER Register Address Description Reset Value HCVER0 0X4AC000FE HWInit Host Controller Version Register (Channel 0) 0x0401 HCVER1 0X4A8000FE HWInit Host Controller Version Register (Channel 1) 0x0401 Name Description Initial Value VENVER [15:8] 0x04 Vendor Version Number...
Page 521: Overview
S3C2416X RISC MICROPROCESSOR LCD CONTROLLER LCD CONTROLLER 1 OVERVIEW The LCD controller consists of logic for transferring image data from a video buffer located in system memory to an external LCD driver interface. LCD driver interface has two kind of interface. One is conventional RGB- interface and the other is i80-System interface.
Page 522: Chapter 21 Lcd Controller
LCD CONTROLLER S3C2416X RISC MICROPROCESSOR 1.1 FEATURES 1.1.1 The features of LCD controller are: 32-bit AMBA AHB Master /AHB Slave • Bus Interface • Video Output Interface RGB Parallel I/F (24-bit) RGB Serial I/F (8-bit) i80-System I/F (18-bit) • PIP (OSD) function Supports X,Y indexed position Supports 4-bit Alpha blending : Plane / Pixel(only supports 24-bit 8:8:8 mode)
Page 523: Functional Description
S3C2416X RISC MICROPROCESSOR LCD CONTROLLER 2 FUNCTIONAL DESCRIPTION 2.1 BRIEF OF THE SUB-BLOCK The LCD controller consists of a VSFR, VDMA, VPRCS, VTIME, and video clock generator. The VSFR has 71 programmable register sets and two-256x25 palette memory, which are used to configure the LCD controller. The VDMA is a dedicated LCD DMA, which it can transfer the video data in frame memory to VPRCS.
Page 524: Interface
LCD CONTROLLER S3C2416X RISC MICROPROCESSOR AMBA Win0(RGB) Win1(RGB) Blending Color key OUTPUT(RGB) Figure 21-2. Block diagram of the Data Flow 2.3 INTERFACE LCD controller supports 2 types of display device. One type is the conventional RGB-interface that uses RGB data, Vertical/horizontal sync, data valid signal and data sync clock. The Second type is i80-System interface that uses address, data, chip select, read/write control and register/status indicating signal.
Page 525: Overview Of The Color Data
S3C2416X RISC MICROPROCESSOR LCD CONTROLLER 2.4 OVERVIEW OF THE COLOR DATA 2.4.1 RGB Data format The LCD controller requests the specified memory format of frame buffer. The next table shows some examples of each display mode. 2.4.2 28BPP display (A4+888) (BSWP = 0, HWSWP = 0, BLD_PIX = 1, ALPHA_SEL = 1) D[31:28] D[27:24]...
Page 526 LCD CONTROLLER S3C2416X RISC MICROPROCESSOR 2.4.3 25BPP display (A888) (BSWP = 0, HWSWP = 0) D[31:25] D[24] D[23:0] 000H Dummy Bit 004H Dummy Bit 008H Dummy Bit ..LCD Panel NOTES: AEN : Select Alpha value in Window 1 Alpha Value Register for alpha blending AEN = 0 : ALPHA0_R/G/B values are applied.
Page 527 S3C2416X RISC MICROPROCESSOR LCD CONTROLLER 2.4.4 24BPP display (A887) (BSWP = 0, HWSWP = 0) D[31:24] D[23] D[22:0] 000H Dummy Bit 004H Dummy Bit 008H Dummy Bit ..LCD Panel NOTES: AEN : Select Alpha value in Window 1 Alpha Value Register for alpha blending AEN = 0 : ALPHA0_R/G/B values are applied.
Page 528 LCD CONTROLLER S3C2416X RISC MICROPROCESSOR 2.4.5 24BPP display (888) (BSWP = 0, HWSWP = 0) D[31:24] D[23:0] 000H Dummy Bit 004H Dummy Bit 008H Dummy Bit ..LCD Panel NOTE: D[23:16] = Red data, D[15:8] = Green data, D[7:0] = Blue data 21-8...
Page 529 S3C2416X RISC MICROPROCESSOR LCD CONTROLLER 2.4.6 19BPP display (A666) (BSWP = 0, HWSWP = 0) D[31:19] D[18] D[17:0] 000H Dummy Bit 004H Dummy Bit 008H Dummy Bit ..LCD Panel NOTES: AEN : Select Alpha value in Window 1 Alpha Value Register for alpha blending AEN = 0 : ALPHA0_R/G/B values are applied.
Page 530 LCD CONTROLLER S3C2416X RISC MICROPROCESSOR 2.4.7 18BPP display (666) (BSWP = 0, HWSWP = 0) D[31:18] D[17:0] 000H Dummy Bit 004H Dummy Bit 008H Dummy Bit ..LCD Panel ..LCD Panel NOTE: D[17:12] = Red data, D[11:6] = Green data, D[5:0] = Blue data 21-10...
Page 531 S3C2416X RISC MICROPROCESSOR LCD CONTROLLER 2.4.8 16BPP display (A555) (BSWP = 0, HWSWP = 0) D[31] D[30:16] D[15] D[14:0] 000H AEN1 AEN2 004H AEN3 AEN4 008H AEN5 AEN6 (BSWP = 0, HWSWP = 1) [31] D[30:16] D[15] D[14:0] 000H AEN2 AEN1 004H AEN4...
Page 532: Bpp(1+5:5:5, Bswp/Hwswp=0) Display Types
LCD CONTROLLER S3C2416X RISC MICROPROCESSOR 2.4.9 16BPP display (1+555) (BSWP = 0, HWSWP = 0) D[31:16] D[15:0] 000H 004H 008H (BSWP = 0, HWSWP = 1) D[31:16] D[15:0] 000H 004H 008H NOTE: {D[14:10], D[15] } = Red data, {D[9:5], D[15] } = Green data, {D[4:0], D[15]}= Blue data Figure 21-3.
Page 533: Bpp(5:6:5, Bswp/Hwswp=0) Display Types
S3C2416X RISC MICROPROCESSOR LCD CONTROLLER 2.4.10 16BPP display (565) (BSWP = 0, HWSWP = 0) D[31:16] D[15:0] 000H 004H 008H (BSWP = 0, HWSWP = 1) D[31:16] D[15:0] 000H 004H 008H NOTE: D[15:11] = Red data, D[10:5] = Green data, D[4:0] = Blue data Figure 21-4.
Page 534 LCD CONTROLLER S3C2416X RISC MICROPROCESSOR 2.4.11 8BPP display (A232) (BSWP = 0, HWSWP = 0) D[31] D[30:24] D[23] D[22:16] D[15] D[14:8] D[7] D[6:0] 000H AEN1 AEN2 AEN3 AEN4 004H AEN5 AEN6 AEN7 AEN8 008H AEN9 AEN10 AEN11 AEN12 (BSWP = 1, HWSWP = 0) D[31] D[30:24] D[23]...
Page 535 S3C2416X RISC MICROPROCESSOR LCD CONTROLLER 2.4.12 8BPP display (Palette) (BSWP = 0, HWSWP = 0) D[31:24] D[23:16] D[15:8] D[7:0] 000H 004H 008H (BSWP = 1, HWSWP = 0) D[31:24] D[23:16] D[15:8] D[7:0] 000H 004H 008H ..LCD Panel NOTE: The values of frame buffer are index of palette memory. The MSB value of Palette memory is AEN bit.
Page 536 LCD CONTROLLER S3C2416X RISC MICROPROCESSOR 2.4.13 4BPP display (Palette) (BSWP = 0, HWSWP = 0) D[31:28] D[27:24] D[23:20] D[19:16] D[15:12] D[11:8] D[7:4] D[3:0] 000H 004H 008H (BSWP = 1, HWSWP = 0) D[31:28] D[27:24] D[23:20] D[19:16] D[15:12] D[11:8] D[7:4] D[3:0] 000H 004H 008H...
Page 537 S3C2416X RISC MICROPROCESSOR LCD CONTROLLER 2.4.14 2BPP display (Palette) (BSWP = 0, HWSWP = 0) [31:30] [29:28] [27:26] [25:24] [23:22] [21:20] [19:18] [17:16] 002H 006H 00AH … [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 000H 004H 008H 2.4.15 1BPP display (Palette) (BSWP = 0, HWSWP = 0) [31] [30]...
Page 538: Vd Signal Connection
LCD CONTROLLER S3C2416X RISC MICROPROCESSOR 2.5 VD SIGNAL CONNECTION 2.5.1 VD Pin Descriptions at 24BPP RGB parallel GREEN BLUE 2.5.2 VD Pin Descriptions at 18BPP RGB parallel GREEN BLUE 2.5.3 VD Pin Descriptions at 16BPP RGB parallel (5:6:5) GREEN BLUE 2.5.4 VD Pin Descriptions at 24BPP RGB Serial (8+8+8) [15:0] time...
Page 539 S3C2416X RISC MICROPROCESSOR LCD CONTROLLER 2.5.6 VD Pin Descriptions at 18BPP i80-System Interface GREEN BLUE 2.5.7 VD Pin Descriptions at 16BPP i80-System Interface GREEN BLUE 21-19...
Page 540: Palette Usage
LCD CONTROLLER S3C2416X RISC MICROPROCESSOR 2.6 PALETTE USAGE 2.6.1 Palette Configuration and Format Control The LCD controller can support the 256 colors palette for various selection of color mapping. The user can select 256 colors from the 24-bit colors through these four formats. 256 colors palette consist of the 256(depth) ×...
Page 541: Bpp (A:6:6:6) Palette Data Format
S3C2416X RISC MICROPROCESSOR LCD CONTROLLER Table 21-2. 19BPP (A:6:6:6) Palette Data Format INDEX\Bit Pos. … ..… … … … … … … … … … … … … … … … … … Number of Table 21-3. 16BPP(A:5:5:5) Palette Data Format INDEX\Bit Pos.
Page 542: Window Blending
LCD CONTROLLER S3C2416X RISC MICROPROCESSOR 3 WINDOW BLENDING 3.1 OVERVIEW The main function of the VPRCS module is window blending. LCD controller has 2-window layers and the detail is described below. As an example of application, System can use win0 as an OS window, full TV screen window or etc.
Page 543: Blending Diagram/Details
S3C2416X RISC MICROPROCESSOR LCD CONTROLLER 3.2 BLENDING DIAGRAM/DETAILS LCD controller could blend 2-Layer for the only one pixel at the same time. The Blending factor, alpha value is controlled by ALPHA0_R/G/B and ALPHA1_R/G/B fields in Window 1 Alpha Value register or DATA[27:24] in frame buffer, which are implemented for each window layer and color(R,G,B).
Page 544: Color Key Block Diagram
LCD CONTROLLER S3C2416X RISC MICROPROCESSOR COMPKEY Mask bit of COLVAL to compare with Window color DIRCON COLVAL Frame Buffer R’G’B’ Compare Window0 (Background) Selected Window Match with COLVAL : Window1 Unselected window (Foreground) Unmatched with CONVAL : Selected window Figure 21-6. Color Key Block Diagram Window0 (Green) Window0...
Page 545: Color Key Function Configurations
S3C2416X RISC MICROPROCESSOR LCD CONTROLLER OSD Image 180x100 Back-Ground 320x240 Blended (Alpha = 0x9) Blended (Alpha = 0xf) and No Color key and No Color key No Blend and Blended (Alpha = 0x0) Color Key Enable Blended (Alpha = 0x9) and Color Key Enable Figure 21-8.
Page 546: Vtime Controller Operation
LCD CONTROLLER S3C2416X RISC MICROPROCESSOR 4 VTIME CONTROLLER OPERATION 4.1 RGB INTERFACE The VTIME generates the control signals such as, RGB_VSYNC, RGB_HSYNC, RGB_VDEN and RGB_VCLK signal for RGB interface. These control signals are highly related with the configuration on the VIDTCON0/1/2 registers in the VSFR register.
Page 547: Virtual Display
S3C2416X RISC MICROPROCESSOR LCD CONTROLLER 5 VIRTUAL DISPLAY The LCD controller supports the hardware horizontal or vertical scrolling. If the screen is scrolled, the fields of LCDBASEU and LCDBASEL registers need to be changed (refer to Figure 21-9), but PAGEWIDTH and OFFSIZE value do not change.
Page 548: Rgb Interface I/O
LCD CONTROLLER S3C2416X RISC MICROPROCESSOR 6 RGB INTERFACE I/O 6.1.1 Signals Name Type Description RGB_HSYNC Output Horizontal Sync. Signal RGB_VSYNC Output Vertical Sync. Signal RGB_VCLK Output LCD Video Clock RGB_VDEN Output Data Enable RGB_VD[23:0] Output RGB data output 6.1.2 RGB I/F Timing 1 FRAME INT_FrSyn (internal)
Page 549: Lcd Cpu Interface I/O (I80-System I/F)
S3C2416X RISC MICROPROCESSOR LCD CONTROLLER 7 LCD CPU INTERFACE I/O (i80-SYSTEM I/F) 7.1.1 Signals Name Type Description SYS_VD[17:0] InOut Video Data SYS_CS0 Output Chip select for Main LCD SYS_CS1 Output Chip select for Sub LCD SYS_WR Output Write enable SYS_OE Output Output enable SYS_RS...
Page 550: Lcd Signal Muxing Table (Rgb And I-80 I/F)
LCD CONTROLLER S3C2416X RISC MICROPROCESSOR 7.1.3 LCD signal Muxing Table 21-6. LCD Signal Muxing Table (RGB and i-80 I/F) VIDOUT Signals 10/11 SYS_WR RGB_VCLK/SYS_WR Reserved RGB_VCLK 10/11 SYS_CS0 RGB_HSYNC/SYS_CS0 Reserved RGB_HSYNC 10/11 SYS_CS1 RGB_VSYNC/SYS_CS1 Reserved RGB_VSYNC 10/11 SYS_RS RGB_VDEN/SYS_RS Reserved RGB_VDEN 10/11 SYS_OE...
Page 551: Programmer's Model
S3C2416X RISC MICROPROCESSOR LCD CONTROLLER 8 PROGRAMMER’S MODEL 8.1 OVERVIEW The following registers are used to configure LCD controller 1. VIDCON0: Configure Video output format and display enable/disable. 2. VIDCON1: RGB I/F control signal. 3. SYSIFCONx: i80-System I/F control signal. 4.
Page 552 LCD CONTROLLER S3C2416X RISC MICROPROCESSOR Register Address Description Reset Value VIDW00ADD2B0 0x4C800094 Window 0’s buffer size register, buffer 0 0x0000_0000 VIDW00ADD2B1 0x4C800098 Window 0’s buffer size register, buffer 1 0x0000_0000 VIDW01ADD2 0x4C80009C Window 1’s buffer size register 0x0000_0000 VIDINTCON 0x4C8000AC Indicate the Video interrupt control register 0x03F0_0000 W1KEYCON0...
Page 553 S3C2416X RISC MICROPROCESSOR LCD CONTROLLER 8.1.2 Video Main Control 0 Register Register Address Description Reset Value VIDCON0 0x4C800000 Video control 1 register 0x0000_0000 VIDCON0 Description Initial State Reserved [31:24] Reserved 0x00 VIDOUT [23:22] It determines the output format of LCD Controller 00 = RGB I/F 01 = Reserved 10 = i80-System I/F for Main LDI...
Page 554 LCD CONTROLLER S3C2416X RISC MICROPROCESSOR 8.1.3 Video Main Control 0 Register (Continued) VIDCON0 Description Initial State CLKVALUP [12] Select CLKVAL_F Update timing control 0 = Always 1 = Start of a frame (Only once per frame) CLKVAL_F [11:6] Determine the rates of VCLK. VCLK = (HCLK or LCD video Clock) / [CLKVAL+1] ( CLKVAL ≥...
Page 555 S3C2416X RISC MICROPROCESSOR LCD CONTROLLER 8.1.4 Video Main Control 1 Register Register Address Description Reset Value VIDCON1 0x4C800004 Video control 2 register 0x0000_0000 VIDCON1 Description Initial state LINECNT [26:16] Provide the status of the line counter (read only) (read only) Up count from 0 to LINEVAL Reserved [15]...
Page 556 LCD CONTROLLER S3C2416X RISC MICROPROCESSOR 8.1.6 Video Time Control 1 Register Register Address Description Reset Value VIDTCON1 0x4C80000C Video time control 2 register 0x0000_0000 VIDTCON1 Description Initial state HBPD [23:16] Horizontal back porch is the number of VCLK periods between 0000000 the edge of HSYNC and the start of active data.
Page 557 S3C2416X RISC MICROPROCESSOR LCD CONTROLLER 8.1.8 Window 0 Control Register Register Address Description Reset Value WINCON0 0x4C800014 Window 0 control register 0x0000_0000 WINCON0 Description Initial State Status of Current display Buffer (Read only) 0 = buffer0 display 1 = buffer1 display BUFSTATUS [24] Note: RGB I/F does not support auto-change mode.
Page 558 LCD CONTROLLER S3C2416X RISC MICROPROCESSOR 8.1.9 Window 1 Control Register Register Address Description Reset Value WINCON1 0x4C800018 Window control 1 register 0x0000_0000 WINCON1 Description Initial State BITSWP [18] Bit swap control 0 = Swap Disable 1 = Swap Enable BYTSWP [17] Byte swaps control 0 = Swap Disable...
Page 559 S3C2416X RISC MICROPROCESSOR LCD CONTROLLER WINCON1 Description Initial State Per pixel blending case( BLD_PIX ==1) 0 = selected by AEN bit in frame buffer for each pixel or Key area AEN = 0 ALPHA0_R/G/B AEN = 1 ALPHA1_R/G/B KEYBLEND (W1KEYCON0[26]) Non-Key area ALPHA0_R/G/B Key area...
Page 560 LCD CONTROLLER S3C2416X RISC MICROPROCESSOR 8.1.12 Window 1 Position Control A Register Register Address Description Reset Value VIDOSD1A 0x4C800034 Video Window 1’s position control 2 register 0x0000_0000 VIDOSD1A Description initial state OSD_LeftTopX_F [21:11] Horizontal screen coordinate for left top pixel of OSD image OSD_LeftTopY_F [10:0] Vertical screen coordinate for left top pixel of OSD image...
Page 561 S3C2416X RISC MICROPROCESSOR LCD CONTROLLER 8.1.15 FRAME Buffer Address 0 Register Register Address Description Reset Value VIDW00ADD0B0 0x4C800064 0x0000_0000 Window 0’s buffer start address register, buffer 0 VIDW00ADD0B1 0x4C800068 0x0000_0000 Window 0’s buffer start address register, buffer 1 VIDW01ADD0 0x4C80006C 0x0000_0000 Window 1’s buffer start address register VIDWxxADD0...
Page 562 LCD CONTROLLER S3C2416X RISC MICROPROCESSOR 8.1.17 FRAME Buffer Address 2 Register(Virtual screen) Register Address Description Reset Value VIDW00ADD2B0 0x4C800094 Window 0’s buffer size register, buffer 0 0x0000_0000 VIDW00ADD2B1 0x4C800098 Window 0’s buffer size register, buffer 1 0x0000_0000 VIDW01ADD2 0x4C80009C Window 1’s buffer size register 0x0000_0000 VIDWxxADD2 Description...
Page 563 S3C2416X RISC MICROPROCESSOR LCD CONTROLLER 8.1.18 VIDEO Interrupt Control Register Register Address Description Reset Value VIDINTCON 0x4C8000AC Indicate the Video interrupt control register 0x3F00000 VIDINTCON Description Initial state FIFOINTERVAL [25:20] These bits control the interval of the FIFO interrupt. 0x3F SYSMAINCON [19] Sending complete interrupt enable bit to Main LCD...
Page 564 LCD CONTROLLER S3C2416X RISC MICROPROCESSOR 8.1.19 Win1 Color Key 0 Register Register Address Description Reset Value W1KEYCON0 0x4C8000B0 Color key control register 0x0000_0000 W1KEYCON0 Description Initial state KEYBLEN [26] Alpha value control for Key area or Non-Key area 0 = Alpha value selected by AEN bit in frame buffer 1 = Alpha value selected by below area Non-Key area : ALPHA0_R/G/B Key area...
Page 565 S3C2416X RISC MICROPROCESSOR LCD CONTROLLER 8.1.20 WIN 1 Color key 1 Register Register Address Description Reset Value W1KEYCON1 0x4C8000B4 Color key value ( transparent value) register 0x0000_0000 W1KEYCON1 Description Initial state COLVAL [23:0] Color key value for the transparent pixel effect NOTE: COLVAL and COMPKEY use 24-bit color data at all bpp mode.
Page 566 LCD CONTROLLER S3C2416X RISC MICROPROCESSOR 8.1.21 WIN0 Color MAP Register Address Description Reset Value WIN0MAP 0x4C8000D0 Window color control 0x0000_0000 WIN0MAP Description Initial state MAPCOLEN_F [24] Window’s color mapping control bit. If this bit is enabled then Video DMA will stop, and MAPCOLOR will be appear on back-ground image instead of original image.
Page 567 S3C2416X RISC MICROPROCESSOR LCD CONTROLLER 8.1.23 Window Palette control Register Register Address Description Reset Value WPALCON 0x4C8000E4 Window Palette control register 0x0000_0000 WPALCON Description Initial state PALUPDATEEN Palette memory access-right control bit. Users should set this bit before access (write or read) palette memory, in this case LCD controller cannot access palette.
Page 568 LCD CONTROLLER S3C2416X RISC MICROPROCESSOR 8.1.24 Main LCD i80-System Interface control Register Address Description Reset Value SYSIFCON0 0x4C800130 i80-System Interface control for Main LDI(LCD) 0x0000_0000 SYSIFCON1 0x4C800134 i80-System Interface control for Sub LDI(LCD) 0x0000_0000 SYSIFCONx Description Initial State Reserved [23:20] Reserved LCD_CS_SETUP [19:16]...
Page 569 S3C2416X RISC MICROPROCESSOR LCD CONTROLLER 8.1.25 Dithering Control 1 Register Register Address Description Reset Value DITHMODE 0x4C800138 Dithering mode register 0x0000_0000 DITHMODE Description Initial state Reserved [30:7] Not used for normal access (Write not-zero values to these register make to come out abnormal result ) RDithPos [6:5] Red Dither bit control...
Page 570 LCD CONTROLLER S3C2416X RISC MICROPROCESSOR 8.1.26 i80-System Interface Command Control 0 Register Address Description Reset Value SIFCCON0 0x4C80013C i80-System Interface Command Control 0x0000_0000 SIFCCON0 Description Initial State Reserved [11:10] Reserved SYS_CS0_CON LCD i80-System Interface SYS_CS0 (main) Signal control 0 = Disable (High) 1 = Enable (Low) SYS_CS1_CON LCD i80-System Interface SYS_CS1 (sub) Signal control...
Page 571 S3C2416X RISC MICROPROCESSOR LCD CONTROLLER 8.1.27 i80-System Interface Command Control 1 Register Address Description Reset Value SIFCCON1 0x4C800140 i80-System Interface Command Data Write register 0x0000_0000 SIFCCON1 Description Initial State Reserved [23:18] Reserved SYS_WDATA [17:0] LCD i80-System Interface Write Data 8.1.28 i80-System Interface Command Control 2 Register Address Description...
Page 572 LCD CONTROLLER S3C2416X RISC MICROPROCESSOR 8.1.29 i80-System I/F TRIGGER CONTROL 2 Register Register Address Description Reset Value CPUTRIGCON2 0x4C800160 Software-Based Trigger control register 0x0000_0000 CPUTRIGCON2 Description Initial State SWTRIG Software-Based Transmission Trigger When this bit is set, trigger happens. This bit is automatically cleared.
Page 573: Adc & Touch Screen Interface
S3C2416X RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE ADC & TOUCH SCREEN INTERFACE 1 OVERVIEW The 12-bit CMOS ADC (Analog to Digital Converter) is a recycling type device with 10-channel analog inputs. It converts the analog input signal into 12-bit binary digital codes at a maximum conversion rate of 1MSPS with 5MHz A/D converter clock.
Page 574: Adc & Touch Screen Interface Operation
ADC AND TOUCH SCREEN INTERFACE S3C2416X RISC MICROPROCESSOR 2 ADC & TOUCH SCREEN INTERFACE OPERATION 2.1 BLOCK DIAGRAM Figure 22-1 shows the functional block diagram of A/D converter and touch screen interface. Note that the A/D converter device is a recycling type. VDDA_ADC PULL_UP XM_SEN...
Page 575: Function Descriptions
S3C2416X RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE 2.2 FUNCTION DESCRIPTIONS 2.2.1 A/D Conversion Time When the PCLK frequency is 50 MHz, the prescaler value is 49 and total 10-bit and 12-bit conversion time is given: A/D converter freq. = 50 MHz/(49+1) = 1 MHz Conversion time = 1/(1MHz / (5cycles)) = 1/200 KHz = 5 us NOTE This A/D converter is designed to operate at maximum 5 MHz clock, so the conversion rate can go up to...
Page 576: Timing Diagram In Auto (Sequential) X/Y Position Conversion Mode
ADC AND TOUCH SCREEN INTERFACE S3C2416X RISC MICROPROCESSOR 4. Waiting for interrupt mode (ADCTSC = 0xd3) Touch screen controller generates interrupt (INT_TC) signal when the stylus is down. The value of ADC touch screen control register (ADCTSC) is ‘0xd3’; PULL_UP is ‘0’, XP_SEN is ‘1’, XM_SEN is ‘0’, YP_SEN is ‘1’ and YM_SEN is ‘1’.
Page 577: Adc And Touch Screen Interface Special Registers
S3C2416X RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE 3 ADC AND TOUCH SCREEN INTERFACE SPECIAL REGISTERS 3.1 ADC CONTROL (ADCCON) REGISTER Register Address Description Reset Value ADCCON 0x58000000 ADC control register 0x3FC4 ADCCON Description Initial State ECFLG [15] End of conversion flag (read only). 0 = A/D conversion in process 1 = End of A/D conversion PRSCEN...
Page 578: Adc Touch Screen Control (Adctsc) Register
ADC AND TOUCH SCREEN INTERFACE S3C2416X RISC MICROPROCESSOR 3.2 ADC TOUCH SCREEN CONTROL (ADCTSC) REGISTER Register Address Description Reset Value ADCTSC 0x58000004 ADC touch screen control register 0x058 ADCTSC Description Initial State UD_SEN Select interrupt source Stylus Up or Down 0 = Detect Stylus Down Signal.
Page 579: Adc Start Delay (Adcdly) Register
S3C2416X RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE 3.3 ADC START DELAY (ADCDLY) REGISTER Register Address Description Reset Value ADCDLY 0x58000008 ADC start or interval delay register 0x00ff ADCDLY Description Initial State DELAY [15:0] Incase of ADC conversion mode (Normal, Separate, Auto 0x00ff conversion);...
Page 580: Adc Conversion Data (Adcdat0) Register
ADC AND TOUCH SCREEN INTERFACE S3C2416X RISC MICROPROCESSOR 3.4 ADC CONVERSION DATA (ADCDAT0) REGISTER Register Address Description Reset Value ADCDAT0 0x5800000C ADC conversion data register ADCDAT0 Description Initial State UPDOWN [15] Up or down state of Stylus at Waiting for Interrupt Mode. 0 = Stylus down state 1 = Stylus up state AUTO_PST...
Page 581: Adc Conversion Data (Adcdat1) Register
S3C2416X RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE 3.5 ADC CONVERSION DATA (ADCDAT1) REGISTER Register Address Description Reset Value ADCDAT1 0x58000010 ADC conversion data register ADCDAT1 Description Initial State UPDOWN [15] Up or down state of Stylus at Waiting for Interrupt Mode. 0 = Stylus down state 1 = Stylus up state AUTO_PST...
Page 582: Adc Channel Mux Register (Adcmux)
ADC AND TOUCH SCREEN INTERFACE S3C2416X RISC MICROPROCESSOR 3.7 ADC CHANNEL MUX REGISTER (ADCMUX) Register Address Description Reset Value ADCMUX 0x5800018 Analog input channel select ADCMUX Description Initial State ADCMUX [3:0] Analog input channel select. 0000 = AIN 0 0001 = AIN 1 0010 = AIN 2 0011 = AIN 3 0100 = AIN 4...
Page 583: Iis Multi Audio Interface
S3C2416X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE IIS MULTI AUDIO INTERFACE 1 OVERVIEW IIS (Inter-IC Sound) is one of the popular digital audio interface. The bus has only to handle audio data, while the other signals, such as sub-coding and control, are transferred separately. Surely, it is possible to transmit data between two IIS bus.
Page 584: Block Diagram
S3C2416X RISC MICROPROCESSOR S3C2416X RISC MICROPROCESSOR 4 BLOCK DIAGRAM Figure 23-1. IIS-Bus Block Diagram 5 FUNCTIONAL DESCRIPTIONS IIS interface consists of register bank, FIFOs, shift registers, clock control, DMA finite state machine, and channel control block as shown in Figure 23-1. Note that each FIFO has 32-bit width and 16 depth structure, which contains left/right channel data.
Page 585: Master/Slave Mode
S3C2416X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE 5.1 MASTER/SLAVE MODE Master or slave mode can be chosen by setting IMS bit of IISMOD register. In master mode, I2SSCLK and I2SLRCLK are generated internally and supplied to external device. Therefore a root clock is needed for generating I2SSCLK and I2SLRCLK by dividing.
Page 586: Dma Transfer
S3C2416X RISC MICROPROCESSOR S3C2416X RISC MICROPROCESSOR 5.2 DMA TRANSFER In the DMA transfer mode, the transmitter or receiver FIFO are accessible by DMA controller. DMA service request is activated internally by the transmitter or receiver FIFO state. The FTXEMPT, FRXEMPT, FTXFULL, and FRXFULL bits of I2SCON register represent the transmitter or receiver FIFO data state.
Page 587: Audio Serial Data Format
S3C2416X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE 6 AUDIO SERIAL DATA FORMAT 6.1 IIS-BUS FORMAT The IIS bus has four lines including serial data input I2SSDI, serial data output I2SSDO, left/right channel select clock I2SLRCLK, and serial bit clock I2SSCLK; the device generating I2SLRCLK and I2SSCLK is the master. Serial data is transmitted in 2's complement with the MSB first with a fixed position, whereas the position of the LSB depends on the word length.
Page 588: Iis Audio Serial Data Formats
S3C2416X RISC MICROPROCESSOR S3C2416X RISC MICROPROCESSOR Figure 23-3 shows the audio serial format of IIS, MSB-justified, and LSB-justified. Note that in this figure, the word length is 16 bit and I2SLRCLK makes transition every 24 cycle of I2SSCLK (BFS is 48 fs, where fs is sampling frequency;...
Page 589: Sampling Frequency And Master Clock
S3C2416X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE 6.4 SAMPLING FREQUENCY AND MASTER CLOCK Master clock frequency (RCLK) can be selected by sampling frequency as shown in Table 23-1. Because RCLK is made by IIS pre-scaler, the pre-scaler value and RCLK type (256fs or 384fs or 512fs or 768fs) should be determined properly.
Page 590: Programming Guide
I2SLRCLK, I2SSCLK and I2SCDCLK is inout-type. The each of I2SSDI and I2SSDO is input and output. 2. Now then, you choose clock source. S3C2416 has four clock sources. Those are PCLK, divided EPLL clock EPLLRefCLK and external codec. If you want to know more detail, refer Figure 23-2.
Page 591: Example Code
S3C2416X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE 7.4 EXAMPLE CODE TX CHANNEL The I2S TX channel provides single/double/tripple stereo compliant outputs. The transmit channel can operate in master or Slave mode. Data is transferred between the processor and the I2S controller via an APB access or a DMA access.
Page 592 S3C2416X RISC MICROPROCESSOR S3C2416X RISC MICROPROCESSOR The Data is aligned in the TX FIFO for 8-bits/channel or 16-bits/channel BLC as shown BLC=00 BLC=00 BLC=01 BLC=01 RIGHT CHANNEL LEFT CHANNEL LOC 0 LOC 1 LOC 2 LOC 3 LOC 4 LOC 5 LOC 6 LOC 7 LOC 8...
Page 593: Tx Fif0 Structure For Blc = 10 (24-Bits/Channel)
S3C2416X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE The Data is aligned in the TX FIFO for 24-bits/channel BLC as shown BLC = 10 (24-bits/channel) LOC 0 INVALID LEFT CHANNEL LOC 1 INVALID RIGHT CHANNEL LOC 2 INVALID LEFT CHANNEL LOC 3 INVALID RIGHT CHANNEL LOC 4...
Page 594 S3C2416X RISC MICROPROCESSOR S3C2416X RISC MICROPROCESSOR RX CHANNEL The I2S RX channel provides a single stereo compliant output. The receive channel can operate in master or slave mode. Data is received from the input line and transferred into the RX FIFO. The processor can then read this data via an APB read or a DMA access can access this data.
Page 595 S3C2416X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE The Data is aligned in the RX FIFO for 8-bits/channel or 16-bits/channel BLC as shown BLC=00 BLC=00 BLC=01 BLC=01 RIGHT CHANNEL LEFT CHANNEL LOC 0 LOC 1 LOC 2 LOC 3 LOC 4 LOC 5 LOC 6 LOC 7...
Page 596: Rx Fif0 Structure For Blc = 10 (24-Bits/Channel)
S3C2416X RISC MICROPROCESSOR S3C2416X RISC MICROPROCESSOR The Data is aligned in the RX FIFO for 24-bits/channel BLC as shown BLC = 10 (24-bits/channel) LOC 0 INVALID LEFT CHANNEL LOC 1 INVALID RIGHT CHANNEL LOC 2 INVALID LEFT CHANNEL LOC 3 INVALID RIGHT CHANNEL LOC 4...
Page 597: Iis-Bus Interface Special Registers
S3C2416X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE 8 IIS-BUS INTERFACE SPECIAL REGISTERS Table 23-3. Register Summary of IIS Interface Register Address Description Reset Value IISCON 0x55000000 IIS interface control register 0xC600 IISMOD 0x55000004 IIS interface mode register IISFIC 0x55000008 IIS interface FIFO control register IISPSR 0x5500000C IIS interface clock divider control register...
Page 598: Iis Control Register (Iiscon)
S3C2416X RISC MICROPROCESSOR S3C2416X RISC MICROPROCESSOR 8.1 IIS CONTROL REGISTER (IISCON) Register Address Description Reset Value IISCON 0x55000000 IIS interface control register 0x0000_C600 IISCON Description Reserved. Program to zero. Reserved [31:18] FTXURSTATUS [17] TX FIFO under-run interrupt status. And this is used by interrupt clear bit.
Page 599 S3C2416X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE IISCON Description FRXFULL Rx FIFO full status indication. 0 = FIFO is not full (ready for receive data from channel) 1 = FIFO is full (not ready for receive data from channel) TXDMAPAUSE Tx DMA operation pause command.
Page 600: Iis Mode Register (Iismod)
S3C2416X RISC MICROPROCESSOR S3C2416X RISC MICROPROCESSOR 8.2 IIS MODE REGISTER (IISMOD) Register Address Description Reset Value IISMOD 0x55000004 IIS interface mode register 0x0000_0000 IISMOD Description Reserved [31:15] Reserved. Program to zero. CDD2 [21:20] Channel-2 Data Discard. Discard means zero padding. It only supports 8/16 bit mode.
Page 601 S3C2416X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE IISMOD Description [9:8] Transmit or receive mode select. 00 = Transmit only mode 01 = Receive only mode 10 = Transmit and receive simultaneous mode 11 = Reserved Left/Right channel clock polarity select. 0 = Low for left channel and high for right channel 1 = High for left channel and low for right channel [6:5]...
Page 602: Iis Fifo Control Register (Iisfic)
S3C2416X RISC MICROPROCESSOR S3C2416X RISC MICROPROCESSOR 8.3 IIS FIFO CONTROL REGISTER (IISFIC) Register Address Description Reset Value IISFIC 0x55000008 IIS interface FIFO control register 0x0000_0000 IISFIC Description [31:29] Reserved. Program to zero. FTX2CNT [28:24] TX FIFO2 data count. (0 ~ 16) [23:21] Reserved.
Page 603: Iis Transmit Register (Iistxd)
S3C2416X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE 8.5 IIS TRANSMIT REGISTER (IISTXD) Register Address Description Reset Value IISTXD 0x55000010 IIS interface transmit data register 0x0000_0000 IISTXD Description IISTXD [31:0] TX FIFO write data. Note that the left/right channel data is allocated as the following bit fields.
Page 604 S3C2416X RISC MICROPROCESSOR S3C2416X RISC MICROPROCESSOR NOTES 23-22...
Page 605: Ac97 Controller
AC97 CONTROLLER 1 OVERVIEW The AC97 Controller Unit of the S3C2416 supports the AC97 revision 2.0 features. AC97 Controller communicates with AC97 Codec using audio controller link (AC-link). Controller sends the stereo PCM data to Codec. The external digital-to-analog converter (DAC) in the Codec then converts the audio sample to an analog audio waveform.
Page 606: Ac97 Controller Operation
Power-down sequence and Wake-up sequence. 2.1 BLOCK DIAGRAM Figure 24-1 shows the functional block diagram of S3C2416 AC97 Controller. The AC97 signals form the AC-link, which is a point-to-point synchronous serial inter-connecting that supports full-duplex data transfers. All digital audio streams and command/status information are communicated over the AC-link.
Page 607: Internal Data Path
2.2 INTERNAL DATA PATH Figure 24-2 shows the internal data path of S3C2416 AC97 Controller. It has stereo Pulse Code Modulated (PCM) In, Stereo PCM Out and mono Mic-in buffers, which consist of 16-bit, 16 entries buffer. It also has 20-bit I/O shift register via AC-link.
Page 608: Operation Flow Chart
AC97 CONTROLLER S3C2416X RISC MICROPROCESSOR 3 OPERATION FLOW CHART When you initialize the AC97 controller, you must assert system reset or cold reset. Because we don’t know the previous state of the external the AC97 audio-codec. This assumes that GPIO is already ready. Then you make codec ready interrupt enable.
Page 609: Ac-Link Digital Interface Protocol
4 AC-LINK DIGITAL INTERFACE PROTOCOL Each AC97 Codec incorporates a five-pin digital serial interface that links it to the S3C2416 AC97 Controller. AC- link is a full-duplex, fixed-clock, PCM digital stream. It employs a time division multiplexed (TDM) scheme to handle control register accesses and multiple input and output audio streams.
Page 610: Ac-Link Output Frame (Sdata_Out)
AC97 CONTROLLER S3C2416X RISC MICROPROCESSOR 4.1 AC-LINK OUTPUT FRAME (SDATA_OUT) Slot 0: Tag Phase In slot 0, the first bit is a bit (SDATA_OUT, bit 15) which represents the validity of the entire frame. If bit 15 is a 1, the current frame contains at least a valid time slot.
Page 611: Ac-Link Input Frame (Sdata_In)
S3C2416X RISC MICROPROCESSOR AC97 CONTROLLER 4.2 AC-LINK INPUT FRAME (SDATA_IN) Slot 0: Tag Phase In slot 0, the first bit is a bit (SDATA_OUT, bit 15) that indicates whether the AC97 controller is in the CODEC ready state. If the CODEC Ready bit is a 0, the AC97 controller is not ready for normal operation. This condition is normal after the power is de-asserted on reset and the AC97 controller voltage references are settling.
Page 612: Ac-Link Input Frame
AC97 CONTROLLER S3C2416X RISC MICROPROCESSOR Slot 4: PCM Right channel audio Slot 4 which is audio input frame is the right channel audio output of the AC97 Codec. If a sample has a resolution that is less than 16 bits, the AC97 Codec fills all training non-valid bit positions in the slot with zeroes. Slot 6: Microphone Record Data The AC97 Controller only supports 16-bit resolution for the MIC-in channel.
Page 613: Ac97 Power-Down
S3C2416X RISC MICROPROCESSOR AC97 CONTROLLER 5 AC97 POWER-DOWN For details, please refer the AC-Link Power Managerment part of AC97 revision 2.0 specification. SYNC BIT_CLK slot 12 Write to Data SDATA_OUT prev.frame 0X26 slot 12 SDATA_IN prev.frame Figure 24-7. AC97 Power-down Timing 5.1.1 Powering Down the AC-link The AC-link signals enter a low power mode when the AC97 Codec Power-down register (0x26) bit PR4 is set to a 1 (by writing 0x1000).
Page 614: Codec Reset
AC97 CONTROLLER S3C2416X RISC MICROPROCESSOR 6 CODEC RESET For details, please refer the CODEC Reset part of AC97 revision 2.0 specification. 6.1.1 Cold AC97 Reset A cold reset is generated when the nRESET pin is asserted through the AC_GLBCTRL. Asserting and deasserting nRESET activates BITCLK and SDATA_OUT.
Page 615: Ac97 Controller State Diagram
S3C2416X RISC MICROPROCESSOR AC97 CONTROLLER 7 AC97 CONTROLLER STATE DIAGRAM WARM IDLE ACTIVE INIT READY : PCLK rising : ACLINK_ON : CODEC_READY & TRANS_DATA & NORMAL_SYNC : ~CODEC_READY | ~TRANS_DATA : !ACLINK_ON : POWER_DOWN : WARM_RESET : CODEC_WAKEUP : COLD_RESET | ~PRESETn Figure 24-9.
Page 616: Ac97 Controller Special Registers
AC97 CONTROLLER S3C2416X RISC MICROPROCESSOR 8 AC97 CONTROLLER SPECIAL REGISTERS 8.1 AC97 SPECIAL FUNCION REGISTER SUMMARY Register Address Description Reset Value AC_GLBCTRL 0x5B000000 AC97 Global Control Register 0x00000000 AC_GLBSTAT 0x5B000004 AC97 Global Status Register 0x00000001 AC_CODEC_CMD 0x5B000008 AC97 Codec Command Register 0x00000000 AC_CODEC_STAT 0x5B00000C...
Page 617: Ac97 Global Control Register (Ac_Glbctrl)
S3C2416X RISC MICROPROCESSOR AC97 CONTROLLER 8.2 AC97 GLOBAL CONTROL REGISTER (AC_GLBCTRL) This is the global register of the AC97 controller. There are interrupt control registers, DMA control registers, AC- Link control register, data transmission control register and related reset control register. Register Address Description...
Page 618: Ac97 Global Status Register (Ac_Glbstat)
AC97 CONTROLLER S3C2416X RISC MICROPROCESSOR 8.3 AC97 GLOBAL STATUS REGISTER (AC_GLBSTAT) This is the status register. When the interrupt is occurred, you can check what the interrupt source is. Register Address Description Reset Value AC_GLBSTAT 0x5B000004 AC97 Global Status Register 0x00000001 AC_GLBSTAT Description...
Page 619: Ac97 Codec Status Register (Ac_Codec_Stat)
S3C2416X RISC MICROPROCESSOR AC97 CONTROLLER 8.5 AC97 CODEC STATUS REGISTER (AC_CODEC_STAT) If the Read enable bit is 1 and Codec command address is valid, Codec status data is also valid. Register Address Description Reset Value AC_CODEC_STAT 0x5B00000C AC97 Codec Status Register 0x00000000 AC_CODEC_STAT Description...
Page 620: Ac97 Mic In Channel Fifo Address Register (Ac_Micaddr)
AC97 CONTROLLER S3C2416X RISC MICROPROCESSOR 8.7 AC97 MIC IN CHANNEL FIFO ADDRESS REGISTER (AC_MICADDR) To index the internal MIC-in FIFO address. Register Address Description Reset Value AC_MICADDR 0x5B000014 AC97 MIC In Channel FIFO Address Register 0x00000000 AC_MICADDR Description Initial State [31:20] Reserved.
Page 621: Chapter 25 Pcm Audio Interface
S3C2416X RISC MICROPROCESSOR PCM AUDIO INTERFACE PCM AUDIO INTERFACE 1 OVERVIEW The S3C2416 has one port of PCM Audio Interface. The PCM Audio Interface module provides PCM bi- directional serial interface to an external Codec. 1.1 FEATURE • Mono, 16bit PCM, 1 port audio interface.
Page 622 PCM AUDIO INTERFACE S3C2416X RISC MICROPROCESSOR 2 PCM AUDIO INTERFACE The PCM Audio Interface provides a serial interface to an external Codec. The PCM module receives an input PCMSOURCE_CLK that is used to generate the serial shift timing. The PCM interface outputs a serial data out, a serial shift clock, and a sync signal.
Page 623: Pcm Timing
S3C2416X RISC MICROPROCESSOR PCM AUDIO INTERFACE 3 PCM TIMING The following figures show the timing relationship for the PCM transfers. Figure 25-1 shows a PCM transfer with the MSB configured to be coincident with the PCMFSYNC. This MSB positioning corresponds to setting the TX_MSB_POS and RX_MSB_POS bits in PCMCTL register to be 0. input PCMSOURCE_CLK output...
Page 624: Pcm Input Clock Diagram
1/(SYNC_DIV+1) (1/16~1/512) PCM_CDCLK CTL_SERCLK_SEL Figure 25-3. Input Clock Diagram for PCM S3C2416 PCM is able to select clock either PCLK or External Clock. Refer figure 25-3. To enable clock gating, please refer to the SYSCON part(SCLKCON, PCLKCON). 25-4...
Page 625: Pcm Registers
S3C2416X RISC MICROPROCESSOR PCM AUDIO INTERFACE 3.2 PCM REGISTERS There are 8 control registers. The details of those registers are as follows. 3.3 PCM REGISTER SUMMARY Register Address Description Reset Value PCM_CTL 0x5C000000 PCM Main Control 0x00000000 PCM_CLKCTL 0x5C000004 PCM Clock and Shift control 0x00000000 PCM_TXFIFO 0x5C000008...
Page 626: Pcm Control Register
PCM AUDIO INTERFACE S3C2416X RISC MICROPROCESSOR 3.4 PCM CONTROL REGISTER The PCM_CTL register is used to control the various aspects of the PCM module. It also provides a status bit to provide the option to using polling instead of interrupt based control. Register Address Description...
Page 627 S3C2416X RISC MICROPROCESSOR PCM AUDIO INTERFACE PCM_CTL Description Initial State TX_MSB_POS Controls the position of the MSB bit in the serial output stream relative to the PCMFSYNC signal 0 = MSB sent during the same clock that PCMFSYNC is high 1 = MSB sent on the next PCMSCLK cycle after PCMFSYNC is high RX_MSB_POS...
Page 628: Pcm Clk Control Register
PCM AUDIO INTERFACE S3C2416X RISC MICROPROCESSOR 3.5 PCM CLK CONTROL REGISTER Register Address Description Reset Value PCM_CLKCTL 0x5C000004 Control the PCM Audio Inteface 0x00000000 The bit definitions for the PCM_CTL Control Register are shown below: PCM_CLKCTL Description Initial State Reserved [31:20] Reserved CTL_SERCLK_EN...
Page 629: The Pcm Tx Fifo Register
S3C2416X RISC MICROPROCESSOR PCM AUDIO INTERFACE 3.6 THE PCM TX FIFO REGISTER Register Address Description Reset Value PCM_TXFIFO 0x5C000008 PCM interface Transmit FIFO data register 0x00010000 The bit definitions for the PCM_TXFIFO Register are shown below: PCM_TXFIFO Description Initial State Reserved [31:17] Reserved...
Page 630: Pcm Rx Fifo Register
PCM AUDIO INTERFACE S3C2416X RISC MICROPROCESSOR 3.7 PCM RX FIFO REGISTER Register Address Description Reset Value PCM_RXFIFO 0x5C00000C PCM interface Receive FIFO data register 0x00010000 The bit definitions for the PCM_RXFIFO Register are shown below: PCM_RXFIFO Description Initial State Reserved [31:17] Reserved RXFIFO_DVALID...
Page 631: Pcm Interrupt Control Register
S3C2416X RISC MICROPROCESSOR PCM AUDIO INTERFACE 3.8 PCM INTERRUPT CONTROL REGISTER The PCM_IRQ_CTL register is used to control the various aspects of the PCM interrupts. Register Address Description Reset Value PCM_IRQ_CTL 0x5C000010 Control the PCM Interrupts 0x00000000 The bit definitions for the PCM_IRQ_CTL Control Register are shown below: PCM_IRQ_CTL Description Initial State...
Page 632 PCM AUDIO INTERFACE S3C2416X RISC MICROPROCESSOR PCM_IRQ_CTL Description Initial State TXFIFO_ERROR_ Interrupt is generated for TxFIFO starve ERROR. STARVE This occurs whenever the TxFIFO is read when it is still empty. This is considered an ERROR and will have unexpected results 1: IRQ source enabled 0: IRQ source disabled TXFIFO_ERROR_...
Page 633 S3C2416X RISC MICROPROCESSOR PCM AUDIO INTERFACE PCM_IRQ_CTL Description Initial State RXFIFO_ERROR_ Interrupt is generated for RxFIFO overflow ERROR. OVERFLOW This occurs whenever the RxFIFO is written when it is already full. This is considered an ERROR and will have unexpected results 1: IRQ source enabled 0: IRQ source disabled...
Page 634: Pcm Interrupt Status Register
PCM AUDIO INTERFACE S3C2416X RISC MICROPROCESSOR 3.9 PCM INTERRUPT STATUS REGISTER The PCM_IRQ_STAT register is used to report IRQ status. Register Address Description Reset Value PCM_IRQ_STAT 0x5C000014 PCM Interrupt Status 0x00000000 The bit definitions for the PCM_IRQ_STATUS Register are described below: PCM_IRQ_STAT Description Initial State...
Page 635 S3C2416X RISC MICROPROCESSOR PCM AUDIO INTERFACE PCM_IRQ_STAT Description Initial State RXFIFO_EMPTY Interrupt is generated whenever the RX FIFO is empty 1 = IRQ is occurred. 0 = IRQ is not occurred. RXFIFO_ALMOST Interrupt is generated whenever the RX FIFO is ALMOST _EMPTY empty.
Page 636: Pcm Fifo Status Register
PCM AUDIO INTERFACE S3C2416X RISC MICROPROCESSOR 3.10 PCM FIFO STATUS REGISTER The PCM_FIFO_STAT register is used to report FIFO status. Register Address Description Reset Value PCM_FIFO_STAT 0x5C000018 PCM FIFO Status 0x00000000 The bit definitions for the PCM_FIFO_STATUS Register are shown below: PCM_FIFO_STAT Description Initial State...
Page 637: Pcm Interrupt Clear Register
S3C2416X RISC MICROPROCESSOR PCM AUDIO INTERFACE 3.11 PCM INTERRUPT CLEAR REGISTER The PCM_CLRINT register is used to clear the interrupt. Interrupt service routine is responsible for clearing interrupt asserted. Writing any values on this register clears interrupts for ARM. Reading this register is not allowed.
Page 638 PCM AUDIO INTERFACE S3C2416X RISC MICROPROCESSOR NOTES 25-18...
Page 639: Electrical Data
S3C2416X RISC MICROPROCESSOR ELECTRICAL DATA ELECTRICAL DATA 1 ABSOLUTE MAXIMUM RATINGS Table 26-1. Absolute Maximum Rating Parameter Symbol Unit VDDi, VDDiarm, VDDalive, VDDA_MPLL, VDDA_EPLL, -0.5 VDDI_UDEV VDD_OP1, VDD_OP2, VDD_OP3, DC Supply Voltage VDD_RTC, VDD_SRAM, VDD_SD, -0.5 VDDA_ADC, VDDA33x, VDD_USBOSC VDD_SDRAM -0.5 DC Input Voltage -0.5...
Page 640: Recommended Operating Conditions
ELECTRICAL DATA S3C2416X RISC MICROPROCESSOR 2 RECOMMENDED OPERATING CONDITIONS Table 26-2. Recommended Operating Conditions (400MHz) Parameter Symbol Unit DC Supply Voltage for Alive Block VDDalive 1.15 1.25 DC Supply Voltage for Core Block ARMCLK / HCLK VDDiarm 400/133 VDDi 1.25 1.35 VDDA_MPLL VDDA_EPLL...
Page 641 S3C2416X RISC MICROPROCESSOR ELECTRICAL DATA Table 26-3. Recommended Operating Conditions (266MHz) Parameter Symbol Unit DC Supply Voltage for Alive Block VDDalive 1.15 1.25 DC Supply Voltage for Core Block ARMCLK / HCLK VDDiarm 1.25 1.35 266/133 VDDi VDDA_MPLL 1.25 1.35 VDDA_EPLL VDD_OP1 DC Supply Voltage for I/O Block1...
Page 642: C. Electrical Characteristics
ELECTRICAL DATA S3C2416X RISC MICROPROCESSOR 3 D.C. ELECTRICAL CHARACTERISTICS Table 26-4. Normal I/O PAD DC Electrical Characteristics = 1.7V~3.60V, Vext = 3.0~5.5V , T = -40 to 85°C Parameter Condition Unit VDD Power Off VDD=3.3V Tolerant external Vtol voltage** VDD Power On VDD=2.5V VDD=1.8V High Level Input Voltage...
Page 643: Special Memory Ddr I/O Pad Dc Electrical Characteristics
S3C2416X RISC MICROPROCESSOR ELECTRICAL DATA Table 26-5. Special Memory DDR I/O PAD DC Electrical Characteristics =1.7V~2.7V, Vext = 3.0~3.6V , T = -40 to 85°C Parameter Condition Unit VDD Power Off Tolerant external Vtol VDD=2.5V VDD Power voltage** VDD=1.8V High Level Input Voltage LVCMOS Interface 0.7VDD VDD+0.3...
Page 644: Usb Dc Electrical Characteristics
ELECTRICAL DATA S3C2416X RISC MICROPROCESSOR Table 26-6. USB DC Electrical Characteristics = 3.0 to 3.6V; GND = 0V; Cload = 2uF; unless otherwise specified. Symbol Parameter Conditions Unit Supply voltage Differential input sensitivity Differential common mode voltage Low level input voltage High level input voltage Low level output voltage RL = 1.5KΩ...
Page 645: C. Electrical Characteristics
S3C2416X RISC MICROPROCESSOR ELECTRICAL DATA 4 A.C. ELECTRICAL CHARACTERISTICS XTALCYC 1/2 VDD_OP1 1/2 VDD_OP1 The clock input from the X pin. NOTE: TIpll Figure 26-1. XTIpll Clock Timing EXTCYC EXTHIGH EXTLOW 1/2 VDD_OP1 1/2 VDD_OP1 NOTE: The clock input from the EXTCLK pin. Figure 26-2.
Page 646: Hclk/Clkout/Sclk In Case That Extclk Is Used
ELECTRICAL DATA S3C2416X RISC MICROPROCESSOR HCLK (internal) HC2CK CLKOUT (HCLK) HC2SCLK SCLK Figure 26-4. HCLK/CLKOUT/SCLK in case that EXTCLK is used Figure 26-5. Manual Reset Input Timing 26-8...
Page 647: Power-On Oscillation Setting Timing
S3C2416X RISC MICROPROCESSOR ELECTRICAL DATA Power PLL can operate after OM[3:2] is latched. nRESET XTIpll or EXTCLK PLL is configured by S/W first time. tPLL Clock Disable VCO is adapted to new clock frequency. output tRST2RUN FCLK MCU operates by XTIpll FCLK is new frequency.
Page 648: Sleep Mode Return Oscillation Setting Timing
ELECTRICAL DATA S3C2416X RISC MICROPROCESSOR EXTCLK XTIpll Wake up from sleep mode Clock Disable tOSC2 Output Several slow clocks (XTIpll or EXTCLK) FCLK Sleep mode is initiated. Figure 26-7. Sleep Mode Return Oscillation Setting Timing 26-10...
Page 649: Smc Synchronous Read Timing
S3C2416X RISC MICROPROCESSOR ELECTRICAL DATA Figure 26-8. SMC Synchronous Read Timing Figure 26-9. SMC Asynchronous Read Timing 26-11...
Page 650: Smc Asynchronous Write Timing
ELECTRICAL DATA S3C2416X RISC MICROPROCESSOR Asynchronous Write SMCLK tADDRD_A RADDR tDOD_A RDATA D(A) tCSD_A nRCS tWED nRWE Figure 26-10. SMC Asynchronous Write Timing Figure 26-11. SMC Synchronous Write Timing 26-12...
Page 651: Smc Wait Timing
S3C2416X RISC MICROPROCESSOR ELECTRICAL DATA S M C LK R A D D R [26 :0] R D A T A D (A ) [31 :0] nR C S nR O E nW A IT tH S tW S Figure 26-12. SMC Wait Timing 26-13...
Page 652: Nand Flash Timing
ELECTRICAL DATA S3C2416X RISC MICROPROCESSOR TACLS TWRPH0 TWRPH1 HCLK tCLED tCLED FCLE tWED tWED nFWE tWDD tWDD RDATA COMMAND [15:0] TACLS TWRPH0 TWRPH1 TACLS TWRPH0 TWRPH1 HCLK HCLK tALED tALED tALED tALED FALE FALE tWED tWED tWED tWED nFWE nFWE tWDD tWDD tWDD...
Page 653: Sdram Read / Write Timing (Trp = 2, Trcd = 2, Tcl = 2, Dw = 16-Bit)
S3C2416X RISC MICROPROCESSOR ELECTRICAL DATA Figure 26-14. SDRAM READ / WRITE Timing (Trp = 2, Trcd = 2, Tcl = 2, DW = 16-bit) 26-15...
Page 654: Ddr2 Timing
ELECTRICAL DATA S3C2416X RISC MICROPROCESSOR SCLK tSCD WRITE TIMING @ RL = 3, WL=RL-1 nSCAS tSWD nSWE tDQSS tWPRE SDATA READ TIMING @ RL = 3 nSCAS tSWD nSWE tDQSQ SDATA Figure 26-15. DDR2 Timing Parameter Symbol Unit DDR2 First DQS latching transition to associated 0.66 DQSS clock edge...
Page 655: Sdram Mrs Timing
S3C2416X RISC MICROPROCESSOR ELECTRICAL DATA SCLK SCKE tSAD tSAD SADDR tSAD A10/AP tSCSD tSCSD nSCSx tSRD tSRD nSRAS tSCD nSCAS DQMx tSWD tSWD nSWE SDATA 'HZ' Figure 26-16. SDRAM MRS Timing 26-17...
Page 656: Sdram Auto Refresh Timing (Trp = 2, Trc = 4)
ELECTRICAL DATA S3C2416X RISC MICROPROCESSOR SCLK SCKE tSAD tSAD SADDR tSAD A10/AP tSCSD tSCSD nSCSx tSRD tSRD nSRAS tSCD nSCAS DQMx tSWD nSWE SDATA 'HZ' Before executing auto/self refresh command, all banks must be in idle state. NOTE: Figure 26-17. SDRAM Auto Refresh Timing (Trp = 2, Trc = 4) 26-18...
Page 657: External Dma Timing (Handshake, Single Transfer)
S3C2416X RISC MICROPROCESSOR ELECTRICAL DATA HCLK tXRS nXDREQ tXRS tXAD tCADH nXDACK Read Write Min. 3SCLK tCADL Figure 26-18. External DMA Timing (Handshake, Single transfer) Tf2hsetup VSYNC Tf2hhold HSYNC Tvfpd Tvspw Tvbpd VDEN HSYNC Tl2csetup Tvclkh Tvclk VCLK Tvclkl Tvdhold Tvdsetup Tve2hold VDEN...
Page 658: Iis Interface Timing (I2S Master Mode Only)
ELECTRICAL DATA S3C2416X RISC MICROPROCESSOR I2SLRCLK(Output) LRId I2SSCLK(Output) I2SSDO(Output) Figure 26-20. IIS Interface Timing (I2S Master Mode Only) I2SLRCLK(Input) LRId I2SSCLK(Input) I2SSDI(Input) Figure 26-21. IIS Interface Timing (I2S Slave Mode Only) fSCL tSCLHIGH tSCLLOW IICSCL tSTOPH tBUF tSDAS tSDAH tSTARTS IICSDA Figure 26-22.
Page 659: High Speed Sdmmc Interface Timing
S3C2416X RISC MICROPROCESSOR ELECTRICAL DATA SD_CLK tHSDCD SD_CMD(out) tHSDCS tHSDCH SD_CMD(in) tHSDDD SD_DAT(out) tHSDDS tHSDDH SD_DAT(in) Figure 26-23. High Speed SDMMC Interface Timing SPICLK XspiMOSI (MO) tSPIMIH tSPIMOD XspiMISO (MI) tSPIMIS XspiMISO (SO) tSPISOD tSPISIH XspiMOSI (SI) tSPISIS tSPICSSD XspiCS tSPICSSS Figure 26-24.
Page 660: Usb Timing (Data Signal Rise/Fall Time)
ELECTRICAL DATA S3C2416X RISC MICROPROCESSOR Rise Time Fall Time VCRS Differential Data Lines Figure 26-25. USB Timing (Data signal rise/fall time) Figure 26-26. PCM Interface Timing 26-22...
Page 661: Clock Timing Constants
S3C2416X RISC MICROPROCESSOR ELECTRICAL DATA Table 26-8. Clock Timing Constants = -40 to 85°C, VDD_OP1 = 3.3V ± 0.3V) (VDDi = 1.3V± 0.05V (400MHz), VDDi = 1.3 V± 0.05V (266MHz), T Parameter Symbol Unit Crystal clock input frequency XTAL Crystal clock input cycle time XTALCYC (note 1) External clock input frequency...
Page 662: Smc Timing Constants
ELECTRICAL DATA S3C2416X RISC MICROPROCESSOR Table 26-9. SMC Timing Constants = -40 to 85°C, VDD_SRAM = 1.8V ± 0.1V) (VDDi = 1.3V± 0.05V (400MHz), VDDi = 1.3 V± 0.05V (266MHz), T Parameter Symbol Unit SMC Chip Select Delay bank0 5.72 bank1 6.40 bank2...
Page 663: Memory Interface Timing Constants (Sdram)
S3C2416X RISC MICROPROCESSOR ELECTRICAL DATA Table 26-11. Memory Interface Timing Constants (SDRAM) = -40 to 85°C, VDD_SDRAM = 1.8V ± 0.1V, (VDDi = 1.3V± 0.05V (400MHz), VDDi = 1.3 V± 0.05V (266MHz), T 133MHz, CL = 15pF) Parameter Symbol Unit SDRAM Address Delay 1.65 4.25...
Page 664: Dma Controller Module Signal Timing Constants
ELECTRICAL DATA S3C2416X RISC MICROPROCESSOR Table 26-12. DMA Controller Module Signal Timing Constants (VDDi = 1.3V± 0.05V (400MHz), VDDi = 1.3 V± 0.05V (266MHz), TA = -40 to 85°C, VDD_OP2 = 3.3V ± 0.3V) Parameter Symbol Unit eXternal Request Setup 6.4/6.4 9.9/9.9 aCcess to Ack Delay when Low transition...
Page 665: Iis Controller Module Signal Timing Constants(I2S Slave Mode Only)
S3C2416X RISC MICROPROCESSOR ELECTRICAL DATA Table 26-15. IIS Controller Module Signal Timing Constants(I2S Slave Mode Only) = –40 to 85 °C, VDD_OP2 = 3.3V ± 0.3V) (VDDi = 1.3V± 0.05V (400MHz), VDDi = 1.3 V± 0.05V (266MHz), T Parameter Symbol Min.
Page 666: High Speed Spi Interface Transmit/Receive Timing Constants
ELECTRICAL DATA S3C2416X RISC MICROPROCESSOR Table 26-17. High Speed SPI Interface Transmit/Receive Timing Constants = -40 to 85°C, VDD_SD = 3.3V ± 0.3V) (VDDi = 1.3V± 0.05V (400MHz), VDDi = 1.3 V± 0.05V (266MHz), T (SPICLKout = 50Mhz, PAD loading = 30pF) Parameter Symbol Typ.
Page 667: Usb Electrical Specifications
S3C2416X RISC MICROPROCESSOR ELECTRICAL DATA Table 26-18. USB Electrical Specifications (VDD12V = 1.2V ± 5%, T = -40 to 85°C, VDDA33x = 3.3V ± 0.3V) Parameter Symbol Condition Unit Supply Current Operating Current µA Room Temp (25°C) Suspended Current Hot Temp (8°C) Input Levels for Full speed Differential Input Sensitivity Differential Common Mode Range...
Page 668: Usb Full Speed Output Buffer Electrical Characteristics
ELECTRICAL DATA S3C2416X RISC MICROPROCESSOR Table 26-19. USB Full Speed Output Buffer Electrical Characteristics = -40 to 85°C, VDDA33x = 3.3V ± 0.3V) (VDDi = 1.3V± 0.05V (400MHz), VDDi = 1.3 V± 0.05V (266MHz), T Parameter Symbol Condition Unit Driver Characteristics Transition Time Rise Time CL = 50pF...
Page 669: Pcm Interface Timing
S3C2416X RISC MICROPROCESSOR ELECTRICAL DATA Table 26-22. PCM Interface Timing = 3.3V ± 0.3V, 2.5V ± 0.2V, 1.8V ± 0.1V) (VDDiI = 1.0V± 0.05V, T = -40 to 85°C, V Parameter Symbol Min. Typ. Unit PCMSCLK clock width 0.128 8.192 PCMSCLK to PCMFSYNC delay dFSYNC PCMSCLK to PCMSOUT delay...
Page 670 ELECTRICAL DATA S3C2416X RISC MICROPROCESSOR NOTES 26-32...
Page 671: Mechanical Data
S3C2416X RISC MICROPROCESSOR MECHANICAL DATA MECHANICAL DATA 1 PACKAGE DIMENSIONS Figure 27-1. 330-FBGA-1414 Package Dimension 1 (Top View) 30-1...
Page 672 MECHANICAL DATA S3C2416X RISC MICROPROCESSOR Figure 27-2. 330-FBGA-1414 Package Dimension 2 (Bottom View) 30-2...

Samsung S3C2416 User Manual

Chapter 1 Product Overview

Chapter 2 System Controller

Chapter 3 Bus Matrix & EBI

Chapter 4 Bus Priorities

Chapter 5 Static Memory Controller (SMC)

Chapter 6 Mobile DRAM Controller

Chapter 7 NAND Flash Controller

Chapter 8 DMA Controller

Chapter 9 Interrupt Controller

Chapter 10 I/O Ports

Chapter 11 Watchdog Timer

Chapter 12 PWM Timer

Chapter 13 Real Time Clock (RTC)

Chapter 14 UART

Chapter 15 USB Host Controller

Chapter 16 USB 2.0 Function

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Summary of Contents for Samsung S3C2416