ST STM32F205 series Reference Manual page 98

Reset and clock control (RCC)
Bits 17:16 PLLP: Main PLL (PLL) division factor for main system clock
Caution: The software has to set these bits correctly not to exceed 120 MHz on this domain.
Bits 14:6 PLLN: Main PLL (PLL) multiplication factor for VCO
Set and cleared by software to control the multiplication factor of the VCO. These bits can be
written only when PLL is disabled. Only half-word and word accesses are allowed to write
these bits.
Caution: The software has to set these bits correctly to ensure that the VCO output
Bits 5:0 PLLM: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
Set and cleared by software to divide the PLL and PLLI2S input clock before the VCO. These
bits can be written only when the PLL and PLLI2S are disabled.
Caution: The software has to set these bits correctly to ensure that the VCO input frequency
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Set and cleared by software to control the frequency of the general PLL output clock. These
bits can be written only if PLL is disabled.
PLL output clock frequency = VCO frequency / PLLP with PLLP = 2, 4, 6, or 8
00: PLLP = 2
01: PLLP = 4
10: PLLP = 6
11: PLLP = 8
frequency is between 64 and 432 MHz.
VCO output frequency = VCO input frequency × PLLN with 64 ≤ PLLN ≤ 432
000000000: PLLN = 0, wrong configuration
000000001: PLLN = 1, wrong configuration
...
011000000: PLLN = 192
011000001: PLLN = 193
011000010: PLLN = 194
...
110110000: PLLN = 432
110110001: PLLN = 433, wrong configuration
...
111111111: PLLN = 511, wrong configuration
ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit
PLL jitter.
VCO input frequency = PLL input clock frequency / PLLM with 2 ≤ PLLM ≤ 63
000000: PLLM = 0, wrong configuration
000001: PLLM = 1, wrong configuration
000010: PLLM = 2
000011: PLLM = 3
000100: PLLM = 4
...
111110: PLLM = 62
111111: PLLM = 63
RM0033 Rev 8
RM0033