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ST STM32F205 series Reference Manual

ST STM32F205 series Reference Manual

Advanced arm-based 32-bit mcus

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STM32F205xx, STM32F207xx, STM32F215xx and STM32F217xx

Introduction

This reference manual targets application developers. It provides complete information on

how to use the STM32F205xx, STM32F207xx, STM32F215xx and STM32F217xx

microcontroller memory and peripherals. The STM32F205xx, STM32F207xx,

STM32F215xx and STM32F217xx will be referred to as STM32F20x and STM32F21x

throughout the document, unless otherwise specified.

The STM32F20x and STM32F21x constitute a family of microcontrollers with different

memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics, please refer to

the STM32F20x and STM32F21x datasheets.

For information on programming, erasing and protection of the internal Flash memory

please refer to the STM32F20x and STM32F21x Flash programming manual.

For information on the Arm

Reference Manual.

Related documents

Available from www.arm.com:

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• Cortex

Available from your STMicroelectronics sales office:

• STM32F20x and STM32F21x datasheets

• STM32F20x and STM32F21x Flash programming manual

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• Cortex

2018

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Cortex

-M3 Technical Reference Manual, available from http://infocenter.arm.com

-M3 programming manual (PM0056)

Reference manual

advanced Arm-based 32-bit MCUs

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-M3 core, please refer to the Cortex

RM0033 Rev 8

RM0033

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Summary of Contents for ST STM32F205 series

Page 1 • Cortex -M3 Technical Reference Manual, available from http://infocenter.arm.com Available from your STMicroelectronics sales office: • STM32F20x and STM32F21x datasheets • STM32F20x and STM32F21x Flash programming manual ® • Cortex -M3 programming manual (PM0056) 2018 RM0033 Rev 8 1/1378 www.st.com...
Page 2: Table Of Contents
Contents RM0033 Contents Documentation conventions ....... . . 46 General information ......... 46 List of abbreviations for registers .
Page 3 RM0033 Contents 3.4.3 Control register (CRC_CR) ........63 3.4.4 CRC register map .
Page 4: Syscfg External Interrupt Configuration Register
Contents RM0033 5.2.7 Clock security system (CSS) ....... . . 91 5.2.8 RTC/AWU clock .
Page 5 RM0033 Contents GPIO main features ........138 GPIO functional description .
Page 6 Contents RM0033 SYSCFG registers ......... 159 7.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP) .
Page 7 RM0033 Contents 9.3.1 General description ........178 9.3.2 DMA transactions .
Page 8 Contents RM0033 10.3.2 ADC clock ..........214 10.3.3 Channel selection .
Page 9 RM0033 Contents 10.13.9 ADC regular sequence register 1 (ADC_SQR1) ....246 10.13.10 ADC regular sequence register 2 (ADC_SQR2) ....247 10.13.11 ADC regular sequence register 3 (ADC_SQR3) .
Page 10 Contents RM0033 11.5 DAC registers ..........268 11.5.1 DAC control register (DAC_CR) .
Page 11 RM0033 Contents 12.6 Data format description ........288 12.6.1 Data formats .
Page 12 Contents RM0033 13.3.13 Clearing the OCxREF signal on an external event ....336 13.3.14 6-step PWM generation ........337 13.3.15 One-pulse mode .
Page 13 RM0033 Contents 14.3.2 Counter modes ......... . 379 14.3.3 Clock selection .
Page 14 Contents RM0033 General-purpose timers (TIM9 to TIM14) ..... . . 437 15.1 TIM9 to TIM14 introduction ........437 15.2 TIM9 to TIM14 main features .
Page 15 RM0033 Contents 15.5.2 TIM10/11/13/14 Interrupt enable register (TIMx_DIER) ... . 475 15.5.3 TIM10/11/13/14 status register (TIMx_SR) ..... 475 15.5.4 TIM10/11/13/14 event generation register (TIMx_EGR) .
Page 16 Contents RM0033 17.3.2 Register access protection ....... . . 497 17.3.3 Debug mode .
Page 17 RM0033 Contents 19.6.2 CRYP status register (CRYP_SR) ......534 19.6.3 CRYP data input register (CRYP_DIN) ......535 19.6.4 CRYP data output register (CRYP_DOUT) .
Page 18 Contents RM0033 21.4.1 HASH control register (HASH_CR) ......559 21.4.2 HASH data input register (HASH_DIN) ......562 21.4.3 HASH start register (HASH_STR) .
Page 19 RM0033 Contents 22.6.8 RTC alarm A register (RTC_ALRMAR) ......591 22.6.9 RTC alarm B register (RTC_ALRMBR) ......592 22.6.10 RTC write protection register (RTC_WPR) .
Page 20 Contents RM0033 Universal synchronous asynchronous receiver transmitter (USART) ........631 24.1 USART introduction .
Page 21 RM0033 Contents 25.3 SPI functional description ........686 25.3.1 General description .
Page 22 Contents RM0033 26.2 SDIO bus topology ......... 737 26.3 SDIO functional description .
Page 23 RM0033 Contents 26.7.3 CE-ATA interrupt ......... 776 26.7.4 Aborting CMD61 .
Page 24 Contents RM0033 27.5.3 Loop back combined with silent mode ......799 27.6 Debug mode ..........800 27.7 bxCAN functional description .
Page 25 RM0033 Contents 28.5.5 MAC filtering ..........867 28.5.6 MAC loopback mode .
Page 26 Contents RM0033 29.4.3 SRP dual role device ........964 29.5 USB peripheral .
Page 27 RM0033 Contents 29.17.1 Core initialization ........1053 29.17.2 Host initialization .
Page 28 Contents RM0033 30.9 Dynamic update of the OTG_HS_HFIR register ....1114 30.10 FIFO RAM allocation ........1115 30.10.1 Peripheral mode .
Page 29 RM0033 Contents 31.5.4 NOR Flash/PSRAM controller asynchronous transactions ..1269 31.5.5 Synchronous transactions ....... . . 1286 31.5.6 NOR/PSRAM control registers .
Page 30 Contents RM0033 32.8.4 DP and AP read/write accesses ......1328 32.8.5 SW-DP registers ........1329 32.8.6 SW-AP registers .
Page 31 RM0033 Contents Device electronic signature ....... . 1348 33.1 Unique device ID register (96 bits) ......1348 33.2 Flash size .
Page 32 List of tables RM0033 List of tables Table 1. STM32F20x and STM32F21x register boundary addresses ..... . . 51 Table 2. Flash module organization .
Page 33 RM0033 List of tables Table 49. Positioning of captured data bytes in 32-bit words (14-bit width) ....282 Table 50. Data storage in monochrome progressive video format ......289 Table 51.
Page 34 List of tables RM0033 oversampling by 8 ............651 Table 93.
Page 35 RM0033 List of tables Table 144. Destination address filtering ..........869 Table 145.
Page 36 List of tables RM0033 Table 195. FSMC_BCRx bit fields ..........1288 Table 196.
Page 37 RM0033 List of figures List of figures Figure 1. System architecture ............49 Figure 2.
Page 38 List of figures RM0033 Figure 49. Data registers in single DAC channel mode ........259 Figure 50.
Page 39 RM0033 List of figures Figure 101. Dead-time waveforms with delay greater than the positive pulse....332 Figure 102. Output behavior in response to a break........335 Figure 103.
Page 40 List of figures RM0033 Figure 153. Master/Slave timer example ..........408 Figure 154.
Page 41 RM0033 List of figures Figure 203. AES-CBC mode decryption ..........519 Figure 204.
Page 42 List of figures RM0033 Figure 255. TXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers ........697 Figure 256.
Page 43 RM0033 List of figures Figure 301. bxCAN in loop back mode ..........799 Figure 302.
Page 44 List of figures RM0033 Figure 353. SOF connectivity ............973 Figure 354.
Page 45 RM0033 List of figures Figure 403. Mode2 and mode B read accesses ........1274 Figure 404.
Page 46: Documentation Conventions
Documentation conventions RM0033 Documentation conventions General information The STM32F205xx, STM32F207xx, STM32F215xx and STM32F217xx devices have an ®(a) ® Cortex -M3 core. List of abbreviations for registers The following abbreviations are used in register descriptions: read/write (rw) Software can read and write to these bits. read-only (r) Software can only read these bits.
Page 47: Peripheral Availability
RM0033 Documentation conventions Peripheral availability For peripheral availability and number across all STM32F20x and STM32F21x sales types, please refer to the STM32F20x and STM32F21x datasheets. RM0033 Rev 8 47/1378...
Page 48: Memory And Bus Architecture
Memory and bus architecture RM0033 Memory and bus architecture System architecture The main system consists of 32-bit multilayer AHB bus matrix that interconnects: • Height masters: ® – Cortex -M3 core I-bus, D-bus and S-bus – DMA1 memory bus – DMA2 memory bus –...
Page 49: S0: I-Bus
RM0033 Memory and bus architecture Figure 1. System architecture USB OTG Cortex-M3 DMA1 DMA2 Ethernet ICODE Flash memory DCODE SRAM 112 Kbyte SRAM 16 Kbyte APB1 periph 1 APB2 periph 2 FSMC Static MemCtl Bus matrix-S ai15963b 2.1.1 S0: I-bus ®...
Page 50: S5: Dma Peripheral Bus
Memory and bus architecture RM0033 2.1.5 S5: DMA peripheral bus This bus connects the DMA peripheral master bus interface to the BusMatrix. This bus is used by the DMA to access AHB peripherals or to perform memory-to-memory transfers. The targets of this bus are the AHB and APB peripherals plus data memories: internal SRAM and external memories through the FSMC.
Page 51: Memory Map
RM0033 Memory and bus architecture Memory map See the datasheet corresponding to your device for a comprehensive diagram of the memory map. Table 1 gives the boundary addresses of the peripherals available in all STM32F20x and STM32F21x devices. Table 1. STM32F20x and STM32F21x register boundary addresses Boundary address Peripheral Register map...
Page 52 Memory and bus architecture RM0033 Table 1. STM32F20x and STM32F21x register boundary addresses (continued) Boundary address Peripheral Register map 0x4001 4800 - 0x4001 4BFF TIM11 Section 15.5.12: TIM10/11/13/14 register map on page 482 0x4001 4400 - 0x4001 47FF TIM10 Section 15.4.14: TIM9/12 register map on 0x4001 4000 - 0x4001 43FF TIM9 page 472...
Page 53: Embedded Sram
RM0033 Memory and bus architecture Table 1. STM32F20x and STM32F21x register boundary addresses (continued) Boundary address Peripheral Register map 0x4000 7400 - 0x4000 77FF Section 11.5.15: DAC register map on page 276 0x4000 7000 - 0x4000 73FF Section 4.4.3: PWR register map on page 83 0x4000 6800 - 0x4000 6BFF CAN2 Section 27.9.5: bxCAN register map on page 834...
Page 54: Bit Banding
Memory and bus architecture RM0033 instance, the Ethernet MAC can read/write from/to the 16 KB SRAM while the CPU is reading/writing from/to the 112 KB SRAM. The CPU can access the system SRAM through the System Bus or through the I-Code/D- Code buses when boot from SRAM is selected or when physical remap is selected (SYSCFG memory remap register (SYSCFG_MEMRMP) in the SYSCFG controller).
Page 55: Embedded Flash Memory
RM0033 Memory and bus architecture 2.3.3 Embedded Flash memory The Flash memory has the following main features: • Capacity up to 1 Mbyte • 128 bits wide data read • Byte, half-word, word and double word write • Sector and mass erase •...
Page 56: Table 3. Number Of Wait States According To Cortex ® -M3 Clock Frequency
Memory and bus architecture RM0033 ® Table 3. Number of wait states according to Cortex -M3 clock frequency ® HCLK - Cortex -M3 clock frequency (MHz) Wait states (WS) Voltage range Voltage range Voltage range Voltage range (LATENCY) 2.7 to 3.6 V 2.4 to 2.7 V 2.1 to 2.4 V to 2.1 V...
Page 57 RM0033 Memory and bus architecture configured, you can check the AHB prescaler factor and clock source status values. To make sure that the number of WS you have programmed is effective, you can read the FLASH_ACR register. The FLASH_ACR register is used to enable/disable the acceleration features and control the Flash memory access time according to CPU frequency.
Page 58: Adaptive Real-Time Memory Accelerator (Art Accelerator™)
Memory and bus architecture RM0033 Bit 8 PRFTEN: Prefetch enable 0: Prefetch is disabled 1: Prefetch is enabled Bits 7:3 Reserved, must be kept cleared. Bits 2:0 LATENCY: Latency These bits represent the ratio of the CPU clock period to the Flash memory access time. 000: Zero wait state 001: One wait state 010: Two wait states...
Page 59: Table 5. Memory Mapping Vs. Boot Mode/Physical Remap
RM0033 Memory and bus architecture The values on the BOOT pins are latched on the 4th rising edge of SYSCLK after a reset. It is up to the user to set the BOOT1 and BOOT0 pins after reset to select the required boot mode.
Page 60 CAN and USB OTG FS require an external clock (HSE) multiple of 1 MHz (ranging from 4 to 26 MHz). The embedded bootloader code is located in system memory. It is programmed by ST during production. For additional information, refer to application note AN2606.
Page 61: Crc Calculation Unit
RM0033 CRC calculation unit CRC calculation unit This section applies to the whole STM32F20x and STM32F21x and family, unless otherwise specified. CRC introduction The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.
Page 62: Crc Functional Description
CRC calculation unit RM0033 CRC functional description The CRC calculation unit mainly consists of a single 32-bit data register, which: • is used as an input register to enter new data in the CRC calculator (when writing into the register) •...
Page 63: Control Register (Crc_Cr)
RM0033 CRC calculation unit Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 General-purpose 8-bit data register bits Can be used as a temporary storage location for one byte. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register.
Page 64: Power Control (Pwr)
Power control (PWR) RM0033 Power control (PWR) Power supplies The device requires a 1.8-to-3.6 V operating voltage supply (V ). An embedded linear voltage regulator is used to supply the internal 1.2 V digital power. The real-time clock (RTC), the RTC backup registers, and the backup SRAM (BKP SRAM) can be powered from the V voltage when the main V supply is powered off.
Page 65: Independent A/D Converter Supply And Reference Voltage
RM0033 Power control (PWR) 4.1.1 Independent A/D converter supply and reference voltage To improve conversion accuracy, the ADC has an independent power supply which can be separately filtered and shielded from noise on the PCB. • The ADC voltage supply input is available on a separate V pin.
Page 66: Table 17. Rtc_Af2 Pin
Power control (PWR) RM0033 When the backup domain is supplied by V (analog switch connected to V ), the following functions are available: • PC14 and PC15 can be used as either GPIO or LSE pins • PC13 can be used as a GPIO or as the RTC_AF1 pin (refer to Table 16: RTC_AF1 pin for more details about this pin configuration) •...
Page 67: Voltage Regulator
RM0033 Power control (PWR) Backup SRAM The backup domain includes 4 Kbytes of backup SRAM addressed in 32-bit, 16-bit or 8-bit mode. Its content is retained even in Standby or V mode when the low-power backup regulator is enabled. It can be considered as an internal EEPROM when V is always present.
Page 68: Power Supply Supervisor
Power control (PWR) RM0033 The voltage regulator is always enabled after Reset. It works in three different modes depending on the application modes. • In Run mode, the regulator supplies full power to the 1.2 V domain (core, memories and digital peripherals). •...
Page 69: Brownout Reset (Bor)
RM0033 Power control (PWR) 4.2.2 Brownout reset (BOR) During power on, the Brownout reset (BOR) keeps the device under reset until the supply voltage reaches the specified V threshold. is configured through device option bytes. By default, BOR is off. Three programmable V threshold levels can be selected: BOR Level 3 (V...
Page 70: Low-Power Modes
Power control (PWR) RM0033 Figure 7. PVD thresholds 100 mV PVD threshold hysteresis PVD output Low-power modes By default, the microcontroller is in Run mode after a system or a power-on reset. In Run mode the CPU is clocked by HCLK and the program code is executed. Several low-power modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event.
Page 71 RM0033 Power control (PWR) Exiting low-power mode The MCU exits from Sleep and Stop modes low-power mode depending on the way the low- power mode was entered: • If the WFI instruction or Return from ISR was used to enter the low-power mode, any peripheral interrupt acknowledged by the NVIC can wake up the device.
Page 72: Slowing Down System Clocks
Power control (PWR) RM0033 Table 7. Low-power mode summary Effect on Effect on 1.2 V Mode name Entry Wakeup Voltage regulator domain clocks domain clocks WFI or Return CPU CLK OFF Sleep Any interrupt from ISR no effect on other (Sleep now or None clocks or analog...
Page 73: Sleep Mode
RM0033 Power control (PWR) 4.3.3 Sleep mode Entering Sleep mode The Sleep mode is entered according to Section : Entering low-power mode, when the ® SLEEPDEEP bit in the Cortex -M3 System Control register is cleared. Refer to Table 8 Table 9 for details on how to enter Sleep mode.
Page 74: Stop Mode
Power control (PWR) RM0033 4.3.4 Stop mode ® The Stop mode is based on the Cortex -M3 deepsleep mode combined with peripheral clock gating. The voltage regulator can be configured either in normal or low-power mode. In Stop mode, all clocks in the 1.2 V domain are stopped, the PLLs, the HSI and the HSE RC oscillators are disabled.
Page 75: Table 10. Stop Mode
RM0033 Power control (PWR) Exiting Stop mode The Stop mode is exited according to Section : Exiting low-power mode. Refer to Table 10 for more details on how to exit Stop mode. When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock.
Page 76: Standby Mode
Power control (PWR) RM0033 4.3.5 Standby mode The Standby mode allows to achieve the lowest power consumption. It is based on the ® Cortex -M3 deepsleep mode, with the voltage regulator disabled. The 1.2 V domain is consequently powered off. The PLLs, the HSI oscillator and the HSE oscillator are also switched off.
Page 77: Table 11. Standby Mode
RM0033 Power control (PWR) Table 11. Standby mode Standby mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: ® – SLEEPDEEP is set in Cortex -M3 System Control register – PDDS bit is set in Power Control register (PWR_CR) –...
Page 78: Programming The Rtc Alternate Functions To Wake Up The Device From The Stop And Standby Modes
Power control (PWR) RM0033 4.3.6 Programming the RTC alternate functions to wake up the device from the Stop and Standby modes The MCU can be woken up from a low-power mode by an RTC alternate function. The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
Page 79 RM0033 Power control (PWR) RTC alternate functions to wake up the device from the Standby mode • To wake up the device from the Standby mode with an RTC alarm event, it is necessary Enable the RTC alarm interrupt in the RTC_CR register Configure the RTC to generate the RTC alarm •...
Page 80: Power Control Registers
Power control (PWR) RM0033 Enable the RTC TimeStamp interrupt Re-enter the low-power mode Power control registers The power control registers can be accessed by half-words (16 bits) or words (32 bits). 4.4.1 PWR power control register (PWR_CR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by wakeup from Standby mode) Reserved FPDS...
Page 81: Pwr Power Control/Status Register (Pwr_Csr)
RM0033 Power control (PWR) Bit 3 CSBF: Clear standby flag This bit is always read as 0. 0: No effect 1: Clear the SBF Standby Flag (write). Bit 2 CWUF: Clear wakeup flag This bit is always read as 0. 0: No effect 1: Clear the WUF Wakeup Flag after 2 System clock cycles Bit 1 PDDS: Power down deepsleep...
Page 82 Power control (PWR) RM0033 Bit 8 EWUP: Enable WKUP pin This bit is set and cleared by software. 0: WKUP pin is used for general purpose I/O. An event on the WKUP pin does not wakeup the device from Standby mode. 1: WKUP pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin wakes-up the system from Standby mode).
Page 83: Pwr Register Map
RM0033 Power control (PWR) 4.4.3 PWR register map The following table summarizes the PWR registers. Table 12. PWR - register map and reset values Offset Register PLS[2: PWR_CR 0x000 Reserved Reset 0 0 0 0 0 0 0 0 0 0 value PWR_CS 0x004...
Page 84: Reset And Clock Control (Rcc)
Reset and clock control (RCC) RM0033 Reset and clock control (RCC) Reset There are three types of reset, defined as system Reset, power Reset and backup domain Reset. 5.1.1 System reset A system reset sets all registers to their reset values except the reset flags in the clock controller CSR register and the registers in the Backup domain (see Figure "A system reset sets all registers to their reset values unless specified otherwise in the...
Page 85: Power Reset
In this case, whenever a Stop mode entry sequence is successfully executed, the device is reset instead of entering the Stop mode. For further information on the user option bytes, refer to the STM32F20x and STM32F21x Flash programming manual available from your ST sales office. 5.1.2 Power reset...
Page 86: Backup Domain Reset
Reset and clock control (RCC) RM0033 5.1.3 Backup domain reset The backup domain reset sets all RTC registers and the RCC_BDCR register to their reset values. The BKPSRAM is not affected by this reset. The only way of resetting the BKPSRAM is through the Flash interface by requesting a protection level change from 1 to A backup domain reset is generated when one of the following events occurs: Software reset, triggered by setting the BDRST bit in the...
Page 87: Figure 9. Clock Tree
RM0033 Reset and clock control (RCC) Figure 9. Clock tree Watchdog IWDGCLK enable to independent LSI RC watchdog 32 kHz RTCSEL[1:0] RTCCLK OSC32_IN enable to RTC LSE OS C 32.768 kHz OSC32_OUT SYSCLK MCO2 /1 to 5 HSE_RTC MCO1 Peripheral /1 to 5 Ethernet /2 to 31...
Page 88: Hse Clock
Reset and clock control (RCC) RM0033 The clock controller provides a high degree of flexibility to the application in the choice of the external crystal or the oscillator to run the core and peripherals at the highest frequency and, guarantee the appropriate frequency for peripherals that need a specific clock like Ethernet, USB OTG FS and HS, I2S and SDIO.
Page 89: Hsi Clock
RM0033 Reset and clock control (RCC) Figure 10. HSE/ LSE clock sources Hardware configuration OSC_OUT External clock (HiZ) External source OSC_IN OSC_OUT Crystal/ceramicr esonators Load capacitors External source (HSE bypass) In this mode, an external clock source must be provided. You select this mode by setting the HSEBYP and HSEON bits in the RCC clock control register (RCC_CR).
Page 90: Pll Configuration
Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at T = 25 °C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the...
Page 91: Lsi Clock
RM0033 Reset and clock control (RCC) The LSERDY flag in the RCC Backup domain control register (RCC_BDCR) indicates if the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be generated if enabled in the RCC clock interrupt register (RCC_CIR).
Page 92: Rtc/Awu Clock
Reset and clock control (RCC) RM0033 If the HSE oscillator is used directly or indirectly as the system clock (indirectly meaning that it is directly used as PLL input clock, and that PLL clock is the system clock) and a failure is detected, then the system clock switches to the HSI oscillator and the HSE oscillator is disabled.
Page 93: Clock-Out Capability
RM0033 Reset and clock control (RCC) 5.2.10 Clock-out capability Two microcontroller clock output (MCO) pins are available: • MCO1 You can output four different clock sources onto the MCO1 pin (PA8) using the configurable prescaler (from 1 to 5): – HSI clock –...
Page 94: Figure 11. Frequency Measurement With Tim5 In Input Capture Mode
Reset and clock control (RCC) RM0033 The basic concept consists in providing a relative measurement (e.g. HSI/LSE ratio): the precision is therefore tightly linked to the ratio between the two clock sources. The greater the ratio, the better the measurement. It is also possible to measure the LSI frequency: this is useful for applications that do not have a crystal.
Page 95: Rcc Registers
RM0033 Reset and clock control (RCC) RCC registers The RCC registers can be accessed by bytes (8 bits), half-words (16 bits) or words (32 bits). Refer to Section 1.2 on page 46 for a list of abbreviations used in register descriptions. 5.3.1 RCC clock control register (RCC_CR) Address offset: 0x00...
Page 96 Reset and clock control (RCC) RM0033 Bit 18 HSEBYP: HSE clock bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled.
Page 97: Rcc Pll Configuration Register (Rcc_Pllcfgr)
RM0033 Reset and clock control (RCC) 5.3.2 RCC PLL configuration register (RCC_PLLCFGR) Address offset: 0x04 Reset value: 0x24003010 Access: no wait state, word, half-word and byte access. This register is used to configure the PLL clock outputs according to the formulas: •...
Page 98 Reset and clock control (RCC) RM0033 Bits 17:16 PLLP: Main PLL (PLL) division factor for main system clock Set and cleared by software to control the frequency of the general PLL output clock. These bits can be written only if PLL is disabled. Caution: The software has to set these bits correctly not to exceed 120 MHz on this domain.
Page 99: Rcc Clock Configuration Register (Rcc_Cfgr)
RM0033 Reset and clock control (RCC) 5.3.3 RCC clock configuration register (RCC_CFGR) Address offset: 0x08 Reset value: 0x0000 0000 Access: 0 ≤ wait state ≤ 2, word, half-word and byte access 1 or 2 wait states inserted only if the access occurs during a clock source switch. I2SSC MCO2 MCO2 PRE[2:0]...
Page 100 Reset and clock control (RCC) RM0033 Bits 22:21 MCO1: Microcontroller clock output 1 Set and cleared by software. Clock source selection may generate glitches on MCO1. It is highly recommended to configure these bits only after reset before enabling the external oscillators and PLL.
Page 101: Rcc Clock Interrupt Register (Rcc_Cir)
RM0033 Reset and clock control (RCC) Bits 7:4 HPRE: AHB prescaler Set and cleared by software to control AHB clock division factor. Caution: The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after HPRE write. Caution: The AHB clock frequency must be at least 25 MHz when the Ethernet is used.
Page 102 Reset and clock control (RCC) RM0033 Bits 31:24 Reserved, always read as 0. Bit 23 CSSC: Clock security system interrupt clear This bit is set by software to clear the CSSF flag. 0: No effect 1: Clear CSSF flag Bits 22 Reserved, always read as 0.
Page 103 RM0033 Reset and clock control (RCC) Bit 10 HSIRDYIE: HSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization. 0: HSI ready interrupt disabled 1: HSI ready interrupt enabled Bit 9 LSERDYIE: LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization.
Page 104: Rcc Ahb1 Peripheral Reset Register (Rcc_Ahb1Rstr)
Reset and clock control (RCC) RM0033 Bit 0 LSIRDYF: LSI ready interrupt flag Set by hardware when the internal low speed clock becomes stable and LSIRDYDIE is set. Cleared by software setting the LSIRDYC bit. 0: No clock ready interrupt caused by the LSI oscillator 1: Clock ready interrupt caused by the LSI oscillator 5.3.5 RCC AHB1 peripheral reset register (RCC_AHB1RSTR)
Page 105 RM0033 Reset and clock control (RCC) Bit 8 GPIOIRST: IO port I reset Set and cleared by software. 0: does not reset IO port I 1: resets IO port I Bit 7 GPIOHRST: IO port H reset Set and cleared by software. 0: does not reset IO port H 1: resets IO port H Bits 6 GPIOGRST: IO port G reset...
Page 106: Rcc Ahb2 Peripheral Reset Register (Rcc_Ahb2Rstr)
Reset and clock control (RCC) RM0033 5.3.6 RCC AHB2 peripheral reset register (RCC_AHB2RSTR) Address offset: 0x14 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Reserved OTGFS HASH CRYP DCMI Reserved Reserved Bits 31:8 Reserved, always read as 0. Bit 7 OTGFSRST: USB OTG FS module reset Set and cleared by software.
Page 107: Rcc Ahb3 Peripheral Reset Register (Rcc_Ahb3Rstr)
RM0033 Reset and clock control (RCC) 5.3.7 RCC AHB3 peripheral reset register (RCC_AHB3RSTR) Address offset: 0x18 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. Reserved FSMCRST Reserved Bits 31:1 Reserved, always read as 0. Bit 0 FSMCRST: Flexible static memory controller module reset Set and cleared by software.
Page 108 Reset and clock control (RCC) RM0033 Bit 26 CAN2RST: CAN2 reset Set and cleared by software. 0: does not reset CAN2 1: resets CAN2 Bit 25 CAN1RST: CAN1 reset Set and cleared by software. 0: does not reset CAN1 1: resets CAN1 Bit 24 Reserved, always read as 0.
Page 109 RM0033 Reset and clock control (RCC) Bits 13:12 Reserved, always read as 0. Bit 11 WWDGRST: Window watchdog reset Set and cleared by software. 0: does not reset the window watchdog 1: resets the window watchdog Bits 10:9 Reserved, always read as 0. Bit 8 TIM14RST: TIM14 reset Set and cleared by software.
Page 110: Rcc Apb2 Peripheral Reset Register (Rcc_Apb2Rstr)
Reset and clock control (RCC) RM0033 5.3.9 RCC APB2 peripheral reset register (RCC_APB2RSTR) Address offset: 0x24 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. TIM11 TIM10 TIM9 Reserved USART USART SPI1 SDIO TIM8 TIM1 SYSCF Reser- G RST Reser- Reserved...
Page 111 RM0033 Reset and clock control (RCC) Bit 8 ADCRST: ADC interface reset (common to all ADCs) Set and cleared by software. 0: does not reset the ADC interface 1: resets the ADC interface Bits 7:6 Reserved, always read as 0. Bit 5 USART6RST: USART6 reset Set and cleared by software.
Page 112: Rcc Ahb1 Peripheral Clock Register (Rcc_Ahb1Enr)
Reset and clock control (RCC) RM0033 5.3.10 RCC AHB1 peripheral clock register (RCC_AHB1ENR) Address offset: 0x30 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. ETHMA OTGHS OTGHS ETHMA ETHMA ETHMA BKPSR CPTPE DMA2EN DMA1EN Reser- ULPIEN CRXEN CTXEN...
Page 113 RM0033 Reset and clock control (RCC) Bit 21 DMA1EN: DMA1 clock enable Set and cleared by software. 0: DMA1 clock disabled 1: DMA1 clock enabled Bits 20:19 Reserved, always read as 0. Bit 18 BKPSRAMEN: Backup SRAM interface clock enable Set and cleared by software.
Page 114: Rcc Ahb2 Peripheral Clock Enable Register (Rcc_Ahb2Enr)
Reset and clock control (RCC) RM0033 Bit 1 GPIOBEN: IO port B clock enable Set and cleared by software. 0: IO port B clock disabled 1: IO port B clock enabled Bit 0 GPIOAEN: IO port A clock enable Set and cleared by software. 0: IO port A clock disabled 1: IO port A clock enabled 5.3.11...
Page 115: Rcc Ahb3 Peripheral Clock Enable Register (Rcc_Ahb3Enr)
RM0033 Reset and clock control (RCC) 5.3.12 RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) Address offset: 0x38 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. Reserved FSMCEN Reserved Bits 31:1 Reserved, always read as 0. Bit 0 FSMCEN: Flexible static memory controller module clock enable Set and cleared by software.
Page 116 Reset and clock control (RCC) RM0033 Bit 25 CAN1EN: CAN 1 clock enable Set and cleared by software. 0: CAN 1 clock disabled 1: CAN 1 clock enabled Bit 24 Reserved, always read as 0. Bit 23 I2C3EN: I2C3 clock enable Set and cleared by software.
Page 117 RM0033 Reset and clock control (RCC) Bit 11 WWDGEN: Window watchdog clock enable Set and cleared by software. 0: Window watchdog clock disabled 1: Window watchdog clock enabled Bit 10:9 Reserved, always read as 0. Bit 8 TIM14EN: TIM14 clock enable Set and cleared by software.
Page 118: Rcc Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr)
Reset and clock control (RCC) RM0033 5.3.14 RCC APB2 peripheral clock enable register (RCC_APB2ENR) Address offset: 0x44 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. TIM11 TIM10 TIM9 Reserved SPI1 SDIO ADC3 ADC2 ADC1 USART6 USART1 TIM8 TIM1...
Page 119 RM0033 Reset and clock control (RCC) Bit 9 ADC2EN: ADC2 clock enable Set and cleared by software. 0: ADC2 clock disabled 1: ADC2 clock disabled Bit 8 ADC1EN: ADC1 clock enable Set and cleared by software. 0: ADC1 clock disabled 1: ADC1 clock disabled Bits 7:6 Reserved, always read as 0.
Page 120: Rcc Ahb1 Peripheral Clock Enable In Low Power Mode Register (Rcc_Ahb1Lpenr)
Reset and clock control (RCC) RM0033 5.3.15 RCC AHB1 peripheral clock enable in low power mode register (RCC_AHB1LPENR) Address offset: 0x50 Reset value: 0x7E67 91FF Access: no wait state, word, half-word and byte access. BKPSRA OTGHS OTGHS ETHPTP ETHRX ETHTX ETHMAC DMA2 DMA1...
Page 121 RM0033 Reset and clock control (RCC) Bit 21 DMA1LPEN: DMA1 clock enable during Sleep mode Set and cleared by software. 0: DMA1 clock disabled during Sleep mode 1: DMA1 clock enabled during Sleep mode Bits 20:19 Reserved, always read as 0. Bit 18 BKPSRAMLPEN: Backup SRAM interface clock enable during Sleep mode Set and cleared by software.
Page 122: Rcc Ahb2 Peripheral Clock Enable In Low Power Mode Register (Rcc_Ahb2Lpenr)
Reset and clock control (RCC) RM0033 Bit 4 GPIOELPEN: IO port E clock enable during Sleep mode Set and cleared by software. 0: IO port E clock disabled during Sleep mode 1: IO port E clock enabled during Sleep mode Bit 3 GPIODLPEN: IO port D clock enable during Sleep mode Set and cleared by software.
Page 123: Rcc Ahb3 Peripheral Clock Enable In Low Power Mode Register (Rcc_Ahb3Lpenr)
RM0033 Reset and clock control (RCC) Bit 5 HASHLPEN: Hash modules clock enable during Sleep mode Set and cleared by software. 0: Hash modules clock disabled during Sleep mode 1: Hash modules clock enabled during Sleep mode Bit 4 CRYPLPEN: Cryptography modules clock enable during Sleep mode Set and cleared by software.
Page 124: Rcc Apb1 Peripheral Clock Enable In Low Power Mode Register (Rcc_Apb1Lpenr)
Reset and clock control (RCC) RM0033 5.3.18 RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR) Address offset: 0x60 Reset value: 0x36FE C9FF Access: no wait state, word, half-word and byte access. USART CAN2 CAN1 I2C3 I2C2 I2C1 UART5 UART4 USART2...
Page 125 RM0033 Reset and clock control (RCC) Bit 21 I2C1LPEN: I2C1 clock enable during Sleep mode Set and cleared by software. 0: I2C1 clock disabled during Sleep mode 1: I2C1 clock enabled during Sleep mode Bit 20 UART5LPEN: UART5 clock enable during Sleep mode Set and cleared by software.
Page 126 Reset and clock control (RCC) RM0033 Bit 6 TIM12LPEN: TIM12 clock enable during Sleep mode Set and cleared by software. 0: TIM12 clock disabled during Sleep mode 1: TIM12 clock enabled during Sleep mode Bit 5 TIM7LPEN: TIM7 clock enable during Sleep mode Set and cleared by software.
Page 127: Rcc Apb2 Peripheral Clock Enabled In Low Power Mode Register (Rcc_Apb2Lpenr)
RM0033 Reset and clock control (RCC) 5.3.19 RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR) Address offset: 0x64 Reset value: 0x0007 5F33 Access: no wait state, word, half-word and byte access. TIM11 TIM10 TIM9 LPEN LPEN LPEN Reserved SYSC USART...
Page 128 Reset and clock control (RCC) RM0033 Bit 10 ADC3LPEN: ADC 3 clock enable during Sleep mode Set and cleared by software. 0: ADC 3 clock disabled during Sleep mode 1: ADC 3 clock disabled during Sleep mode Bit 9 ADC2LPEN: ADC2 clock enable during Sleep mode Set and cleared by software.
Page 129: Rcc Backup Domain Control Register (Rcc_Bdcr)
RM0033 Reset and clock control (RCC) 5.3.20 RCC Backup domain control register (RCC_BDCR) Address offset: 0x70 Reset value: 0x0000 0000, reset by Backup domain reset. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register. The LSEON, LSEBYP, RTCSEL and RTCEN bits in the RCC Backup domain control register (RCC_BDCR)
Page 130: Rcc Clock Control & Status Register (Rcc_Csr)
Reset and clock control (RCC) RM0033 Bit 1 LSERDY: External low-speed oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles.
Page 131 RM0033 Reset and clock control (RCC) Bit 27 PORRSTF: POR/PDR reset flag Set by hardware when a POR/PDR reset occurs. Cleared by writing to the RMVF bit. 0: No POR/PDR reset occurred 1: POR/PDR reset occurred Bit 26 PINRSTF: PIN reset flag Set by hardware when a reset from the NRST pin occurs.
Page 132: Rcc Spread Spectrum Clock Generation Register (Rcc_Sscgr)
Reset and clock control (RCC) RM0033 5.3.22 RCC spread spectrum clock generation register (RCC_SSCGR) Address offset: 0x80 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. The spread spectrum clock generation is available only for the main PLL. The RCC_SSCGR register must be written either before the main PLL is enabled or after the main PLL disabled.
Page 133: Rcc Plli2S Configuration Register (Rcc_Plli2Scfgr)
RM0033 Reset and clock control (RCC) 5.3.23 RCC PLLI2S configuration register (RCC_PLLI2SCFGR) Address offset: 0x84 Reset value: 0x2000 3000 Access: no wait state, word, half-word and byte access. This register is used to configure the PLLI2S clock outputs according to the formulas: •...
Page 134 Reset and clock control (RCC) RM0033 Bits 27:15 Reserved, always read as 0. Bits 14:6 PLLI2SN: PLLI2S multiplication factor for VCO Set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when the PLLI2S is disabled. Only half-word and word accesses are allowed to write these bits.
Page 135: Rcc Register Map
RM0033 Reset and clock control (RCC) 5.3.24 RCC register map Table 13 gives the register map and reset values. Table 13. RCC register map and reset values Addr. Register offset name 0x00 RCC_CR Reserved Reserved RCC_PLLC 0x04 Reserved Reserved 0x08 RCC_CFGR 0x0C RCC_CIR...
Page 136 Reset and clock control (RCC) RM0033 Table 13. RCC register map and reset values (continued) Addr. Register offset name RCC_AHB2 0x34 Reserved RCC_AHB3 0x38 Reserved 0x3C Reserved Reserved RCC_APB1 0x40 RCC_APB2 0x44 Reserved 0x48 Reserved Reserved 0x4C Reserved Reserved RCC_AHB1 0x50 LPENR RCC_AHB2...
Page 137 RM0033 Reset and clock control (RCC) Table 13. RCC register map and reset values (continued) Addr. Register offset name 0x74 RCC_CSR Reserved 0x78 Reserved Reserved 0x7C Reserved Reserved RCC_SSCG 0x80 INCSTEP MODPER PLLI2S RCC_PLLI2 0x84 PLLI2SNx Reserved Reserved SCFGR Refer to Section 2.3 on page 51 for the register boundary addresses.
Page 138: General-Purpose I/Os (Gpio)
General-purpose I/Os (GPIO) RM0033 General-purpose I/Os (GPIO) This section applies to the whole STM32F20x and STM32F21x family, unless otherwise specified. GPIO introduction Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection register (GPIOx_AFRH and GPIOx_AFRL).
Page 139: Table 14. Port Bit Configuration Table
RM0033 General-purpose I/Os (GPIO) Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR register is to allow atomic read/modify accesses to any of the GPIO registers. In this way, there is no risk of an IRQ occurring between the read and the modify access.
Page 140: General-Purpose I/O (Gpio)
General-purpose I/Os (GPIO) RM0033 Table 14. Port bit configuration table (continued) MODER(i) OSPEEDR(i) PUPDR(i) OTYPER(i) I/O configuration [1:0] [B:A] [1:0] PP + PU PP + PD Reserved SPEED [B:A] OD + PU OD + PD Reserved Input Floating Input Input Reserved (input floating) Input/output Analog...
Page 141: I/O Pin Multiplexer And Mapping
RM0033 General-purpose I/Os (GPIO) 6.3.2 I/O pin multiplexer and mapping The microcontroller I/O pins are connected to onboard peripherals/modules through a multiplexer that allows only one peripheral’s alternate function (AF) connected to an I/O pin at a time. In this way, there can be no conflict between peripherals sharing the same I/O pin. Each I/O pin has a multiplexer with sixteen alternate function inputs (AF0 to AF15) that can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to 15) registers:...
Page 142: Table 15. Flexible Swj-Dp Pin Assignment
General-purpose I/Os (GPIO) RM0033 Table 15. Flexible SWJ-DP pin assignment SWJ I/O pin assigned PA13 / PA14 / Available debug ports PA15 / PB3 / PB4/ JTMS/ JTCK/ JTDI JTDO NJTRST SWDIO SWCLK Full SWJ (JTAG-DP + SW-DP) - Reset state Full SWJ (JTAG-DP + SW-DP) but without NJTRST JTAG-DP Disabled and SW-DP Enabled...
Page 143: Figure 14. Selecting An Alternate Function
RM0033 General-purpose I/Os (GPIO) Figure 14. Selecting an alternate function For pins 0 to 7, the GPIOx_AFRL[31:0] register selects the dedicated alternate function AF0 (system) AF1 (TIM1/TIM2) AF2 (TIM3..5) AF3 (TIM8..11) AF4 (I2C1..3) AF5 (SPI1/SPI2) AF6 (SPI3) Pin x (x = 0..7) AF7 (USART1..3) AF8 (USART4..6) AF9 (CAN1/CAN2, TIM12..14)
Page 144: I/O Port Control Registers
General-purpose I/Os (GPIO) RM0033 6.3.3 I/O port control registers Each of the GPIOs has four 32-bit memory-mapped control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The GPIOx_MODER register is used to select the I/O direction (input, output, AF, analog). The GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (push-pull or open-drain) and speed (the I/O speed pins are directly connected to the corresponding GPIOx_OSPEEDR register bits whatever the I/O direction).
Page 145: I/O Alternate Function Input/Output
RM0033 General-purpose I/Os (GPIO) The LOCK sequence (refer to Section 6.4.8: GPIO port configuration lock register (GPIOx_LCKR) (x = A..I)) can only be performed using a word (32-bit long) access to the GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same time as the [15:0] bits.
Page 146: Output Configuration
General-purpose I/Os (GPIO) RM0033 Figure 15. Input floating/pull up/pull down configurations Read V DD V DD on/off TTL Schmitt protection trigger diode pull Write input driver I/O pin on/off output driver protection pull diode down V SS V SS Read/write ai15940b 6.3.10 Output configuration...
Page 147: Alternate Function Configuration
RM0033 General-purpose I/Os (GPIO) Figure 16. Output configuration Read TTL Schmitt trigger on/off protection Write diode Input driver pull I/O pin Output driver on/off P-MOS protection pull down diode Output control Read/write N-MOS Push-pull or Open-drain ai15941b 6.3.11 Alternate function configuration When the I/O port is programmed as alternate function: •...
Page 148: Analog Configuration
General-purpose I/Os (GPIO) RM0033 6.3.12 Analog configuration When the I/O port is programmed as analog configuration: • The output buffer is disabled • The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0). •...
Page 149: Selection Of Rtc_Af1 And Rtc_Af2 Alternate Functions
RM0033 General-purpose I/Os (GPIO) 6.3.15 Selection of RTC_AF1 and RTC_AF2 alternate functions The STM32F4xx feature two GPIO pins RTC_AF1 and RTC_AF2 that can be used for the detection of a tamper or time stamp event, or AFO_ALARM, or AFO_CALIB RTC outputs. •...
Page 150 General-purpose I/Os (GPIO) RM0033 Table 17. RTC_AF2 pin TSINSEL Time TAMP1INSEL ALARMOUTTYPE Tamper TIMESTAMP Pin configuration and function stamp TAMPER1 AFO_ALARM enabled enabled pin selection configuration selection TAMPER1 input floating Don’t care Don’t care TIMESTAMP and TAMPER1 input Don’t care floating TIMESTAMP input floating Don’t care...
Page 151: Gpio Registers
RM0033 General-purpose I/Os (GPIO) GPIO registers This section gives a detailed description of the GPIO registers. For a summary of register bits, register address offsets and reset values, refer to Table The GPIO registers can be accessed by byte (8 bits), half-words (16 bits) or words (32 bits). 6.4.1 GPIO port mode register (GPIOx_MODER) (x = A..I) Address offset: 0x00...
Page 152: Gpio Port Output Speed Register (Gpiox_Ospeedr)
General-purpose I/Os (GPIO) RM0033 6.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..I) Address offset: 0x08 Reset values: • 0x0000 00C0 for port B • 0x0000 0000 for other ports OSPEEDR15 OSPEEDR14 OSPEEDR13 OSPEEDR12 OSPEEDR11 OSPEEDR10 OSPEEDR9 OSPEEDR8 [1:0] [1:0] [1:0] [1:0]...
Page 153: Gpio Port Input Data Register (Gpiox_Idr) (X = A
RM0033 General-purpose I/Os (GPIO) 6.4.5 GPIO port input data register (GPIOx_IDR) (x = A..I) Address offset: 0x10 Reset value: 0x0000 XXXX (where X means undefined) Reserved IDR15 IDR14 IDR13 IDR12 IDR11 IDR10 IDR9 IDR8 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0 Bits 31:16 Reserved, must be kept at reset value.
Page 154: Gpio Port Configuration Lock Register (Gpiox_Lckr)
General-purpose I/Os (GPIO) RM0033 Bits 31:16 BRy: Port x reset bit y (y = 0..15) These bits are write-only and can be accessed in word, half-word or byte mode. A read to these bits returns the value 0x0000. 0: No action on the corresponding ODRx bit 1: Resets the corresponding ODRx bit Note: If both BSx and BRx are set, BSx has priority.
Page 155: Gpio Alternate Function Low Register (Gpiox_Afrl) (X = A
RM0033 General-purpose I/Os (GPIO) Bits 31:17 Reserved, must be kept at reset value. Bit 16 LCKK[16]: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. 0: Port configuration lock key not active 1: Port configuration lock key active.
Page 156: (X = A
General-purpose I/Os (GPIO) RM0033 6.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A..I) Address offset: 0x24 Reset value: 0x0000 0000 AFRH15[3:0] AFRH14[3:0] AFRH13[3:0] AFRH12[3:0] AFRH11[3:0] AFRH10[3:0] AFRH9[3:0] AFRH8[3:0] Bits 31:0 AFRHy: Alternate function selection for port x bit y (y = 8..15) These bits are written by software to configure alternate function I/Os AFRHy selection: 0000: AF0...
Page 157: Gpio Register Map
RM0033 General-purpose I/Os (GPIO) 6.4.11 GPIO register map The following table gives the GPIO register map and the reset values. Table 18. GPIO register map and reset values Offset Register GPIOA_ MODER 0x00 Reset value GPIOB_ MODER 0x00 Reset value GPIOx_MODER (where x = C..I) 0x00...
Page 158 General-purpose I/Os (GPIO) RM0033 Table 18. GPIO register map and reset values (continued) Offset Register GPIOx_PUPDR (where x = C.. 0x0C Reset value GPIOx_IDR (where x = A..I) 0x10 Reserved Reset value GPIOx_ODR (where x = A..I) 0x14 Reserved Reset value GPIOx_BSRR (where x = A..I) 0x18...
Page 159: System Configuration Controller (Syscfg)
RM0033 System configuration controller (SYSCFG) System configuration controller (SYSCFG) The system configuration controller is mainly used to remap the memory accessible in the code area, select the Ethernet PHY interface and manage the external interrupt line connection to the GPIOs. I/O compensation cell By default the I/O compensation cell is not used.
Page 160: Syscfg Peripheral Mode Configuration Register (Syscfg_Pmc)
System configuration controller (SYSCFG) RM0033 Bits 31:2 Reserved Bits 1:0 MEM_MODE: Memory mapping selection Set and cleared by software. This bit controls the memory internal mapping at address 0x0000 0000. After reset these bits take on the memory mapping selected by the BOOT pins. 00: Main Flash memory mapped at 0x0000 0000 01: System Flash memory mapped at 0x0000 0000 10: FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000 0000...
Page 161: Syscfg External Interrupt Configuration Register 2
RM0033 System configuration controller (SYSCFG) Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 0 to 3) These bits are written by software to select the source input for the EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin 0011: PD[x] pin 0100: PE[x] pin...
Page 162: (Syscfg_Exticr4)
System configuration controller (SYSCFG) RM0033 Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 8 to 11) These bits are written by software to select the source input for the EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin 0011: PD[x] pin 0100: PE[x] pin...
Page 163: Syscfg Register Map
RM0033 System configuration controller (SYSCFG) Bits 31:9 Reserved Bit 8 READY: Compensation cell ready flag 0: I/O compensation cell not ready 1: O compensation cell ready Bits 7:2 Reserved Bit 0 CMP_PD: Compensation cell power-down 0: I/O compensation cell power-down mode 1: I/O compensation cell enabled 7.2.8 SYSCFG register map...
Page 164: Interrupts And Events
Interrupts and events RM0033 Interrupts and events This Section applies to the whole STM32F20x and STM32F21x family, unless otherwise specified. Nested vectored interrupt controller (NVIC) 8.1.1 NVIC features The nested vector interrupt controller NVIC includes the following features: ® • 81 maskable interrupt channels (not including the 16 interrupt lines of Cortex -M3) •...
Page 165 RM0033 Interrupts and events Table 20. Vector table (continued) Type of Acronym Description Address priority settable BusFault Pre-fetch fault, memory access fault 0x0000_0014 settable UsageFault Undefined instruction or illegal state 0x0000_0018 0x0000_001C - Reserved 0x0000_002B System service call via SWI settable SVCall 0x0000_002C...
Page 166 Interrupts and events RM0033 Table 20. Vector table (continued) Type of Acronym Description Address priority ADC1, ADC2 and ADC3 global settable 0x0000_0088 interrupts settable CAN1_TX CAN1 TX interrupts 0x0000_008C settable CAN1_RX0 CAN1 RX0 interrupts 0x0000_0090 settable CAN1_RX1 CAN1 RX1 interrupt 0x0000_0094 settable CAN1_SCE...
Page 167 RM0033 Interrupts and events Table 20. Vector table (continued) Type of Acronym Description Address priority TIM8 Update interrupt and TIM13 settable TIM8_UP_TIM13 0x0000_00F0 global interrupt TIM8_TRG_COM_ TIM8 Trigger and Commutation settable 0x0000_00F4 TIM14 interrupts and TIM14 global interrupt settable TIM8_CC TIM8 Capture Compare interrupt 0x0000_00F8 settable...
Page 168: External Interrupt/Event Controller (Exti)
Interrupts and events RM0033 Table 20. Vector table (continued) Type of Acronym Description Address priority settable USART6 USART6 global interrupt 0x0000_015C settable I2C3_EV C3 event interrupt 0x0000_0160 settable I2C3_ER C3 error interrupt 0x0000_0164 OTG_HS_EP1_OU USB On The Go HS End Point 1 settable 0x0000_0168 Out global interrupt...
Page 169: Exti Block Diagram
RM0033 Interrupts and events 8.2.2 EXTI block diagram Figure 19 shows the block diagram. Figure 19. External interrupt/event controller block diagram AMBA APB bus PCLK2 Peripheral interface Software Rising Falling Pending Interrupt interrupt trigger trigger request mask event selection selection register register Register...
Page 170 Interrupts and events RM0033 generated. The pending bit corresponding to the interrupt line is also set. This request is reset by writing a ‘1’ in the pending register. To generate the event, the event line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the event request by writing a ‘1’...
Page 171: External Interrupt/Event Line Mapping
RM0033 Interrupts and events 8.2.5 External interrupt/event line mapping The 140 GPIOs are connected to the 16 external interrupt/event lines in the following manner: Figure 20. External interrupt/event GPIO mapping EXTI0[3:0] bits in the SYSCFG_EXTICR1 register EXTI0 EXTI1[3:0] bits in the SYSCFG_EXTICR1 register EXTI1 EXTI15[3:0] bits in the SYSCFG_EXTICR4 register PA15...
Page 172: Exti Registers
Interrupts and events RM0033 registers EXTI Refer to Section 1.2 on page 46 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32 bits). 8.3.1 Interrupt mask register (EXTI_IMR) Address offset: 0x00 Reset value: 0x0000 0000 MR22 MR21...
Page 173: Rising Trigger Selection Register (Exti_Rtsr)
RM0033 Interrupts and events 8.3.3 Rising trigger selection register (EXTI_RTSR) Address offset: 0x08 Reset value: 0x0000 0000 TR22 TR21 TR20 TR19 TR18 TR17 TR16 Reserved TR15 TR14 TR13 TR12 TR11 TR10 Bits 31:23 Reserved, must be kept at reset value (0). Bits 22:0 TRx: Rising trigger event configuration bit of line x 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line...
Page 174: Software Interrupt Event Register (Exti_Swier)
Interrupts and events RM0033 8.3.5 Software interrupt event register (EXTI_SWIER) Address offset: 0x10 Reset value: 0x0000 0000 SWIER SWIER SWIER SWIER SWIER SWIER SWIER Reserved SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER Bits 31:23 Reserved, must be kept at reset value (0).
Page 175: Exti Register Map
RM0033 Interrupts and events 8.3.7 EXTI register map Table 21 gives the EXTI register map and the reset values. Table 21. External interrupt/event controller register map and reset values Offset Register EXTI_IMR MR[22:0] 0x00 Reserved Reset value EXTI_EMR MR[22:0] 0x04 Reserved Reset value EXTI_RTSR...
Page 176: Dma Controller (Dma)
DMA controller (DMA) RM0033 DMA controller (DMA) DMA introduction Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory and between memory and memory. Data can be quickly moved by DMA without any CPU action. This keeps CPU resources free for other operations. The DMA controller combines a powerful dual AHB master bus architecture with independent FIFO to optimize the bandwidth of the system, based on a complex bus matrix architecture.
Page 177 RM0033 DMA controller (DMA) FIFO to ensure an immediate data transfer as soon as a DMA request is triggered by a peripheral. • Each stream can be configured by hardware to be: – a regular channel that supports peripheral-to-memory, memory-to-peripheral and memory-to-memory transfers –...
Page 178: Dma Functional Description
DMA controller (DMA) RM0033 DMA functional description 9.3.1 General description Figure 21 shows the block diagram of a DMA. Figure 21. DMA block diagram DMA controller REQ_STR0_CH0 Memory port REQ_STR0_CH1 REQ_STR0_CH7 REQ_STR1_CH0 REQ_STR1_CH1 REQ_STREAM0 REQ_STREAM1 REQ_STR1_CH7 REQ_STREAM2 REQ_STREAM3 REQ_STREAM4 Arbiter REQ_STREAM5 REQ_STREAM6 REQ_STREAM7...
Page 179: Dma Transactions
RM0033 DMA controller (DMA) Figure 22 for the implementation of the system of two DMA controllers. Figure 22. System implementation of the two DMA controllers Bus matrix (AHB Flash multilayer) memory 112 KB SRAM 16 KB SRAM AHB1 peripherals DMA controller 2 AHB-APB APB2 APB2...
Page 180: Channel Selection
DMA controller (DMA) RM0033 After an event, the peripheral sends a request signal to the DMA controller. The DMA controller serves the request depending on the channel priorities. As soon as the DMA controller accesses the peripheral, an Acknowledge signal is sent to the peripheral by the DMA controller.
Page 181: Arbiter
RM0033 DMA controller (DMA) Table 23. DMA2 request mapping Peripheral Stream 0 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7 requests TIM8_CH1 TIM1_CH1 Channel 0 ADC1 TIM8_CH2 ADC1 TIM1_CH2 TIM8_CH3 TIM1_CH3 Channel 1 DCMI ADC2 ADC2 DCMI...
Page 182: Source, Destination And Transfer Modes
DMA controller (DMA) RM0033 AHB port. The register that contains the amount of data items to be transferred is decremented after each transaction. 9.3.6 Source, destination and transfer modes Both source and destination transfers can address peripherals and memories in the entire 4 GB area, at addresses comprised between 0x0000 0000 and 0xFFFF FFFF.
Page 183: Figure 24. Peripheral-To-Memory Mode
RM0033 DMA controller (DMA) Figure 24. Peripheral-to-memory mode DMA controller DMA_SxM0AR DMA_SxM1AR (1) AHB memory Memory bus port Memory destination FIFO Arbiter level REQ_STREAMx FIFO AHB peripheral Peripheral bus port Peripheral source DMA_SxPAR Peripheral DMA request MS47543V1 1. For double-buffer mode. Memory-to-peripheral mode Figure 25 describes this mode.
Page 184: Figure 25. Memory-To-Peripheral Mode
DMA controller (DMA) RM0033 Figure 25. Memory-to-peripheral mode DMA_SxM0AR DMA controller DMA_SxM1AR Memory bus AHB memory port Memory source FIFO Arbiter level REQ_STREAMx FIFO AHB peripheral Peripheral bus port Peripheral destination DMA_SxPAR Peripheral DMA request ai15949 1. For double-buffer mode. Memory-to-memory mode The DMA channels can also work without being triggered by a request from a peripheral.
Page 185: Pointer Incrementation
RM0033 DMA controller (DMA) Figure 26. Memory-to-memory mode DMA_SxM0AR DMA controller DMA_SxM1AR AHB memory Memory bus port Memory 2 destination Arbiter FIFO FIFO level FIFO Stream enable AHB peripheral Peripheral bus port Memory 1 source DMA_SxPAR ai15950 1. For double-buffer mode. 9.3.7 Pointer incrementation Peripheral and memory pointers can optionally be automatically post-incremented or kept...
Page 186: Circular Mode
DMA controller (DMA) RM0033 9.3.8 Circular mode The Circular mode is available to handle circular buffers and continuous data flows (e.g. ADC scan mode). This feature can be enabled using the CIRC bit in the DMA_SxCR register. When the circular mode is activated, the number of data items to be transferred is automatically reloaded with the initial value programmed during the stream configuration phase, and the DMA requests continue to be served.
Page 187: Programmable Data Width, Packing/Unpacking, Endianess
RM0033 DMA controller (DMA) memory 0 to 1 (or from 1 to 0) depending on the value of CT in the DMA_SxCR register in accordance with one of the two above conditions. For all the other modes (except the Double buffer mode), the memory address registers are write-protected as soon as the stream is enabled.
Page 188: Table 26. Packing/Unpacking & Endian Behavior (Bit Pinc = Minc = 1)
DMA controller (DMA) RM0033 Table 26. Packing/unpacking & endian behavior (bit PINC = MINC = 1) Number Peripheral port address / byte lane Peripher of data Memory Memory port memory peripheral items to transfer address / byte port transfer PINCOS = 1 PINCOS = 0 port width transfer...
Page 189: Single And Burst Transfers
RM0033 DMA controller (DMA) Table 27. Restriction on NDT versus PSIZE and MSIZE PSIZE[1:0] of DMA_SxCR MSIZE[1:0] of DMA_SxCR NDT[15:0] of DMA_SxNDTR 00 (8-bit) 01 (16-bit) must be a multiple of 2 00 (8-bit) 10 (32-bit) must be a multiple of 4 01 (16-bit) 10 (32-bit) must be a multiple of 2...
Page 190: Fifo
DMA controller (DMA) RM0033 9.3.12 FIFO FIFO structure The FIFO is used to temporarily store data coming from the source before transmitting them to the destination. Each stream has an independent 4-word FIFO and the threshold level is software- configurable between 1/4, 1/2, 3/4 or full. To enable the use of the FIFO threshold level, the direct mode must be disabled by setting the DMDIS bit in the DMA_SxFCR register.
Page 191: Table 28. Fifo Threshold Configurations
RM0033 DMA controller (DMA) FIFO threshold and burst configuration Caution is required when choosing the FIFO threshold (bits FTH[1:0] of the DMA_SxFCR register) and the size of the memory burst (MBURST[1:0] of the DMA_SxCR register): The content pointed by the FIFO threshold must exactly match to an integer number of memory burst transfers.
Page 192: Dma Transfer Completion
DMA controller (DMA) RM0033 FIFO flush The FIFO can be flushed when the stream is disabled by resetting the EN bit in the DMA_SxCR register and when the stream is configured to manage peripheral-to-memory or memory-to-memory transfers: If some data are still present in the FIFO when the stream is disabled, the DMA controller continues transferring the remaining data to the destination (even though stream is effectively disabled).
Page 193: Dma Transfer Suspension
RM0033 DMA controller (DMA) to-memory) all the remaining data have been flushed from the FIFO into the memory • In Peripheral flow controller mode: – The last external burst or single request has been generated from the peripheral and (when the DMA is operating in peripheral-to-memory mode) the remaining data have been transferred from the FIFO into the memory –...
Page 194: Flow Controller
DMA controller (DMA) RM0033 9.3.15 Flow controller The entity that controls the number of data to be transferred is known as the flow controller. This flow controller is configured independently for each stream using the PFCTRL bit in the DMA_SxCR register. The flow controller can be: •...
Page 195: Summary Of The Possible Dma Configurations
RM0033 DMA controller (DMA) 9.3.16 Summary of the possible DMA configurations Table 29 summarizes the different possible DMA configurations. Table 29. Possible DMA configurations DMA transfer Flow Circular Transfer Direct Double Source Destination mode controller mode type mode buffer mode single possible possible...
Page 196: Error Management
DMA controller (DMA) RM0033 Double buffer mode and interrupts after half and/or full transfer, and/or errors in the DMA_SxCR register. 10. Activate the stream by setting the EN bit in the DMA_SxCR register. As soon as the stream is enabled, it can serve any DMA request from the peripheral connected to the stream.
Page 197: Dma Interrupts
RM0033 DMA controller (DMA) If the DMEIFx or the FEIFx flag is set due to an overrun or underrun condition, the faulty stream is not automatically disabled and it is up to the software to disable or not the stream by resetting the EN bit in the DMA_SxCR register.
Page 198: Dma Registers
DMA controller (DMA) RM0033 DMA registers The DMA registers have to be accessed by words (32 bits). 9.5.1 DMA low interrupt status register (DMA_LISR) Address offset: 0x00 Reset value: 0x0000 0000 Reserved TCIF3 HTIF3 TEIF3 DMEIF3 Reserv FEIF3 TCIF2 HTIF2 TEIF2 DMEIF2 Reserv FEIF2...
Page 199: Dma High Interrupt Status Register (Dma_Hisr)
RM0033 DMA controller (DMA) 9.5.2 DMA high interrupt status register (DMA_HISR) Address offset: 0x04 Reset value: 0x0000 0000 TCIF7 HTIF7 TEIF7 DMEIF7 Reserv FEIF7 TCIF6 HTIF6 TEIF6 DMEIF6 Reserv FEIF6 Reserved TCIF5 HTIF5 TEIF5 DMEIF5 Reserv FEIF5 TCIF4 HTIF4 TEIF4 DMEIF4 Reserv FEIF4 Reserved...
Page 200: Dma Low Interrupt Flag Clear Register (Dma_Lifcr)
DMA controller (DMA) RM0033 9.5.3 DMA low interrupt flag clear register (DMA_LIFCR) Address offset: 0x08 Reset value: 0x0000 0000 CTCIF3 CHTIF3 CTEIF3 CDMEIF3 CFEIF3 CTCIF2 CHTIF2 CTEIF2 CDMEIF2 CFEIF2 Reserved Reserved Reserved CTCIF1 CHTIF1 CTEIF1 CDMEIF1 CFEIF1 CTCIF0 CHTIF0 CTEIF0 CDMEIF0 CFEIF0 Reserved Reserved...
Page 201: Dma Stream X Configuration Register (Dma_Sxcr) (X = 0
RM0033 DMA controller (DMA) Bits 24, 18, 8, 2 CDMEIFx: Stream x clear direct mode error interrupt flag (x = 7..4) Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_HISR register Bits 23, 17, 7, 1 Reserved, must be kept at reset value. Bits 22, 16, 6, 0 CFEIFx: Stream x clear FIFO error interrupt flag (x = 7..4) Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_HISR register 9.5.5...
Page 202 DMA controller (DMA) RM0033 Bit 19 CT: Current target (only in double buffer mode) This bits is set and cleared by hardware. It can also be written by software. 0: The current target memory is Memory 0 (addressed by the DMA_SxM0AR pointer) 1: The current target memory is Memory 1 (addressed by the DMA_SxM1AR pointer) This bit can be written only if EN is ‘0’...
Page 203 RM0033 DMA controller (DMA) Bit 9 PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral address pointer is fixed 1: Peripheral address pointer is incremented after each data transfer (increment is done according to PSIZE) This bit is protected and can be written only if EN is ‘0’.
Page 204: Dma Stream X Number Of Data Register (Dma_Sxndtr) (X = 0
DMA controller (DMA) RM0033 Bit 0 EN: Stream enable / flag stream ready when read low This bit is set and cleared by software. 0: Stream disabled 1: Stream enabled This bit may be cleared by hardware: – on a DMA end of transfer (stream ready to be configured) –...
Page 205: Dma Stream X Peripheral Address Register (Dma_Sxpar) (X = 0
RM0033 DMA controller (DMA) 9.5.7 DMA stream x peripheral address register (DMA_SxPAR) (x = 0..7) Address offset: 0x18 + 0x18 × stream number Reset value: 0x0000 0000 PAR[31:16] PAR[15:0] Bits 31:0 PAR[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. These bits are write-protected and can be written only when bit EN = '0' in the DMA_SxCR register.
Page 206: Dma Stream X Fifo Control Register (Dma_Sxfcr) (X = 0
DMA controller (DMA) RM0033 Bits 31:0 M1A[31:0]: Memory 1 address (used in case of Double buffer mode) Base address of Memory area 1 from/to which the data will be read/written. This register is used only for the Double buffer mode. These bits are write-protected.
Page 207 RM0033 DMA controller (DMA) Bits 5:3 FS[2:0]: FIFO status These bits are read-only. 000: 0 < fifo_level < 1/4 001: 1/4 ≤ fifo_level < 1/2 010: 1/2 ≤ fifo_level < 3/4 011: 3/4 ≤ fifo_level < full 100: FIFO is empty 101: FIFO is full others: no meaning These bits are not relevant in the direct mode (DMDIS bit is zero).
Page 208: Dma Register Map
DMA controller (DMA) RM0033 9.5.11 DMA register map Table 31 summarizes the DMA registers. Table 31. DMA register map and reset values Offset Register DMA_LISR 0x0000 Reserved Reserved Reset value DMA_HISR 0x0004 Reserved Reserved Reset value DMA_LIFCR 0x0008 Reserved Reserved Reset value DMA_HIFCR 0x000C...
Page 209 RM0033 DMA controller (DMA) Table 31. DMA register map and reset values (continued) Offset Register DMA_S1PAR PA[31:0] 0x0030 Reset value DMA_S1M0AR M0A[31:0] 0x0034 Reset value DMA_S1M1AR M1A[31:0] 0x0038 Reset value DMA_S1FCR FS[2:0] [1:0] 0x003C Reserved Reset value DMA_S2CR 0x0040 Reserved Reset value DMA_S2NDTR NDT[15:.]...
Page 210 DMA controller (DMA) RM0033 Table 31. DMA register map and reset values (continued) Offset Register DMA_S3M1AR M1A[31:0] 0x0068 Reset value DMA_S3FCR FS[2:0] [1:0] 0x006C Reserved Reset value DMA_S4CR 0x0070 Reserved Reset value DMA_S4NDTR NDT[15:.] 0x0074 Reserved Reset value DMA_S4PAR PA[31:0] 0x0078 Reset value DMA_S4M0AR...
Page 211 RM0033 DMA controller (DMA) Table 31. DMA register map and reset values (continued) Offset Register DMA_S6M0AR M0A[31:0] 0x00AC Reset value DMA_S6M1AR M1A[31:0] 0x00B0 Reset value DMA_S6FCR FS[2:0] [1:0] 0x00B4 Reserved Reset value DMA_S7CR 0x00B8 Reserved Reset value DMA_S7NDTR NDT[15:.] 0x00BC Reserved Reset value DMA_S7PAR...
Page 212: Analog-To-Digital Converter (Adc)
Analog-to-digital converter (ADC) RM0033 Analog-to-digital converter (ADC) This section applies to the whole STM32F20x and STM32F21x family, unless otherwise specified. 10.1 ADC introduction The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 19 multiplexed channels allowing it to measure signals from 16 external sources, two internal sources, and the V channel.
Page 213: Adc Functional Description
RM0033 Analog-to-digital converter (ADC) 10.3 ADC functional description Figure 28 shows a single ADC block diagram and Table 32 gives the ADC pin description. Figure 28. Single ADC block diagram Interrupt Flags enable bits DMA overrun OVRIE End of conversion EOCIE ADC Interrupt to NVIC End of injected conversion...
Page 214: Adc On-Off Control
Analog-to-digital converter (ADC) RM0033 Table 32. ADC pins Name Signal type Remarks Input, analog reference The higher/positive reference voltage for the ADC, REF+ ≤ ≤ positive 1.8 V REF+ Analog power supply equal to V ≤ ≤ Input, analog supply 2.4 V (3.6 V) for full speed ≤...
Page 215: Single Conversion Mode
RM0033 Analog-to-digital converter (ADC) The total number of conversions in the injected group must be written in the L[1:0] bits in the ADC_JSQR register. If the ADC_SQRx or ADC_JSQR registers are modified during a conversion, the current conversion is reset and a new start pulse is sent to the ADC to convert the newly chosen group.
Page 216: Timing Diagram
Analog-to-digital converter (ADC) RM0033 Note: Injected channels cannot be converted continuously. The only exception is when an injected channel is configured to be converted automatically after regular channels in continuous mode (using JAUTO bit), refer to Auto-injection section) 10.3.6 Timing diagram As shown in Figure 29, the ADC needs a stabilization time of t...
Page 217: Scan Mode
RM0033 Analog-to-digital converter (ADC) Table 33. Analog watchdog channel selection ADC_CR1 register control bits (x = don’t care) Channels guarded by the analog watchdog AWDSGL bit AWDEN bit JAWDEN bit None All injected channels All regular channels All regular and injected channels Single injected channel Single...
Page 218: Discontinuous Mode
Analog-to-digital converter (ADC) RM0033 interrupted but the regular sequence is executed at the end of the injected sequence. Figure 31 shows the corresponding timing diagram. Note: When using triggered injection, one must ensure that the interval between trigger events is longer than the injection sequence.
Page 219 RM0033 Analog-to-digital converter (ADC) Example: • n = 3, channels to be converted = 0, 1, 2, 3, 6, 7, 9, 10 • 1st trigger: sequence converted 0, 1, 2. An EOC event is generated at each conversion. • 2nd trigger: sequence converted 3, 6, 7. An EOC event is generated at each conversion •...
Page 220: Data Alignment
Analog-to-digital converter (ADC) RM0033 10.4 Data alignment The ALIGN bit in the ADC_CR2 register selects the alignment of the data stored after conversion. Data can be right- or left-aligned as shown in Figure 32 Figure The converted data value from the injected group of channels is decreased by the user- defined offset written in the ADC_JOFRx registers so the result can be a negative value.
Page 221: Channel-Wise Programmable Sampling Time
RM0033 Analog-to-digital converter (ADC) 10.5 Channel-wise programmable sampling time The ADC samples the input voltage for a number of ADCCLK cycles that can be modified using the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can be sampled with a different sampling time. The total conversion time is calculated as follows: = Sampling time + 12 cycles conv...
Page 222: Table 35. External Trigger For Regular Channels
Analog-to-digital converter (ADC) RM0033 Table 35. External trigger for regular channels Source Type EXTSEL[3:0] TIM1_CH1 event 0000 TIM1_CH2 event 0001 TIM1_CH3 event 0010 TIM2_CH2 event 0011 TIM2_CH3 event 0100 TIM2_CH4 event 0101 TIM2_TRGO event 0110 Internal signal from on-chip TIM3_CH1 event 0111 timers TIM3_TRGO event...
Page 223: Fast Conversion Mode
RM0033 Analog-to-digital converter (ADC) Table 36. External trigger for injected channels Source Connection type JEXTSEL[3:0] TIM1_CH4 event 0000 TIM1_TRGO event 0001 TIM2_CH1 event 0010 TIM2_TRGO event 0011 TIM3_CH2 event 0100 TIM3_CH4 event 0101 TIM4_CH1 event 0110 Internal signal from on-chip TIM4_CH2 event 0111 timers...
Page 224: Data Management
Analog-to-digital converter (ADC) RM0033 10.8 Data management 10.8.1 Using the DMA Since converted regular channel values are stored into a unique data register, it is useful to use DMA for conversion of more than one regular channel. This avoids the loss of the data already stored in the ADC_DR register.
Page 225: Conversions Without Dma And Without Overrun Detection
RM0033 Analog-to-digital converter (ADC) 10.8.3 Conversions without DMA and without overrun detection It may be useful to let the ADC convert one or more channels without reading the data each time (if there is an analog watchdog for instance). For that, the DMA must be disabled (DMA = 0) and the EOC bit must be set at the end of a sequence only (EOCS = 0).
Page 226: Figure 35. Multi Adc Block Diagram
Analog-to-digital converter (ADC) RM0033 Figure 35. Multi ADC block diagram Regular data register (12 bits) (16 bits) Injected data registers Regular (4 x 16 bits) channels ADC3 (Slave) Injected channels Regular data register (12 bits) (16 bits) Injected data registers Regular (4 x 16 bits) channels...
Page 227 RM0033 Analog-to-digital converter (ADC) • DMA requests in Multi ADC mode: In Multi ADC mode the DMA may be configured to transfer converted data in three different modes. In all cases, the DMA streams to use are those connected to the ADC: –...
Page 228: Injected Simultaneous Mode
Analog-to-digital converter (ADC) RM0033 representing two ADC converted data items are transferred as a half-word. The data transfer order is similar to that of the DMA mode 2. DMA mode 3 is used in interleaved mode in 6-bit and 8-bit resolutions (dual and triple mode).
Page 229: Regular Simultaneous Mode
RM0033 Analog-to-digital converter (ADC) Dual ADC mode At the end of conversion event on ADC1 or ADC2: • The converted data are stored into the ADC_JDRx registers of each ADC interface. • A JEOC interrupt is generated (if enabled on one of the two ADC interfaces) when the ADC1/ADC2’s injected channels have all been converted.
Page 230: Figure 38. Regular Simultaneous Mode On 16 Channels: Dual Adc Mode
Analog-to-digital converter (ADC) RM0033 Dual ADC mode At the end of conversion event on ADC1 or ADC2: • A 32-bit DMA transfer request is generated (if DMA[1:0] bits in the ADC_CCR register are equal to 0b10). This request transfers the ADC2 converted data stored in the upper half-word of the ADC_CDR 32-bit register to the SRAM and then the ADC1 converted data stored in the lower half-word of ADC_CCR to the SRAM.
Page 231: Interleaved Mode
RM0033 Analog-to-digital converter (ADC) 10.9.3 Interleaved mode This mode can be started only on a regular group (usually one channel). The external trigger source comes from the regular channel multiplexer of ADC1. Dual ADC mode After an external trigger occurs: •...
Page 232: Alternate Trigger Mode
Analog-to-digital converter (ADC) RM0033 a given time). In this case, the delay becomes the sampling time + 2 ADC clock cycles. For instance, if DELAY = 5 clock cycles and the sampling takes 15 clock cycles on the three ADCs, then 17 clock cycles will separate the conversions on ADC1, ADC2 and ADC3). If the CONT bit is set on ADC1, ADC2 and ADC3, the selected regular channels of all ADCs are continuously converted.
Page 233: Figure 42. Alternate Trigger: Injected Group Of Each Adc
RM0033 Analog-to-digital converter (ADC) ADC has to perform an injected conversion. It is resumed when the injected conversion is finished. If the conversion sequence is interrupted (for instance when DMA end of transfer occurs), the multi-ADC sequencer must be reset by configuring it in independent mode first (bits DUAL[4:0] = 00000) before reprogramming the interleaved mode.
Page 234: Combined Regular/Injected Simultaneous Mode
Analog-to-digital converter (ADC) RM0033 Figure 43. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode 1st trigger 3rd trigger 5th trigger 7th trigger Sampling JEOC on ADC1 Conversion ADC1 ADC2 JEOC on ADC2 2nd trigger 4th trigger 6th trigger 8th trigger ai16060 Triple ADC mode...
Page 235: Combined Regular Simultaneous + Alternate Trigger Mode
RM0033 Analog-to-digital converter (ADC) ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions. 10.9.6 Combined regular simultaneous + alternate trigger mode It is possible to interrupt the simultaneous conversion of a regular group to start the alternate trigger conversion of an injected group.
Page 236: Temperature Sensor
Analog-to-digital converter (ADC) RM0033 Figure 46. Case of trigger occurring during injected conversion 1st trigger 3rd trigger ADC1 reg ADC1 inj ADC2 reg ADC2 inj 2nd trigger 2nd trigger ai16063 10.10 Temperature sensor The temperature sensor can be used to measure the ambient temperature (T ) of the device.
Page 237: Figure 47. Temperature Sensor And Vrefint Channel Block Diagram
RM0033 Analog-to-digital converter (ADC) Figure 47. Temperature sensor and V channel block diagram REFINT TSVREFE control bit Temper ature SENSE sensor ADC1_IN16 converted data ADC1 REFINT Internal ADC1_IN17 power block ai16065 Reading the temperature To use the sensor: Select ADC1_IN16 input channel. Select a sampling time greater than the minimum sampling time specified in the datasheet.
Page 238: Battery Charge Monitoring
Analog-to-digital converter (ADC) RM0033 10.11 Battery charge monitoring The VBATE bit in the ADC_CCR register is used to switch to the battery voltage. As the voltage could be higher than V , to ensure the correct operation of the ADC, the pin is internally connected to a bridge divider by 2.
Page 239: Adc Registers
RM0033 Analog-to-digital converter (ADC) 10.13 ADC registers Refer to Section 1.1: List of abbreviations for registers for registers for a list of abbreviations used in register descriptions. The peripheral registers must be written at word level (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
Page 240: Adc Control Register 1 (Adc_Cr1)
Analog-to-digital converter (ADC) RM0033 10.13.2 ADC control register 1 (ADC_CR1) Address offset: 0x04 Reset value: 0x0000 0000 OVRIE AWDEN JAWDEN Reserved Reserved JDISCE DISC AWDSG DISCNUM[2:0] JAUTO SCAN JEOCIE AWDIE EOCIE AWDCH[4:0] Bits 31:27 Reserved, must be kept at reset value. Bit 26 OVRIE: Overrun interrupt enable This bit is set and cleared by software to enable/disable the Overrun interrupt.
Page 241 RM0033 Analog-to-digital converter (ADC) Bit 11 DISCEN: Discontinuous mode on regular channels This bit is set and cleared by software to enable/disable Discontinuous mode on regular channels. 0: Discontinuous mode on regular channels disabled 1: Discontinuous mode on regular channels enabled Bit 10 JAUTO: Automatic injected group conversion This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion.
Page 242: Adc Control Register 2 (Adc_Cr2)
Analog-to-digital converter (ADC) RM0033 10.13.3 ADC control register 2 (ADC_CR2) Address offset: 0x08 Reset value: 0x0000 0000 SWST JSWST EXTEN EXTSEL[3:0] JEXTEN JEXTSEL[3:0] reserved reserved ALIGN EOCS CONT ADON reserved Reserved Bit 31 Reserved, must be kept at reset value. Bit 30 SWSTART: Start conversion of regular channels This bit is set by software to start conversion and cleared by hardware as soon as the conversion starts.
Page 243 RM0033 Analog-to-digital converter (ADC) Bit 22 JSWSTART: Start conversion of injected channels This bit is set by software and cleared by hardware as soon as the conversion starts. 0: Reset state 1: Starts conversion of injected channels Note: This bit can be set only when ADON = 1 otherwise no conversion is launched. Bits 21:20 JEXTEN: External trigger enable for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group.
Page 244: Adc Sample Time Register 1 (Adc_Smpr1)
Analog-to-digital converter (ADC) RM0033 Bits 7:2 Reserved, must be kept at reset value. Bit 1 CONT: Continuous conversion This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. 0: Single conversion mode 1: Continuous conversion mode Bit 0 ADON: A/D Converter ON / OFF This bit is set and cleared by software.
Page 245: Adc Injected Channel Data Offset Register X (Adc_Jofrx) (X=1
RM0033 Analog-to-digital converter (ADC) Bits 31:30 Reserved, must be kept at reset value. Bits 29:0 SMPx[2:0]: Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: 000: 3 cycles 001: 15 cycles 010: 28 cycles...
Page 246: Adc Watchdog Lower Threshold Register (Adc_Ltr)
Analog-to-digital converter (ADC) RM0033 Note: The software can write to these registers when an ADC conversion is ongoing. The programmed value will be effective when the next conversion is complete. Writing to this register is performed with a write delay that can create uncertainty on the effective time at which the new value is programmed.
Page 247: Adc Regular Sequence Register 2 (Adc_Sqr2)
RM0033 Analog-to-digital converter (ADC) Bits 14:10 SQ15[4:0]: 15th conversion in regular sequence Bits 9:5 SQ14[4:0]: 14th conversion in regular sequence Bits 4:0 SQ13[4:0]: 13th conversion in regular sequence 10.13.10 ADC regular sequence register 2 (ADC_SQR2) Address offset: 0x30 Reset value: 0x0000 0000 SQ12[4:0] SQ11[4:0] SQ10[4:1]...
Page 248: Adc Injected Sequence Register (Adc_Jsqr)
Analog-to-digital converter (ADC) RM0033 Bits 19:15 SQ4[4:0]: 4th conversion in regular sequence Bits 14:10 SQ3[4:0]: 3rd conversion in regular sequence Bits 9:5 SQ2[4:0]: 2nd conversion in regular sequence Bits 4:0 SQ1[4:0]: 1st conversion in regular sequence 10.13.12 ADC injected sequence register (ADC_JSQR) Address offset: 0x38 Reset value: 0x0000 0000 JL[1:0]...
Page 249: Adc Injected Data Register X (Adc_Jdrx) (X= 1
RM0033 Analog-to-digital converter (ADC) 10.13.13 ADC injected data register x (ADC_JDRx) (x= 1..4) Address offset: 0x3C - 0x48 Reset value: 0x0000 0000 Reserved JDATA[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 JDATA[15:0]: Injected data These bits are read-only. They contain the conversion result from injected channel x. The data are left -or right-aligned as shown in Figure 32 Figure...
Page 250: Adc Common Status Register (Adc_Csr)
Analog-to-digital converter (ADC) RM0033 10.13.15 ADC Common status register (ADC_CSR) Address offset: 0x00 (this offset address is relative to ADC1 base address + 0x300) Reset value: 0x0000 0000 This register provides an image of the status bits of the different ADCs. Nevertheless it is read-only and does not allow to clear the different status bits.
Page 251 RM0033 Analog-to-digital converter (ADC) Bits 31:24 Reserved, must be kept at reset value. Bit 23 TSVREFE: Temperature sensor and V enable REFINT This bit is set and cleared by software to enable/disable the temperature sensor and the channel. REFINT 0: Temperature sensor and V channel disabled REFINT 1: Temperature sensor and V...
Page 252 Analog-to-digital converter (ADC) RM0033 Bit 11:8 DELAY: Delay between 2 sampling phases Set and cleared by software. These bits are used in dual or triple interleaved modes. 0000: 5 * T ADCCLK 0001: 6 * T ADCCLK 0010: 7 * T ADCCLK 1111: 20 * T ADCCLK...
Page 253: 10.13.17 Adc Common Regular Data Register For Dual And Triple Modes
RM0033 Analog-to-digital converter (ADC) 10.13.17 ADC common regular data register for dual and triple modes (ADC_CDR) Address offset: 0x08 (this offset address is relative to ADC1 base address + 0x300) Reset value: 0x0000 0000 DATA2[15:0] DATA1[15:0] Bits 31:16 DATA2[15:0]: 2nd data item of a pair of regular conversions –...
Page 254: Table 39. Adc Register Map And Reset Values For Each Adc
Analog-to-digital converter (ADC) RM0033 Table 39. ADC register map and reset values for each ADC Offset Register ADC_SR 0x00 Reserved Reset value DISC ADC_CR1 AWDCH[4:0] NUM [2:0] 0x04 Reserved Reserved Reset value JEXTSEL ADC_CR2 EXTSEL [3:0] [3:0] 0x08 Reserved Reserved Reset value ADC_SMPR1 Sample time bits SMPx_x...
Page 255: Table 40. Adc Register Map And Reset Values (Common Adc Registers)
RM0033 Analog-to-digital converter (ADC) Table 40. ADC register map and reset values (common ADC registers) Offset Register ADC_CSR 0x00 Reserved Reset value ADC3 ADC2 ADC1 ADC_CCR DELAY [3:0] MULTI [4:0] 0x04 Reserved Reserved Reserved Reset value ADC_CDR Regular DATA2[15:0] Regular DATA1[15:0] 0x08 Reset value Refer to...
Page 256: Digital-To-Analog Converter (Dac)
Digital-to-analog converter (DAC) RM0033 Digital-to-analog converter (DAC) This section applies to the whole STM32F20x and STM32F21x family, unless otherwise specified. 11.1 DAC introduction The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned.
Page 257: Table 41. Dac Pins
RM0033 Digital-to-analog converter (DAC) Figure 48. DAC channel block diagram DAC control register TSELx[2:0] bits SWTR IGx TIM2_T RGO DMAENx TIM4_T RGO TIM5_T RGO TIM6_T RGO TIM7_T RGO TIM8_T RGO EXTI_9 DM A req ue stx Control logicx TENx 12-bit DHRx MAMPx[3:0] bits trianglex...
Page 258: Dac Functional Description
Digital-to-analog converter (DAC) RM0033 11.3 DAC functional description 11.3.1 DAC channel enable Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR register. The DAC channel is then enabled after a startup time t WAKEUP Note: The ENx bit enables the analog DAC Channelx macrocell only.
Page 259: Dac Conversion
RM0033 Digital-to-analog converter (DAC) Figure 49. Data registers in single DAC channel mode 8-bit right aligned 12-bit left aligned 12-bit right aligned ai14710b • Dual DAC channels, there are three possibilities: – 8-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR8RD [7:0] bits (stored into the DHR1[11:4] bits) and data for DAC channel2 to be loaded into the DAC_DHR8RD [15:8] bits (stored into the DHR2[11:4] bits) –...
Page 260: Dac Output Voltage
Digital-to-analog converter (DAC) RM0033 When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage becomes available after a time t that depends on the power supply voltage and the SETTLING analog output load. Figure 51. Timing diagram for conversion with trigger disabled TEN = 0 APB1_CLK 0x1AC Output voltage...
Page 261: Dma Request
RM0033 Digital-to-analog converter (DAC) If the software trigger is selected, the conversion starts once the SWTRIG bit is set. SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the DAC_DHRx register contents. Note: TSELx[2:0] bit cannot be changed when the ENx bit is set. When software trigger is selected, the transfer from the DAC_DHRx register to the DAC_DORx register takes only one APB1 clock cycle.
Page 262: Triangle-Wave Generation
Digital-to-analog converter (DAC) RM0033 Figure 52. DAC LFSR register calculation algorithm ai14713c The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this value is then stored into the DAC_DORx register.
Page 263: Dual Dac Channel Conversion
RM0033 Digital-to-analog converter (DAC) It is possible to reset triangle wave generation by resetting the WAVEx[1:0] bits. Figure 54. DAC triangle wave generation MAMPx[3:0] max amplitude + DAC_DHRx base value DAC_DHRx base value ai14715c Figure 55. DAC conversion (SW trigger enabled) with triangle wave generation APB1_CLK 0x00 0xAAA...
Page 264: Independent Trigger Without Wave Generation
Digital-to-analog converter (DAC) RM0033 11.4.1 Independent trigger without wave generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits •...
Page 265: Independent Trigger With Single Triangle Generation
RM0033 Digital-to-analog converter (DAC) 11.4.4 Independent trigger with single triangle generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits •...
Page 266: Simultaneous Trigger Without Wave Generation
Digital-to-analog converter (DAC) RM0033 11.4.7 Simultaneous trigger without wave generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits •...
Page 267: Simultaneous Trigger With Single Triangle Generation
RM0033 Digital-to-analog converter (DAC) 11.4.10 Simultaneous trigger with single triangle generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits •...
Page 268: Dac Registers
Digital-to-analog converter (DAC) RM0033 11.5 DAC registers Refer to Section 1.1: List of abbreviations for registers for registers for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32 bits). 11.5.1 DAC control register (DAC_CR) Address offset: 0x00 Reset value: 0x0000 0000 DMAU...
Page 269 RM0033 Digital-to-analog converter (DAC) Bits 21:19 TSEL2[2:0]: DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 000: Timer 6 TRGO event 001: Timer 8 TRGO event 010: Timer 7 TRGO event 011: Timer 5 TRGO event 100: Timer 2 TRGO event 101: Timer 4 TRGO event 110: External line9...
Page 270 Digital-to-analog converter (DAC) RM0033 Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1 0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15...
Page 271: Dac Software Trigger Register (Dac_Swtrigr)
RM0033 Digital-to-analog converter (DAC) 11.5.2 DAC software trigger register (DAC_SWTRIGR) Address offset: 0x04 Reset value: 0x0000 0000 Reserved SWTRIG2 SWTRIG1 Reserved Bits 31:2 Reserved, must be kept at reset value. Bit 1 SWTRIG2: DAC channel2 software trigger This bit is set and cleared by software to enable/disable the software trigger. 0: Software trigger disabled 1: Software trigger enabled Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2...
Page 272: Dac Channel1 12-Bit Left Aligned Data Holding Register
Digital-to-analog converter (DAC) RM0033 11.5.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) Address offset: 0x0C Reset value: 0x0000 0000 Reserved DACC1DHR[11:0] Reserved Bits 31:16 Reserved, must be kept at reset value. Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.
Page 273: Dac Channel2 12-Bit Left Aligned Data Holding Register
RM0033 Digital-to-analog converter (DAC) 11.5.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) Address offset: 0x14 Reset value: 0x0000 0000 Reserved DACC2DHR[11:0] Reserved Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.
Page 274: Dual Dac 12-Bit Right-Aligned Data Holding Register (Dac_Dhr12Rd)
Digital-to-analog converter (DAC) RM0033 11.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) Address offset: 0x20 Reset value: 0x0000 0000 DACC2DHR[11:0] Reserved DACC1DHR[11:0] Reserved Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.
Page 275: Dac Channel1 Data Output Register (Dac_Dor1)
RM0033 Digital-to-analog converter (DAC) 11.5.11 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) Address offset: 0x28 Reset value: 0x0000 0000 Reserved DACC2DHR[7:0] DACC1DHR[7:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.
Page 276: Dac Status Register (Dac_Sr)
Digital-to-analog converter (DAC) RM0033 11.5.14 DAC status register (DAC_SR) Address offset: 0x34 Reset value: 0x0000 0000 DMAUDR2 Reserved Reserved rc_w1 DMAUDR1 Reserved Reserved rc_w1 Bits 31:30 Reserved, must be kept at reset value. Bit 29 DMAUDR2: DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).
Page 277 RM0033 Digital-to-analog converter (DAC) Table 43. DAC register map (continued) Offset Register DAC_ 0x1C Reserved DACC2DHR[7:0] DHR8R2 DAC_ 0x20 Reserved DACC2DHR[11:0] Reserved DACC1DHR[11:0] DHR12RD DAC_ 0x24 DACC2DHR[11:0] Reserved DACC1DHR[11:0] Reserved DHR12LD DAC_ 0x28 Reserved DACC2DHR[7:0] DACC1DHR[7:0] DHR8RD DAC_ 0x2C Reserved DACC1DOR[11:0] DOR1 DAC_...
Page 278: Digital Camera Interface (Dcmi)
Digital camera interface (DCMI) RM0033 Digital camera interface (DCMI) This section applies to the whole STM32F20x and STM32F21x family, unless otherwise specified. 12.1 DCMI introduction The digital camera is a synchronous parallel interface able to receive a high-speed data flow from an external 8-, 10-, 12- or 14-bit CMOS camera module.
Page 279: Dcmi Functional Overview
RM0033 Digital camera interface (DCMI) camera are stable and can be sampled. The minimum PIXCLK period must be higher than 2.5 HCLK periods. 12.5 DCMI functional overview The digital camera interface is a synchronous parallel interface that can receive high-speed (up to 54 Mbytes/s) data flows.
Page 280: Dma Interface
Digital camera interface (DCMI) RM0033 Figure 57. Top-level block diagram DCMI_D[0:13] DCMI_PIXCLK External HCLK interface DCMI_HSYNC DCMI_VSYNC DCMI Interrupt DCMI_IT controller DMA_REQ ai15603b 12.5.1 DMA interface The DMA interface is active when the CAPTURE bit in the DCMI_CR register is set. A DMA request is generated each time the camera interface receives a complete 32-bit data block in its register.
Page 281: Table 46. Positioning Of Captured Data Bytes In 32-Bit Words (8-Bit Width)
RM0033 Digital camera interface (DCMI) Figure 58. DCMI signal waveforms DCMI_PIXCLK DCMI_HSYNC DCMI_VSYNC ai15606b 1. The capture edge of DCMI_PIXCLK is the falling edge, the active state of DCMI_HSYNC and DCMI_VSYNC is 1. 1. DCMI_HSYNC and DCMI_VSYNC can change states at the same time. 8-bit data When EDM[1:0] in DCMI_CR are programmed to “00”...
Page 282: Synchronization
Digital camera interface (DCMI) RM0033 12-bit data When EDM[1:0] in DCMI_CR are programmed to “10”, the camera interface captures the 12-bit data at its input D[0..11] and stores them as the 12 least significant bits of a 16-bit word. The remaining most significant bits are cleared to zero. So, in this case a 32-bit data word is made up every two pixel clock cycles.
Page 283: Figure 59. Timing Diagram
RM0033 Digital camera interface (DCMI) Figure 59. Timing diagram Padding data at the end of the JPEG stream Beginning of JPEG stream Programmable JPEG packet size JPEG data End of JPEG stream DCMI_HSYNC DCMI_VSYNC Packet dispatching depends on the image content. This results in a variable blanking duration.
Page 284 Digital camera interface (DCMI) RM0033 Hardware synchronization mode In hardware synchronisation mode, the two synchronization signals (HSYNC/VSYNC) are used. Depending on the camera module/mode, data may be transmitted during horizontal/vertical synchronisation periods. The HSYNC/VSYNC signals act like blanking signals since all the data received during HSYNC/VSYNC active periods are ignored.
Page 285: Capture Modes
RM0033 Digital camera interface (DCMI) This mode can be supported by programming the following codes: • FS ≤ 0xFF • FE ≤ 0xFF • LS ≤ SAV (active) • LE ≤ EAV (active) An embedded unmask code is also implemented for frame/line start and frame/line end codes.
Page 286: Crop Feature
Digital camera interface (DCMI) RM0033 Continuous grab mode In this mode (CM bit = ‘0’ in DCMI_CR), once the CAPTURE bit has been set in DCMI_CR, the grabbing process starts on the next VSYNC or embedded frame start depending on the mode.
Page 287: Figure 62. Coordinates And Size Of The Window After Cropping
RM0033 Digital camera interface (DCMI) Figure 62. Coordinates and size of the window after cropping VST bit in DCMI_CSTRT VLINE bit in DCMI_CSIZE HOFFCNT bit in DCMI_CSTRT CAPCNT bit in DCMI_CSIZE ai15834 These registers specify the coordinates of the starting point of the capture window as a line number (in the frame, starting from 0) and a number of pixel clocks (on the line, starting from 0), and the size of the window as a line number and a number of pixel clocks.
Page 288: Jpeg Format
Digital camera interface (DCMI) RM0033 12.5.6 JPEG format To allow JPEG image reception, it is necessary to set the JPEG bit in the DCMI_CR register. JPEG images are not stored as lines and frames, so the VSYNC signal is used to start the capture while HSYNC serves as a data enable signal.
Page 289: Monochrome Format
RM0033 Digital camera interface (DCMI) 12.6.2 Monochrome format Characteristics: • Raster format • 8 bits per pixel Table 50 shows how the data are stored. Table 50. Data storage in monochrome progressive video format Byte address 31:24 23:16 15:8 n + 3 n + 2 n + 1 n + 7...
Page 290: Dcmi Interrupts
Digital camera interface (DCMI) RM0033 Table 52. Data storage in YCbCr progressive video format Byte address 31:24 23:16 15:8 Y n + 1 Cr n Cb n Y n + 3 Cr n + 2 Y n + 2 Cb n + 2 12.7 DCMI interrupts Five interrupts are generated.
Page 291 RM0033 Digital camera interface (DCMI) Bits 11:10 EDM[1:0]: Extended data mode 00: Interface captures 8-bit data on every pixel clock 01: Interface captures 10-bit data on every pixel clock 10: Interface captures 12-bit data on every pixel clock 11: Interface captures 14-bit data on every pixel clock Bits 9:8 FCRC[1:0]: Frame capture rate control These bits define the frequency of frame capture.
Page 292 Digital camera interface (DCMI) RM0033 Bit 1 CM: Capture mode 0: Continuous grab mode - The received data are transferred into the destination memory through the DMA. The buffer location and mode (linear or circular buffer) is controlled through the system DMA. 1: Snapshot mode (single frame) - Once activated, the interface waits for the start of frame and then transfers a single frame through the DMA.
Page 293: Dcmi Status Register (Dcmi_Sr)
RM0033 Digital camera interface (DCMI) 12.8.2 DCMI status register (DCMI_SR) Address offset: 0x04 Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved Bits 31:3 Reserved, must be kept at reset value.
Page 294: Dcmi Raw Interrupt Status Register (Dcmi_Ris)
Digital camera interface (DCMI) RM0033 12.8.3 DCMI raw interrupt status register (DCMI_RIS) Address offset: 0x08 Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DCMI_RIS gives the raw interrupt status and is accessible in read only.
Page 295: Dcmi Interrupt Enable Register (Dcmi_Ier)
RM0033 Digital camera interface (DCMI) 12.8.4 DCMI interrupt enable register (DCMI_IER) Address offset: 0x0C Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved rw rw rw rw rw The DCMI_IER register is used to enable interrupts.
Page 296: Dcmi Masked Interrupt Status Register (Dcmi_Mis)
Digital camera interface (DCMI) RM0033 12.8.5 DCMI masked interrupt status register (DCMI_MIS) This DCMI_MIS register is a read-only register. When read, it returns the current masked status value (depending on the value in DCMI_IER) of the corresponding interrupt. A bit in this register is set if the corresponding enable bit in DCMI_IER is set and the corresponding bit in DCMI_RIS is set.
Page 297: Dcmi Interrupt Clear Register (Dcmi_Icr)
RM0033 Digital camera interface (DCMI) 12.8.6 DCMI interrupt clear register (DCMI_ICR) Address offset: 0x14 Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved w w w w w The DCMI_ICR register is write-only.
Page 298: Dcmi Embedded Synchronization Code Register (Dcmi_Escr)
Digital camera interface (DCMI) RM0033 12.8.7 DCMI embedded synchronization code register (DCMI_ESCR) Address offset: 0x18 Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:24 FEC: Frame end delimiter code This byte specifies the code of the frame end delimiter.
Page 299: Dcmi Embedded Synchronization Unmask Register (Dcmi_Esur)
RM0033 Digital camera interface (DCMI) 12.8.8 DCMI embedded synchronization unmask register (DCMI_ESUR) Address offset: 0x1C Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:24 FEU: Frame end delimiter unmask This byte specifies the mask to be applied to the code of the frame end delimiter.
Page 300: Dcmi Crop Window Start (Dcmi_Cwstrt)
Digital camera interface (DCMI) RM0033 12.8.9 DCMI crop window start (DCMI_CWSTRT) Address offset: 0x20 Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 VST[12:0 HOFFCNT[13:0] Reserv...
Page 301: Dcmi Data Register (Dcmi_Dr)
RM0033 Digital camera interface (DCMI) 12.8.11 DCMI data register (DCMI_DR) Address offset: 0x28 Reset value: 0x0000 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Byte3 Byte2 Byte1 Byte0...
Page 302 Digital camera interface (DCMI) RM0033 Table 54. DCMI register map and reset values (continued) Offset Register DCMI_ICR 0x14 Reserved Reset value DCMI_ESCR 0x18 Reset value DCMI_ESUR 0x1C Reset value DCMI_CWSTR VST[12:0 HOFFCNT[13:0] Reserve 0x20 Reset value DCMI_CWSIZ VLINE13:0] CAPCNT[13:0] 0x24 Reset value Byte3 Byte2...
Page 303: Advanced-Control Timers (Tim1 And Tim8)
RM0033 Advanced-control timers (TIM1 and TIM8) Advanced-control timers (TIM1 and TIM8) This section applies to the whole STM32F20x and STM32F21x family, unless otherwise specified. 13.1 TIM1 and TIM8 introduction The advanced-control timers (TIM1 and TIM8) consist of a 16-bit auto-reload counter driven by a programmable prescaler.
Page 304: Tim1 And Tim8 Main Features
Advanced-control timers (TIM1 and TIM8) RM0033 13.2 TIM1 and TIM8 main features TIM1 and TIM8 timer features include: • 16-bit up, down, up/down auto-reload counter. • 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock frequency either by any factor between 1 and 65536. •...
Page 305: Figure 65. Advanced-Control Timer Block Diagram
RM0033 Advanced-control timers (TIM1 and TIM8) Figure 65. Advanced-control timer block diagram Internal clock (CK_INT) CK_TIM18 from RCC Trigger Polarity selection, ETRF controller Edge detector and Prescaler ETRP TRGO To other timers To DAC and ADC Input filter ITR0 ITR1 TRGI Slave mode ITR2...
Page 306: Tim1 And Tim8 Functional Description
Advanced-control timers (TIM1 and TIM8) RM0033 13.3 TIM1 and TIM8 functional description 13.3.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.
Page 307: Figure 66. Counter Timing Diagram With Prescaler Division Change From 1 To 2
RM0033 Advanced-control timers (TIM1 and TIM8) Figure 66. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timerclock = CK_CNT FA FB Counter register Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31076V2 Figure 67.
Page 308: Counter Modes
Advanced-control timers (TIM1 and TIM8) RM0033 13.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register plus one (TIMx_RCR+1).
Page 309: Figure 69. Counter Timing Diagram, Internal Clock Divided By 2
RM0033 Advanced-control timers (TIM1 and TIM8) Figure 69. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0034 0035 0036 0000 0001 0002 0003 Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31079V3 Figure 70.
Page 310: Figure 72. Counter Timing Diagram, Update Event When Arpe=0 (Timx_Arr Not Preloaded)
Advanced-control timers (TIM1 and TIM8) RM0033 Figure 72. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) CK_PSC Timerclock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR MS31082V3 Figure 73.
Page 311 RM0033 Advanced-control timers (TIM1 and TIM8) Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event. If the repetition counter is used, the update event (UEV) is generated after downcounting is repeated for the number of times programmed in the repetition counter register plus one (TIMx_RCR+1).
Page 312: Figure 74. Counter Timing Diagram, Internal Clock Divided By 1
Advanced-control timers (TIM1 and TIM8) RM0033 Figure 74. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 01 00 34 33 32 Counter underflow (cnt_udf) Update event (UEV) Update interrupt flag (UIF) MS31184V1 Figure 75. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 313: Figure 76. Counter Timing Diagram, Internal Clock Divided By 4
RM0033 Advanced-control timers (TIM1 and TIM8) Figure 76. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0001 0000 0036 0035 Counter underflow Update event (UEV) Update interrupt flag (UIF) MS40510V1 Figure 77. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register...
Page 314: Figure 78. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
Advanced-control timers (TIM1 and TIM8) RM0033 Figure 78. Counter timing diagram, update event when repetition counter is not used CK_PSC Timerclock = CK_CNT 30 2F Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR MS31188V1 Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the...
Page 315: Figure 79. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr = 0X6
RM0033 Advanced-control timers (TIM1 and TIM8) When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): • The repetition counter is reloaded with the content of TIMx_RCR register •...
Page 316: Figure 81. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36
Advanced-control timers (TIM1 and TIM8) RM0033 Figure 81. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 CK_PSC CNT_EN Timerclock = CK_CNT 0034 0035 0036 0035 Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31191V2 Center-aligned mode 2 or 3 is used with an UIF on overflow. Figure 82.
Page 317: Repetition Counter
RM0033 Advanced-control timers (TIM1 and TIM8) Figure 83. Counter timing diagram, update event with ARPE=1 (counter underflow) CK_PSC Timer clock = CK_CNT Counter register 04 03 02 03 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR Auto-reload active register...
Page 318: Figure 85. Update Rate Examples Depending On Mode And Timx_Rcr Register Settings
Advanced-control timers (TIM1 and TIM8) RM0033 The repetition counter is decremented: • At each counter overflow in upcounting mode, • At each counter underflow in downcounting mode, • At each counter overflow and at each counter underflow in center-aligned mode. Although this limits the maximum number of repetition to 128 PWM cycles, it makes it possible to update the duty cycle twice per PWM period.
Page 319: Clock Selection
RM0033 Advanced-control timers (TIM1 and TIM8) 13.3.4 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin • External clock mode2: external trigger input ETR • Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for example, the user can configure Timer 1 to act as a prescaler for Timer 2.
Page 320: Figure 87. Ti2 External Clock Connection Example
Advanced-control timers (TIM1 and TIM8) RM0033 Figure 87. TI2 external clock connection example TIMx_SMCR TS[2:0] TI2F TI1F Encoder ITRx mode TI1_ED TRGI External clock TI1FP1 CK_PSC mode 1 TI2F_Rising Edge TI2FP2 External clock ETRF Filter detector mode 2 ETRF TI2F_Falling CK_INT Internal clock mode...
Page 321: Figure 88. Control Circuit In External Clock Mode 1
RM0033 Advanced-control timers (TIM1 and TIM8) Figure 88. Control circuit in external clock mode 1 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register Write TIF=0 MS31087V2 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR.
Page 322: Capture/Compare Channels
Advanced-control timers (TIM1 and TIM8) RM0033 For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure: As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
Page 323: Figure 91. Capture/Compare Channel (Example: Channel 1 Input Stage)
RM0033 Advanced-control timers (TIM1 and TIM8) Figure 91. Capture/compare channel (example: channel 1 input stage) TI1F_ED To the slave mode controller TI1F_Rising TI1FP1 Filter TI1F Edge TI1F_Falling downcounter detector IC1PS Divider TI2FP1 /1, /2, /4, /8 CC1P/CC1NP ICF[3:0] TIMx_CCER TIMx_CCMR1 (from slave mode controller) TI2F_Rising...
Page 324: Figure 93. Output Stage Of Capture/Compare Channel (Channel 1 To 3)
Advanced-control timers (TIM1 and TIM8) RM0033 Figure 93. Output stage of capture/compare channel (channel 1 to 3) To the master mode controller ETRF Output enable ‘0’ circuit OC1REFC OC1REF OC1_DT CC1P CNT>CCR1 Output Output Dead-time TIM1_CCER mode CNT=CCR1 selector generator controller OC1N_DT Output...
Page 325: Input Capture Mode
RM0033 Advanced-control timers (TIM1 and TIM8) 13.3.6 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled.
Page 326: Pwm Input Mode
Advanced-control timers (TIM1 and TIM8) RM0033 13.3.7 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. •...
Page 327: Output Compare Mode
RM0033 Advanced-control timers (TIM1 and TIM8) forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. For example: CCxP=0 (OCx active high) => OCx is forced to high level. The OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx register.
Page 328: Pwm Mode
Advanced-control timers (TIM1 and TIM8) RM0033 Figure 96. Output compare mode, toggle on OC1. Write B201h in the CC1R register TIM1_CNT 0039 003A 003B B200 B201 TIM1_CCR1 003A B201 OC1REF= OC1 Match detected on CCR1 Interrupt generated if enabled MS31092V2 13.3.10 PWM mode Pulse Width Modulation mode allows generating a signal with a frequency determined by...
Page 329: Figure 97. Edge-Aligned Pwm Waveforms (Arr=8)
RM0033 Advanced-control timers (TIM1 and TIM8) compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 97 shows some edge-aligned PWM waveforms in an example where TIMx_ARR=8.
Page 330: Figure 98. Center-Aligned Pwm Waveforms (Arr=8)
Advanced-control timers (TIM1 and TIM8) RM0033 TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to Center-aligned mode (up/down counting). Figure 98 shows some center-aligned PWM waveforms in an example where: • TIMx_ARR=8, • PWM mode is the PWM mode 1, •...
Page 331: Complementary Outputs And Dead-Time Insertion
RM0033 Advanced-control timers (TIM1 and TIM8) in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. • Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results.
Page 332: Figure 99. Complementary Output With Dead-Time Insertion
Advanced-control timers (TIM1 and TIM8) RM0033 Figure 99. Complementary output with dead-time insertion. OCxREF delay OCxN delay MS31095V1 Figure 100. Dead-time waveforms with delay greater than the negative pulse. OCxREF delay OCxN MS31096V1 Figure 101. Dead-time waveforms with delay greater than the positive pulse. OCxREF OCxN delay...
Page 333: Using The Break Function
RM0033 Advanced-control timers (TIM1 and TIM8) have both outputs at inactive level or both outputs active and complementary with dead-time. Note: When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes active when OCxREF is high whereas OCxN is complemented and becomes active when OCxREF is low.
Page 334 Advanced-control timers (TIM1 and TIM8) RM0033 active level together. Note that because of the resynchronization on MOE, the dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles). – If OSSI=0 then the timer releases the enable outputs else the enable outputs remain or become high as soon as one of the CCxE or CCxNE bits is high.
Page 335: Figure 102. Output Behavior In Response To A Break
RM0033 Advanced-control timers (TIM1 and TIM8) Figure 102 shows an example of behavior of the outputs in response to a break. Figure 102. Output behavior in response to a break. BREAK (MOE OCxREF (OCxN not implemented, CCxP=0, OISx=1) (OCxN not implemented, CCxP=0, OISx=0) (OCxN not implemented, CCxP=1, OISx=1) (OCxN not implemented, CCxP=1, OISx=0) delay...
Page 336: Clearing The Ocxref Signal On An External Event
Advanced-control timers (TIM1 and TIM8) RM0033 13.3.13 Clearing the OCxREF signal on an external event The OCxREF signal for a given channel can be driven Low by applying a High level to the ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The OCxREF signal remains Low until the next update event, UEV, occurs.
Page 337: 6-Step Pwm Generation
RM0033 Advanced-control timers (TIM1 and TIM8) 13.3.14 6-step PWM generation When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event.
Page 338: One-Pulse Mode
Advanced-control timers (TIM1 and TIM8) RM0033 13.3.15 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.
Page 339: Encoder Interface Mode
RM0033 Advanced-control timers (TIM1 and TIM8) The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY •...
Page 340: Table 55. Counting Direction Versus Encoder Signals
Advanced-control timers (TIM1 and TIM8) RM0033 TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So user must configure TIMx_ARR before starting. in the same way, the capture, compare, prescaler, repetition counter, trigger output features continue to work as normal. Encoder mode and External clock mode 2 are not compatible and must not be selected together.
Page 341: Figure 106. Example Of Counter Operation In Encoder Interface Mode
RM0033 Advanced-control timers (TIM1 and TIM8) Figure 106. Example of counter operation in encoder interface mode. forward jitter backward jitter forward Counter down MS33107V1 Figure 107 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’). Figure 107.
Page 342: Timer Input Xor Function
Advanced-control timers (TIM1 and TIM8) RM0033 13.3.17 Timer input XOR function The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and TIMx_CH3.
Page 343: Figure 108. Example Of Hall Sensor Interface
RM0033 Advanced-control timers (TIM1 and TIM8) Figure 108 describes this example. Figure 108. Example of Hall sensor interface TIH1 TIH2 TIH3 Counter (CNT) (CCR2) CCR1 C7A3 C7A8 C794 C7A5 C7AB C796 TRGO=OC2REF OC1N OC2N OC3N Write CCxE, CCxNE and OCxM for next step ai17335b RM0033 Rev 8 343/1378...
Page 344: Timx And External Trigger Synchronization
Advanced-control timers (TIM1 and TIM8) RM0033 13.3.19 TIMx and external trigger synchronization The TIMx timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated.
Page 345: Figure 110. Control Circuit In Gated Mode
RM0033 Advanced-control timers (TIM1 and TIM8) Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000).
Page 346: Figure 111. Control Circuit In Trigger Mode
Advanced-control timers (TIM1 and TIM8) RM0033 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: • Configure the channel 2 to detect rising edges on TI2.
Page 347: Timer Synchronization
RM0033 Advanced-control timers (TIM1 and TIM8) – CC1P=0 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and detect rising edge only). Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. A rising edge on TI1 enables the counter and sets the TIF flag.
Page 348: Tim1 And Tim8 Registers
Advanced-control timers (TIM1 and TIM8) RM0033 13.4 TIM1 and TIM8 registers Refer to Section 2.2 for a list of abbreviations used in register descriptions. The peripheral registers must be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-word (16 bits) or words (32 bits). 13.4.1 TIM1 and TIM8 control register 1 (TIMx_CR1) Address offset: 0x00...
Page 349: Tim1 And Tim8 Control Register 2 (Timx_Cr2)
RM0033 Advanced-control timers (TIM1 and TIM8) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: –...
Page 350 Advanced-control timers (TIM1 and TIM8) RM0033 Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
Page 351 RM0033 Advanced-control timers (TIM1 and TIM8) Bit 2 CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI Note: This bit acts only on channels that have a complementary output.
Page 352: Tim1 And Tim8 Slave Mode Control Register (Timx_Smcr)
Advanced-control timers (TIM1 and TIM8) RM0033 13.4.3 TIM1 and TIM8 slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 ETPS[1:0] ETF[3:0] TS[2:0] Res. SMS[2:0] Res. Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge.
Page 353 RM0033 Advanced-control timers (TIM1 and TIM8) Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 354: Tim1 And Tim8 Dma/Interrupt Enable Register (Timx_Dier)
Advanced-control timers (TIM1 and TIM8) RM0033 Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
Page 355 RM0033 Advanced-control timers (TIM1 and TIM8) Bit 12 CC4DE: Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled 1: CC4 DMA request enabled Bit 11 CC3DE: Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled 1: CC3 DMA request enabled Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled 1: CC2 DMA request enabled...
Page 356: Tim1 And Tim8 Status Register (Timx_Sr)
Advanced-control timers (TIM1 and TIM8) RM0033 13.4.5 TIM1 and TIM8 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 CC4OF CC3OF CC2OF CC1OF Res. COMIF CC4IF CC3IF CC2IF CC1IF Reserved rc_w0 rc_w0 rc_w0 rc_w0 Res. rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0...
Page 357: Tim1 And Tim8 Event Generation Register (Timx_Egr)
RM0033 Advanced-control timers (TIM1 and TIM8) Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
Page 358 Advanced-control timers (TIM1 and TIM8) RM0033 Bit 5 COMG: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware 0: No action 1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits Note: This bit acts only on channels having a complementary output.
Page 359: Tim1 And Tim8 Capture/Compare Mode Register 1 (Timx_Ccmr1)
RM0033 Advanced-control timers (TIM1 and TIM8) 13.4.7 TIM1 and TIM8 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 360 Advanced-control timers (TIM1 and TIM8) RM0033 Bits 6:4 OC1M: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 361 RM0033 Advanced-control timers (TIM1 and TIM8) Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC.
Page 362: Tim1 And Tim8 Capture/Compare Mode Register 2 (Timx_Ccmr2)
Advanced-control timers (TIM1 and TIM8) RM0033 Bits 1:0 CC1S: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC.
Page 363: Tim1 And Tim8 Capture/Compare Enable Register (Timx_Ccer)
RM0033 Advanced-control timers (TIM1 and TIM8) Input capture mode Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3...
Page 364 Advanced-control timers (TIM1 and TIM8) RM0033 Bit 7 CC2NP: Capture/Compare 2 complementary output polarity refer to CC1NP description Bit 6 CC2NE: Capture/Compare 2 complementary output enable refer to CC1NE description Bit 5 CC2P: Capture/Compare 2 output polarity refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 complementary output polarity...
Page 365 RM0033 Advanced-control timers (TIM1 and TIM8) Bit 1 CC1P: Capture/Compare 1 output polarity CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations.
Page 366: Table 57. Output Control Bits For Complementary Ocx And Ocxn Channels With
Advanced-control timers (TIM1 and TIM8) RM0033 Table 57. Output control bits for complementary OCx and OCxN channels with break feature Control bits Output states OSSI OSSR CCxE CCxNE OCx output state OCxN output state Output Disabled (not driven by Output Disabled (not driven by the the timer), OCx=0, OCx_EN=0 timer), OCxN=0, OCxN_EN=0 Output Disabled (not driven by...
Page 367: Tim1 And Tim8 Counter (Timx_Cnt)
RM0033 Advanced-control timers (TIM1 and TIM8) 13.4.10 TIM1 and TIM8 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 13.4.11 TIM1 and TIM8 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to f / (PSC[15:0] + 1).
Page 368: Tim1 And Tim8 Repetition Counter Register (Timx_Rcr)
Advanced-control timers (TIM1 and TIM8) RM0033 13.4.13 TIM1 and TIM8 repetition counter register (TIMx_RCR) Address offset: 0x30 Reset value: 0x0000 REP[7:0] Reserved Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable.
Page 369: Tim1 And Tim8 Capture/Compare Register 2 (Timx_Ccr2)
RM0033 Advanced-control timers (TIM1 and TIM8) 13.4.15 TIM1 and TIM8 capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
Page 370: Tim1 And Tim8 Capture/Compare Register 4 (Timx_Ccr4)
Advanced-control timers (TIM1 and TIM8) RM0033 13.4.17 TIM1 and TIM8 capture/compare register 4 (TIMx_CCR4) Address offset: 0x40 Reset value: 0x0000 CCR4[15:0] rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro Bits 15:0 CCR4[15:0]: Capture/Compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).
Page 371 RM0033 Advanced-control timers (TIM1 and TIM8) Bit 13 BKP: Break polarity 0: Break input BRK is active low 1: Break input BRK is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 372: Tim1 And Tim8 Dma Control Register (Timx_Dcr)
Advanced-control timers (TIM1 and TIM8) RM0033 Bits 7:0 DTG[7:0]: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x t with t DTG[7:5]=10x => DT=(64+DTG[5:0])xt with T =2xt DTG[7:5]=110 =>...
Page 373: Tim1 And Tim8 Dma Address For Full Transfer (Timx_Dmar)
RM0033 Advanced-control timers (TIM1 and TIM8) 13.4.20 TIM1 and TIM8 DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 0000 DMAB[31:16] DMAB[15:0] Bits 31:0 DMAB[31:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the...
Page 374: Tim1 And Tim8 Register Map
Advanced-control timers (TIM1 and TIM8) RM0033 13.4.21 TIM1 and TIM8 register map TIM1 and TIM8 registers are mapped as 16-bit addressable registers as described in the table below: Table 58. TIM1 and TIM8 register map and reset values Offset Register TIMx_CR1 [1:0] [1:0]...
Page 375 RM0033 Advanced-control timers (TIM1 and TIM8) Table 58. TIM1 and TIM8 register map and reset values (continued) Offset Register TIMx_ARR ARR[15:0] 0x2C Reserved Reset value TIMx_RCR REP[7:0] 0x30 Reserved Reset value TIMx_CCR1 CCR1[15:0] 0x34 Reserved Reset value TIMx_CCR2 CCR2[15:0] 0x38 Reserved Reset value TIMx_CCR3...
Page 376: General-Purpose Timers (Tim2 To Tim5)
General-purpose timers (TIM2 to TIM5) RM0033 General-purpose timers (TIM2 to TIM5) This section applies to the whole STM32F20x and STM32F21x family, unless otherwise specified. 14.1 TIM2 to TIM5 introduction The general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a programmable prescaler.
Page 377: Figure 113. General-Purpose Timer Block Diagram
RM0033 General-purpose timers (TIM2 to TIM5) Figure 113. General-purpose timer block diagram Internal clock (CK_INT) TIMxCLK from RCC Trigger ETRF controller TRGO Polarity selection & edge ETRP TIMx_ETR Input filter detector & prescaler to other timers to DAC/ADC ITR0 ITR1 Slave ITR2 TRGI...
Page 378: Tim2 To Tim5 Functional Description
General-purpose timers (TIM2 to TIM5) RM0033 14.3 TIM2 to TIM5 functional description 14.3.1 Time-base unit The main block of the programmable timer is a 16-bit/32-bit counter with its related auto- reload register. The counter can count up but also down or both up and down. The counter clock can be divided by a prescaler.
Page 379: Counter Modes
RM0033 General-purpose timers (TIM2 to TIM5) Figure 114. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC CNT_EN Timerclock = CK_CNT Counter register F8 F9 FA FB Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS35833V1...
Page 380: Figure 116. Counter Timing Diagram, Internal Clock Divided By 1
General-purpose timers (TIM2 to TIM5) RM0033 does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.
Page 381: Figure 118. Counter Timing Diagram, Internal Clock Divided By 4
RM0033 General-purpose timers (TIM2 to TIM5) Figure 118. Counter timing diagram, internal clock divided by 4 CK_INT CNT_EN Timerclock = CK_CNT Counter register 0035 0036 0000 0001 Counter overflow Update event (UEV) Update interrupt flag (UIF) MSv37301V1 Figure 119. Counter timing diagram, internal clock divided by N CK_INT Timerclock = CK_CNT Counter register...
Page 382: Figure 120. Counter Timing Diagram, Update Event When Arpe=0 (Timx_Arr Not Preloaded)
General-purpose timers (TIM2 to TIM5) RM0033 Figure 120. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) CK_INT CNT_EN Timerclock = CK_CNT Counter register 32 33 34 35 36 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload register Write a new value in TIMx_ARR...
Page 383: Figure 122. Counter Timing Diagram, Internal Clock Divided By 1
RM0033 General-purpose timers (TIM2 to TIM5) preload registers. Then no update event occurs until UDIS bit has been written to 0. However, the counter restarts from the current auto-reload value, whereas the counter of the prescaler restarts from 0 (but the prescale rate doesn’t change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent).
Page 384: Figure 123. Counter Timing Diagram, Internal Clock Divided By 2
General-purpose timers (TIM2 to TIM5) RM0033 Figure 123. Counter timing diagram, internal clock divided by 2 CK_INT CNT_EN Timerclock = CK_CNT Counter register 0002 0001 0000 0036 0035 0034 0033 Counter underflow Update event (UEV) Update interrupt flag (UIF) MSv37306V1 Figure 124.
Page 385: Figure 126. Counter Timing Diagram, Update Event
RM0033 General-purpose timers (TIM2 to TIM5) Figure 126. Counter timing diagram, Update event CK_INT CNT_EN Timerclock = CK_CNT Counter register 04 03 02 00 36 35 34 33 32 31 30 2F Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR MS37341V1...
Page 386: Figure 127. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr=0X6
General-purpose timers (TIM2 to TIM5) RM0033 When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register).
Page 387: Figure 129. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36
RM0033 General-purpose timers (TIM2 to TIM5) Figure 129. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 CK_INT CNT_EN Timerclock = CK_CNT Counter register 0034 0035 0036 0035 Counter overflow (cnt_ovf) Update event (UEV) Update interrupt flag (UIF) MS37344V1 1. Center-aligned mode 2 or 3 is used with an UIF on overflow. Figure 130.
Page 388: Figure 131. Counter Timing Diagram, Update Event With Arpe=1 (Counter Underflow)
General-purpose timers (TIM2 to TIM5) RM0033 Figure 131. Counter timing diagram, Update event with ARPE=1 (counter underflow) CK_INT CNT_EN Timerclock = CK_CNT Counter register 05 04 03 02 02 03 04 05 06 07 Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR Auto-reload active register...
Page 389: Clock Selection
RM0033 General-purpose timers (TIM2 to TIM5) 14.3.3 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin (TIx) • External clock mode2: external trigger input (ETR) available on TIM2, TIM3 and TIM4 only.
Page 390: Figure 134. Ti2 External Clock Connection Example
General-purpose timers (TIM2 to TIM5) RM0033 Figure 134. TI2 external clock connection example TIMx_SMCR TS[2:0] TI2F TI1F Encoder ITRx mode TI1_ED TRGI External clock TI1FP1 CK_PSC mode 1 TI2F_Rising Edge TI2FP2 External clock ETRF Filter detector mode 2 ETRF TI2F_Falling CK_INT Internal clock mode...
Page 391: Figure 135. Control Circuit In External Clock Mode 1
RM0033 General-purpose timers (TIM2 to TIM5) Figure 135. Control circuit in external clock mode 1 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register Write TIF=0 MS31087V2 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR.
Page 392: Capture/Compare Channels
General-purpose timers (TIM2 to TIM5) RM0033 The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal. Figure 137. Control circuit in external clock mode 2 CK_INT CNT_EN ETRP...
Page 393: Figure 139. Capture/Compare Channel 1 Main Circuit
RM0033 General-purpose timers (TIM2 to TIM5) Figure 139. Capture/compare channel 1 main circuit APB Bus MCU-peripheral interface write CCR1H Read CCR1H write_in_progress read_in_progress write CCR1L Capture/compare preload register Read CCR1L Output CC1S[1] compare_transfer mode capture_transfer CC1S[0] Input CC1S[1] OC1PE mode OC1PE Capture /compare shadow register CC1S[0]...
Page 394: Input Capture Mode
General-purpose timers (TIM2 to TIM5) RM0033 14.3.5 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled.
Page 395: Pwm Input Mode
RM0033 General-purpose timers (TIM2 to TIM5) 14.3.6 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. •...
Page 396: Forced Output Mode
General-purpose timers (TIM2 to TIM5) RM0033 14.3.7 Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter.
Page 397: Pwm Mode
RM0033 General-purpose timers (TIM2 to TIM5) The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 142.
Page 398: Figure 143. Edge-Aligned Pwm Waveforms (Arr=8)
General-purpose timers (TIM2 to TIM5) RM0033 The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register. PWM edge-aligned mode Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Upcounting mode.
Page 399: Figure 144. Center-Aligned Pwm Waveforms (Arr=8)
RM0033 General-purpose timers (TIM2 to TIM5) up and down depending on the CMS bits configuration. The direction bit (DIR) in the TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to Center-aligned mode (up/down counting). Figure 144 shows some center-aligned PWM waveforms in an example where: •...
Page 400: One-Pulse Mode
General-purpose timers (TIM2 to TIM5) RM0033 in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. • Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results.
Page 401: Clearing The Ocxref Signal On An External Event
RM0033 General-purpose timers (TIM2 to TIM5) Let’s use TI2FP2 as trigger 1: • Map TI2FP2 on TI2 by writing CC2S=01 in the TIMx_CCMR1 register. • TI2FP2 must detect a rising edge, write CC2P=0 and CC2NP=’0’ in the TIMx_CCER register. • Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=110 in the TIMx_SMCR register.
Page 402: Encoder Interface Mode
General-purpose timers (TIM2 to TIM5) RM0033 The external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR register are cleared to 00. The external clock mode 2 must be disabled: bit ECE in the TIM1_SMCR register is cleared to 0. The external trigger polarity (ETP) and the external trigger filter (ETF) can be configured according to the application’s needs.
Page 403: Table 59. Counting Direction Versus Encoder Signals
RM0033 General-purpose timers (TIM2 to TIM5) must configure TIMx_ARR before starting. In the same way, the capture, compare, prescaler, trigger output features continue to work as normal. In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s position.
Page 404: Figure 147. Example Of Counter Operation In Encoder Interface Mode
General-purpose timers (TIM2 to TIM5) RM0033 Figure 147. Example of counter operation in encoder interface mode forward jitter backward jitter forward Counter down MS33107V1 Figure 148 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=1). Figure 148.
Page 405: Timer Input Xor Function
RM0033 General-purpose timers (TIM2 to TIM5) 14.3.13 Timer input XOR function The TI1S bit in the TIM1_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3. The XOR output can be used with all the timer input functions such as trigger or input capture.
Page 406: Figure 150. Control Circuit In Gated Mode
General-purpose timers (TIM2 to TIM5) RM0033 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000).
Page 407: Figure 151. Control Circuit In Trigger Mode
RM0033 General-purpose timers (TIM2 to TIM5) When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set. The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input.
Page 408: Timer Synchronization
General-purpose timers (TIM2 to TIM5) RM0033 Figure 152. Control circuit in external clock mode 2 + trigger mode CEN/CNT_EN Counter clock = CK_CNT = CK_PSC Counter register MS33110V1 14.3.15 Timer synchronization The TIMx timers are linked together internally for timer synchronization or chaining. When one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of another Timer configured in Slave Mode.
Page 409: Figure 154. Gating Timer 2 With Oc1Ref Of Timer 1
RM0033 General-purpose timers (TIM2 to TIM5) For example, the user can configure Timer 1 to act as a prescaler for Timer 2 (see Figure 153). To do this: • Configure Timer 1 in master mode so that it outputs a periodic trigger signal on each update event UEV.
Page 410: Figure 155. Gating Timer 2 With Enable Of Timer 1
General-purpose timers (TIM2 to TIM5) RM0033 you want in the timer counters. The timers can easily be reset by software using the UG bit in the TIMx_EGR registers. In the next example, we synchronize Timer 1 and Timer 2. Timer 1 is the master and starts from 0.
Page 411: Figure 156. Triggering Timer 2 With Update Of Timer 1
RM0033 General-purpose timers (TIM2 to TIM5) Using one timer to start another timer In this example, we set the enable of Timer 2 with the update event of Timer 1. Refer to Figure 153 for connections. Timer 2 starts counting from its current value (which can be nonzero) on the divided internal clock as soon as the update event is generated by Timer 1.
Page 412: Figure 157. Triggering Timer 2 With Enable Of Timer 1
General-purpose timers (TIM2 to TIM5) RM0033 Figure 157. Triggering timer 2 with Enable of timer 1 CK_INT TIMER1-CEN=CNT_EN TIMER1-CNT_INIT TIMER1-CNT TIMER2-CNT TIMER2-CNT_INIT TIMER2-write CNT TIMER2-TIF Write TIF = 0 MS37391V1 Starting 2 timers synchronously in response to an external trigger In this example, we set the enable of timer 1 when its TI1 input rises, and the enable of Timer 2 with the enable of Timer 1.
Page 413: Debug Mode
RM0033 General-purpose timers (TIM2 to TIM5) Figure 158. Triggering timer 1 and 2 with timer 1 TI1 input CK_INT TIMER1-TI1 TIMER1-CEN=CNT_EN TIMER1-CK_PSC TIMER1-CNT 02 03 04 05 06 07 08 09 TIMER1-TIF TIMER2-CEN=CNT_EN TIMER2-CK_PSC TIMER2-CNT 01 02 03 04 05 06 07 08 09 TIMER2-TIF MS37392V1 14.3.16...
Page 414: Tim2 To Tim5 Registers
General-purpose timers (TIM2 to TIM5) RM0033 14.4 TIM2 to TIM5 registers Refer to Section 2.2 for a list of abbreviations used in register descriptions. The 32-bit peripheral registers have to be written by words (32 bits). All other peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
Page 415 RM0033 General-purpose timers (TIM2 to TIM5) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: –...
Page 416: Timx Control Register 2 (Timx_Cr2)
General-purpose timers (TIM2 to TIM5) RM0033 14.4.2 TIMx control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 TI1S MMS[2:0] CCDS Reserved Reserved Bits 15:8 Reserved, must be kept at reset value. Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) See also Section 13.3.18: Interfacing with Hall sensors...
Page 417: Timx Slave Mode Control Register (Timx_Smcr)
RM0033 General-purpose timers (TIM2 to TIM5) 14.4.3 TIMx slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 ETPS[1:0] ETF[3:0] TS[2:0] SMS[2:0] Res. Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is noninverted, active at high level or rising edge 1: ETR is inverted, active at low level or falling edge Bit 14 ECE: External clock enable...
Page 418 General-purpose timers (TIM2 to TIM5) RM0033 Bit 7 MSM: Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Page 419: Timx Dma/Interrupt Enable Register (Timx_Dier)
RM0033 General-purpose timers (TIM2 to TIM5) Table 60. TIMx internal trigger connection Slave TIM ITR0 (TS = 000) ITR1 (TS = 001) ITR2 (TS = 010) ITR3 (TS = 011) TIM2 TIM1_TRGO TIM8_TRGO TIM3_TRGO TIM4_TRGO TIM3 TIM1_TRGO TIM2_TRGO TIM5_TRGO TIM4_TRGO TIM4 TIM1_TRGO TIM2_TRGO...
Page 420: Timx Status Register (Timx_Sr)
General-purpose timers (TIM2 to TIM5) RM0033 Bit 3 CC3IE: Capture/Compare 3 interrupt enable 0: CC3 interrupt disabled 1: CC3 interrupt enabled Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled 1: CC2 interrupt enabled Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable...
Page 421 RM0033 General-purpose timers (TIM2 to TIM5) Bit 3 CC3IF: Capture/Compare 3 interrupt flag refer to CC1IF description Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
Page 422: Timx Event Generation Register (Timx_Egr)
General-purpose timers (TIM2 to TIM5) RM0033 14.4.6 TIMx event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 CC4G CC3G CC2G CC1G Reserved Res. Bits 15:7 Reserved, must be kept at reset value. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
Page 423: Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)
RM0033 General-purpose timers (TIM2 to TIM5) 14.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 424 General-purpose timers (TIM2 to TIM5) RM0033 Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 425 RM0033 General-purpose timers (TIM2 to TIM5) Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output.
Page 426: Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)
General-purpose timers (TIM2 to TIM5) RM0033 14.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. OC4CE OC4M[2:0] OC4PE OC4FE OC3CE OC3M[2:0] OC3PE OC3FE CC4S[1:0] CC3S[1:0] IC4F[3:0] IC4PSC[1:0] IC3F[3:0] IC3PSC[1:0] Output compare mode Bit 15 OC4CE: Output compare 4 clear enable Bits 14:12 OC4M: Output compare 4 mode...
Page 427: Timx Capture/Compare Enable Register (Timx_Ccer)
RM0033 General-purpose timers (TIM2 to TIM5) Input capture mode Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3...
Page 428: Table 61. Output Control Bit For Standard Ocx Channels
General-purpose timers (TIM2 to TIM5) RM0033 Bit 8 CC3E: Capture/Compare 3 output enable. refer to CC1E description Bit 7 CC2NP: Capture/Compare 2 output Polarity. refer to CC1NP description Bit 6 Reserved, must be kept at reset value. Bit 5 CC2P: Capture/Compare 2 output Polarity. refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable.
Page 429: Timx Counter (Timx_Cnt)
RM0033 General-purpose timers (TIM2 to TIM5) Note: The state of the external IO pins connected to the standard OCx channels depends on the OCx channel state and the GPIO registers. 14.4.10 TIMx counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 0000 CNT[31:16] (depending on timers) CNT[15:0] Bits 31:16 CNT[31:16]: High counter value (on TIM2 and TIM5).
Page 430: Timx Capture/Compare Register 1 (Timx_Ccr1)
General-purpose timers (TIM2 to TIM5) RM0033 Bits 31:16 ARR[31:16]: High auto-reload value (on TIM2 and TIM5). Bits 15:0 ARR[15:0]: Low Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 14.3.1: Time-base unit for more details about ARR update and behavior.
Page 431: Timx Capture/Compare Register 3 (Timx_Ccr3)
RM0033 General-purpose timers (TIM2 to TIM5) Bits 31:16 CCR2[31:16]: High Capture/Compare 2 value (on TIM2 and TIM5). Bits 15:0 CCR2[15:0]: Low Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE).
Page 432: Timx Dma Control Register (Timx_Dcr)
General-purpose timers (TIM2 to TIM5) RM0033 Bits 31:16 CCR4[31:16]: High Capture/Compare 4 value (on TIM2 and TIM5). Bits 15:0 CCR4[15:0]: Low Capture/Compare value if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE).
Page 433: Timx Dma Address For Full Transfer (Timx_Dmar)
RM0033 General-purpose timers (TIM2 to TIM5) 14.4.18 TIMx DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 DMAB[15:0] Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the...
Page 434: Tim2 Option Register (Tim2_Or)
General-purpose timers (TIM2 to TIM5) RM0033 14.4.19 TIM2 option register (TIM2_OR) Address offset: 0x50 Reset value: 0x0000 ITR1_RMP Reserved Reserved Bits 15:12 Reserved, must be kept at reset value. Bits 11:10 ITR1_RMP: Internal trigger 1 remap Set and cleared by software. 00: TIM8_TRGOUT 01: PTP trigger output is connected to TIM2_ITR1 10: OTG FS SOF is connected to the TIM2_ITR1 input...
Page 435: Timx Register Map
RM0033 General-purpose timers (TIM2 to TIM5) 14.4.21 TIMx register map TIMx registers are mapped as described in the table below: Table 62. TIM2 to TIM5 register map and reset values Offset Register TIMx_CR1 [1:0] [1:0] 0x00 Reserved Reset value TIMx_CR2 MMS[2:0] 0x04 Reserved...
Page 436 General-purpose timers (TIM2 to TIM5) RM0033 Table 62. TIM2 to TIM5 register map and reset values (continued) Offset Register ARR[31:16] TIMx_ARR ARR[15:0] (TIM2 and TIM5 only, reserved on the other timers) 0x2C Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0x30 Reserved CCR1[31:16]...
Page 437: General-Purpose Timers (Tim9 To Tim14)
RM0033 General-purpose timers (TIM9 to TIM14) General-purpose timers (TIM9 to TIM14) This section applies to the whole STM32F20x and STM32F21x family, unless otherwise specified. 15.1 TIM9 to TIM14 introduction The TIM9 to TIM14 general-purpose timers consist of a 16-bit auto-reload counter driven by a programmable prescaler.
Page 438: Tim10/Tim11 And Tim13/Tim14 Main Features
General-purpose timers (TIM9 to TIM14) RM0033 Figure 159. General-purpose timer block diagram (TIM9 and TIM12) Internal clock (CK_INT) Trigger controller ITR0 Slave ITR1 Reset, enable, up, count controller ITR2 TRGI mode ITR3 TI1F_ED TI1FP1 TI2FP2 Auto-reload register Stop, Clear CK_PSC CK_CNT CNT counter prescaler...
Page 439: Figure 160. General-Purpose Timer Block Diagram (Tim10/11/13/14)
RM0033 General-purpose timers (TIM9 to TIM14) Figure 160. General-purpose timer block diagram (TIM10/11/13/14) Internal clock (CK_INT) Enable Trigger counter Controller Autoreload register Stop, Clear CK_PSC CK_CNT prescaler counter CC1I CC1I TI1FP1 output Input filter & IC1PS OC1REF Prescaler Capture/Compare 1 register TIMx_CH1 TIMx_CH1 edge detector...
Page 440: Tim9 To Tim14 Functional Description
General-purpose timers (TIM9 to TIM14) RM0033 15.3 TIM9 to TIM14 functional description 15.3.1 Time-base unit The main block of the timer is a 16-bit counter with its related auto-reload register. The counters counts up. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
Page 441: Figure 161. Counter Timing Diagram With Prescaler Division Change From 1 To 2
RM0033 General-purpose timers (TIM9 to TIM14) Figure 161. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timerclock = CK_CNT FA FB Counter register Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31076V2 Figure 162.
Page 442: Counter Modes
General-purpose timers (TIM9 to TIM14) RM0033 15.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller on TIM9 and TIM12) also generates an update event.
Page 443: Figure 164. Counter Timing Diagram, Internal Clock Divided By 2
RM0033 General-purpose timers (TIM9 to TIM14) Figure 164. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0034 0035 0036 0000 0001 0002 0003 Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31079V3 Figure 165.
Page 444: Figure 167. Counter Timing Diagram, Update Event When Arpe=0 (Timx_Arr Not Preloaded)
General-purpose timers (TIM9 to TIM14) RM0033 Figure 167. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) CK_PSC Timerclock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR MS31082V3 Figure 168.
Page 445: Clock Selection
RM0033 General-purpose timers (TIM9 to TIM14) 15.3.3 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1 (for TIM9 and TIM12): external input pin (TIx) • Internal trigger inputs (ITRx) (for TIM9 and TIM12): connecting the trigger output from another timer.
Page 446: Figure 170. Ti2 External Clock Connection Example
General-purpose timers (TIM9 to TIM14) RM0033 Figure 170. TI2 external clock connection example TIMx_SMCR TS[2:0] TI2F TI1F ITRx TI1_ED CK_PSC TRGI External clock TI1FP1 mode 1 TI2F_Rising Edge TI2FP2 Filter detector TI2F_Falling CK_INT Internal clock mode (internal clock) ICF[3:0] CC2P TIMx_CCER TIMx_CCMR1 SMS[2:0]...
Page 447: Capture/Compare Channels
RM0033 General-purpose timers (TIM9 to TIM14) 15.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). Figure 172 Figure 174 give an overview of a capture/compare channel.
Page 448: Input Capture Mode
General-purpose timers (TIM9 to TIM14) RM0033 Figure 173. Capture/compare channel 1 main circuit APB Bus MCU-peripheral interface write CCR1H Read CCR1H write_in_progress read_in_progress write CCR1L Capture/compare preload register Read CCR1L Output CC1S[1] compare_transfer mode capture_transfer CC1S[0] Input CC1S[1] OC1PE mode OC1PE Capture /compare shadow register CC1S[0]...
Page 449 RM0033 General-purpose timers (TIM9 to TIM14) capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to ‘0’...
Page 450: Pwm Input Mode (Only For Tim9/12)
General-purpose timers (TIM9 to TIM14) RM0033 15.3.6 PWM input mode (only for TIM9/12) This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. •...
Page 451: Forced Output Mode
RM0033 General-purpose timers (TIM9 to TIM14) 15.3.7 Forced output mode In output mode (CCxS bits = ‘00’ in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter.
Page 452: Pwm Mode
General-purpose timers (TIM9 to TIM14) RM0033 The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 176.
Page 453: One-Pulse Mode
RM0033 General-purpose timers (TIM9 to TIM14) TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 177 shows some edge- aligned PWM waveforms in an example where TIMx_ARR=8. Figure 177.
Page 454: Figure 178. Example Of One Pulse Mode
General-purpose timers (TIM9 to TIM14) RM0033 Figure 178. Example of one pulse mode. OC1REF TIM1_ARR TIM1_CCR1 DELAY PULSE MS31099V1 For example the user may want to generate a positive pulse on OC1 with a length of t PULSE and after a delay of t as soon as a positive edge is detected on the TI2 input pin.
Page 455: Tim9/12 External Trigger Synchronization
RM0033 General-purpose timers (TIM9 to TIM14) Particular case: OCx fast enable In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle.
Page 456: Figure 179. Control Circuit In Reset Mode
General-purpose timers (TIM9 to TIM14) RM0033 Figure 179. Control circuit in reset mode Counter clock = ck_cnt = ck_psc Counter register 32 33 34 35 36 01 02 03 00 01 02 03 MS31401V2 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: Configure the channel 1 to detect low levels on TI1.
Page 457: Figure 180. Control Circuit In Gated Mode
RM0033 General-purpose timers (TIM9 to TIM14) Figure 180. Control circuit in gated mode cnt_en Counter clock = ck_cnt = ck_psc Counter register 35 36 32 33 Write TIF=0 MS31402V1 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: Configure the channel 2 to detect rising edges on TI2.
Page 458: Timer Synchronization (Tim9/12)
General-purpose timers (TIM9 to TIM14) RM0033 15.3.12 Timer synchronization (TIM9/12) The TIM timers are linked together internally for timer synchronization or chaining. Refer to Section 14.3.15: Timer synchronization for details. Note: The clock of the slave timer must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
Page 459: Tim9 And Tim12 Registers
RM0033 General-purpose timers (TIM9 to TIM14) 15.4 TIM9 and TIM12 registers Refer to Section 2.2 for a list of abbreviations used in register descriptions. The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
Page 460: Tim9/12 Control Register 2 (Timx_Cr2)
General-purpose timers (TIM9 to TIM14) RM0033 15.4.2 TIM9/12 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 MMS[2:0] Reserved Reserved Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 MMS[2:0]: Master mode selection These bits are used to select the information to be sent in Master mode to slave timers for synchronization (TRGO).
Page 461: Tim9/12 Slave Mode Control Register (Timx_Smcr)
RM0033 General-purpose timers (TIM9 to TIM14) 15.4.3 TIM9/12 slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 TS[2:0] SMS[2:0] Reserved Res. Bits 15:8 Reserved, must be kept at reset value. Bit 7 MSM: Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO).
Page 462: Tim9/12 Interrupt Enable Register (Timx_Dier)
General-purpose timers (TIM9 to TIM14) RM0033 Bit 3 Reserved, must be kept at reset value. Bits 2:0 SMS: Slave mode selection When external signals are selected, the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input control register and Control register descriptions.
Page 463 RM0033 General-purpose timers (TIM9 to TIM14) Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled. 1: CC2 interrupt enabled. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled. 1: CC1 interrupt enabled. Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled.
Page 464: Tim9/12 Status Register (Timx_Sr)
General-purpose timers (TIM9 to TIM14) RM0033 15.4.5 TIM9/12 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 CC2OF CC1OF CC2IF CC1IF Reserved Reserved Reserved rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:11 Reserved, must be kept at reset value. Bit 10 CC2OF: Capture/compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input...
Page 465: Tim9/12 Event Generation Register (Timx_Egr)
RM0033 General-purpose timers (TIM9 to TIM14) Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: –...
Page 466: Tim9/12 Capture/Compare Mode Register 1 (Timx_Ccmr1)
General-purpose timers (TIM9 to TIM14) RM0033 15.4.7 TIM9/12 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits in this register have different functions in input and output modes.
Page 467 RM0033 General-purpose timers (TIM9 to TIM14) Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas the active levels of OC1 and OC1N depend on the CC1P and CC1NP bits, respectively.
Page 468 General-purpose timers (TIM9 to TIM14) RM0033 Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1...
Page 469: Tim9/12 Capture/Compare Enable Register (Timx_Ccer)
RM0033 General-purpose timers (TIM9 to TIM14) 15.4.8 TIM9/12 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 CC2NP CC2P CC2E CC1NP CC1P CC1E Reserved Res. Res. Bits 15:8 Reserved, must be kept at reset value. Bit 7 CC2NP: Capture/Compare 2 output Polarity refer to CC1NP description Bits 6 Reserved, must be kept at reset value.
Page 470: Tim9/12 Counter (Timx_Cnt)
General-purpose timers (TIM9 to TIM14) RM0033 Table 64. Output control bit for standard OCx channels CCxE bit OCx output state Output disabled (OCx=’0’, OCx_EN=’0’) OCx=OCxREF + Polarity, OCx_EN=’1’ Note: The states of the external I/O pins connected to the standard OCx channels depend on the state of the OCx channel and on the GPIO registers.
Page 471: Tim9/12 Capture/Compare Register 1 (Timx_Ccr1)
RM0033 General-purpose timers (TIM9 to TIM14) 15.4.12 TIM9/12 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 CCR1[15:0] rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded into the actual capture/compare 1 register (preload value).
Page 472: Tim9/12 Register Map
General-purpose timers (TIM9 to TIM14) RM0033 15.4.14 TIM9/12 register map TIM9/12 registers are mapped as 16-bit addressable registers as described below. The reserved memory areas are highlighted in gray in the table. Table 65. TIM9/12 register map and reset values Offset Register TIMx_CR1...
Page 473 RM0033 General-purpose timers (TIM9 to TIM14) Table 65. TIM9/12 register map and reset values (continued) Offset Register TIMx_CCR1 CCR1[15:0] 0x34 Reserved Reset value TIMx_CCR2 CCR2[15:0] 0x38 Reserved Reset value 0x3C to Reserved 0x4C Refer to Section 3.3: Memory map for the register boundary addresses. RM0033 Rev 8 473/1378...
Page 474: Tim10/11/13/14 Registers
General-purpose timers (TIM9 to TIM14) RM0033 15.5 TIM10/11/13/14 registers The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 15.5.1 TIM10/11/13/14 control register 1 (TIMx_CR1) Address offset: 0x00...
Page 475: Tim10/11/13/14 Interrupt Enable Register (Timx_Dier)
RM0033 General-purpose timers (TIM9 to TIM14) 15.5.2 TIM10/11/13/14 Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 CC1IE Reserved Bits 15:2 Reserved, must be kept at reset value. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled...
Page 476: Tim10/11/13/14 Event Generation Register (Timx_Egr)
General-purpose timers (TIM9 to TIM14) RM0033 Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: –...
Page 477 RM0033 General-purpose timers (TIM9 to TIM14) Output compare mode Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 is derived.
Page 478 General-purpose timers (TIM9 to TIM14) RM0033 Input capture mode Bits 15:8 Reserved, must be kept at reset value. Bits 7:4 IC1F: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1.
Page 479: Tim10/11/13/14 Capture/Compare Enable Register (Timx_Ccer)
RM0033 General-purpose timers (TIM9 to TIM14) 15.5.6 TIM10/11/13/14 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 CC1NP CC1P CC1E Reserved Res. Bits 15:4 Reserved, must be kept at reset value. Bit 3 CC1NP: Capture/Compare 1 complementary output Polarity. CC1 channel configured as output: CC1NP must be kept cleared.
Page 480: Tim10/11/13/14 Counter (Timx_Cnt)
General-purpose timers (TIM9 to TIM14) RM0033 15.5.7 TIM10/11/13/14 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 15.5.8 TIM10/11/13/14 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1).
Page 481: Tim10/11/13/14 Capture/Compare Register 1 (Timx_Ccr1)
RM0033 General-purpose timers (TIM9 to TIM14) 15.5.10 TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 CCR1[15:0] rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
Page 482: Tim10/11/13/14 Register Map
General-purpose timers (TIM9 to TIM14) RM0033 15.5.12 TIM10/11/13/14 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below. Table 67. TIM10/11/13/14 register map and reset values Offset Register TIMx_CR1 Reserve [1:0] 0x00 Reserved Reset value TIMx_SMCR 0x08 Reserved...
Page 483 RM0033 General-purpose timers (TIM9 to TIM14) Table 67. TIM10/11/13/14 register map and reset values (continued) Offset Register TIMx_OR 0x50 Reserved Reset value Refer to Section 3.3: Memory map for the register boundary addresses. RM0033 Rev 8 483/1378...
Page 484: Basic Timers (Tim6 And Tim7)
Basic timers (TIM6 and TIM7) RM0033 Basic timers (TIM6 and TIM7) This section applies to the whole STM32F20x and STM32F21x family, unless otherwise specified. 16.1 TIM6 and TIM7 introduction The basic timers TIM6 and TIM7 consist of a 16-bit auto-reload counter driven by a programmable prescaler.
Page 485: Tim6 And Tim7 Functional Description
RM0033 Basic timers (TIM6 and TIM7) 16.3 TIM6 and TIM7 functional description 16.3.1 Time-base unit The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
Page 486: Figure 183. Counter Timing Diagram With Prescaler Division Change From 1 To 2
Basic timers (TIM6 and TIM7) RM0033 Figure 183. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC CNT_EN Timerclock = CK_CNT Counter register FA FB Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31076V3...
Page 487: Counting Mode
RM0033 Basic timers (TIM6 and TIM7) 16.3.2 Counting mode The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An update event can be generate at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
Page 488: Figure 186. Counter Timing Diagram, Internal Clock Divided By 2
Basic timers (TIM6 and TIM7) RM0033 Figure 186. Counter timing diagram, internal clock divided by 2 CK_INT CNT_EN Timerclock = CK_CNT Counter register 0034 0035 0036 0000 0001 0002 0003 Counter overflow Update event (UEV) Update interrupt flag (UIF) MS35835V1 Figure 187.
Page 489: Clock Source
RM0033 Basic timers (TIM6 and TIM7) Figure 189. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) CK_INT CNT_EN Timerclock = CK_CNT Counter register 32 33 34 35 36 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload register Write a new value in TIMx_ARR...
Page 490: Debug Mode
Basic timers (TIM6 and TIM7) RM0033 Figure 191. Control circuit in normal mode, internal clock divided by 1 Internal clock CEN=CNT_EN CNT_INIT Counter clock = CK_CNT = CK_PSC Counter register 33 34 35 36 03 04 05 MS31085V2 16.3.4 Debug mode ®...
Page 491 RM0033 Basic timers (TIM6 and TIM7) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generates an update interrupt or DMA request if enabled. These events can be: –...
Page 492: Tim6 And Tim7 Control Register 2 (Timx_Cr2)
Basic timers (TIM6 and TIM7) RM0033 16.4.2 TIM6 and TIM7 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 MMS[2:0] Reserved Reserved Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 MMS[2:0]: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO).
Page 493: Tim6 And Tim7 Status Register (Timx_Sr)
RM0033 Basic timers (TIM6 and TIM7) 16.4.4 TIM6 and TIM7 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 Reserved rc_w0 Bits 15:1 Reserved, must be kept at reset value. Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred.
Page 494: Tim6 And Tim7 Prescaler (Timx_Psc)
Basic timers (TIM6 and TIM7) RM0033 16.4.7 TIM6 and TIM7 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1). CK_PSC PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).
Page 495: Tim6 And Tim7 Register Map
RM0033 Basic timers (TIM6 and TIM7) 16.4.9 TIM6 and TIM7 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below. Table 68. TIM6 and TIM7 register map and reset values Offset Register TIMx_CR1 0x00 Reserved Reset value TIMx_CR2...
Page 496: Independent Watchdog (Iwdg)
Independent watchdog (IWDG) RM0033 Independent watchdog (IWDG) This section applies to the whole STM32F20x and STM32F21x family, unless otherwise specified. 17.1 IWDG introduction The devices have two embedded watchdog peripherals which offer a combination of high safety level, timing accuracy and flexibility of use. Both watchdog peripherals (Independent and Window) serve to detect and resolve malfunctions due to software failure, and to trigger system reset or an interrupt (window watchdog only) when the counter reaches a given timeout value.
Page 497: Register Access Protection
RM0033 Independent watchdog (IWDG) 17.3.2 Register access protection Write access to the IWDG_PR and IWDG_RLR registers is protected. To modify them, first write the code 0x5555 in the IWDG_KR register. A write access to this register with a different value will break the sequence and register access will be protected again. This implies that it is the case of the reload operation (writing 0xAAAA).
Page 498: Iwdg Registers
Independent watchdog (IWDG) RM0033 17.4 IWDG registers Refer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). 17.4.1 Key register (IWDG_KR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...
Page 499: Reload Register (Iwdg_Rlr)
RM0033 Independent watchdog (IWDG) 17.4.3 Reload register (IWDG_RLR) Address offset: 0x08 Reset value: 0x0000 0FFF (reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RL[11:0] Reserved rw rw rw...
Page 500: Iwdg Register Map
Independent watchdog (IWDG) RM0033 17.4.5 IWDG register map The following table gives the IWDG register map and reset values. Table 70. IWDG register map and reset values Offset Register IWDG_KR KEY[15:0] Reserved 0x00 Reset value IWDG_PR PR[2:0] Reserved 0x04 Reset value IWDG_RLR RL[11:0] Reserved...
Page 501: Window Watchdog (Wwdg)
RM0033 Window watchdog (WWDG) Window watchdog (WWDG) This section applies to the whole STM32F20x and STM32F21x family, unless otherwise specified. 18.1 WWDG introduction The window watchdog is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence.
Page 502: Figure 193. Watchdog Block Diagram
Window watchdog (WWDG) RM0033 Figure 193. Watchdog block diagram The application program must write in the WWDG_CR register at regular intervals during normal operation to prevent an MCU reset. This operation must occur only when the counter value is lower than the window register value. The value to be stored in the WWDG_CR register must be between 0xFF and 0xC0.
Page 503: How To Program The Watchdog Timeout
RM0033 Window watchdog (WWDG) In some applications, the EWI interrupt can be used to manage a software system check and/or system recovery/graceful degradation, without generating a WWDG reset. In this case, the corresponding interrupt service routine (ISR) should reload the WWDG counter to avoid the WWDG reset, then trigger the required actions.
Page 504: Debug Mode
Window watchdog (WWDG) RM0033 As an example, let us assume APB1 frequency is equal to 24 MHz, WDGTB[1:0] is set to 3 and T[5:0] is set to 63: ⁄ × × × t WWDG 24000 4096 21.85ms Refer to Table 71 for the minimum and maximum values of the t WWDG Table 71.
Page 505: Wwdg Registers
RM0033 Window watchdog (WWDG) 18.6 WWDG registers Refer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). 18.6.1 Control register (WWDG_CR) Address offset: 0x00 Reset value: 0x0000 007F Reserved...
Page 506: Configuration Register (Wwdg_Cfr)
Window watchdog (WWDG) RM0033 18.6.2 Configuration register (WWDG_CFR) Address offset: 0x04 Reset value: 0x0000 007F Reserved WDGTB[1:0] W[6:0] Reserved Bit 31:10 Reserved, must be kept at reset value. Bit 9 EWI: Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset.
Page 507: Wwdg Register Map
RM0033 Window watchdog (WWDG) 18.6.4 WWDG register map The following table gives the WWDG register map and reset values. Table 72. WWDG register map and reset values Offset Register WWDG_CR T[6:0] 0x00 Reserved Reset value WWDG_CFR W[6:0] 0x04 Reserved Reset value WWDG_SR 0x08 Reserved...
Page 508: Cryptographic Processor (Cryp)
Cryptographic processor (CRYP) RM0033 Cryptographic processor (CRYP) This section applies to the whole STM32F20x and STM32F21x family, unless otherwise specified. 19.1 CRYP introduction The cryptographic processor can be used to both encipher and decipher data using the DES, Triple-DES or AES (128, 192, or 256) algorithms. It is a fully compliant implementation of the following standards: •...
Page 509 RM0033 Cryptographic processor (CRYP) • DES/TDES – Direct implementation of simple DES algorithms (a single key, K1, is used) – Supports the ECB and CBC chaining algorithms – Supports 64-, 128- and 192-bit keys (including parity) – 2 × 32-bit initialization vectors (IV) used in the CBC mode –...
Page 510: Cryp Functional Description
Cryptographic processor (CRYP) RM0033 19.3 CRYP functional description The cryptographic processor implements a Triple-DES (TDES, that also supports DES) core and an AES cryptographic core. Section 19.3.1 Section 19.3.2 provide details on these cores. Since the TDES and the AES algorithms use block ciphers, incomplete input data blocks have to be padded prior to encryption (extra bits should be appended to the trailing end of the data string).
Page 511 RM0033 Cryptographic processor (CRYP) According to the mode implemented, the resultant output block is used to calculate the ciphertext. Note that the outputs of the intermediate DEA stages is never revealed outside the cryptographic boundary. The TDES allows three different keying options: •...
Page 512: Figure 196. Des/Tdes-Ecb Mode Encryption
Cryptographic processor (CRYP) RM0033 Figure 196. DES/TDES-ECB mode encryption IN FIFO plaintext P P, 64 bits DATATYPE swapping DEA, encrypt DEA, decrypt DEA, encrypt O, 64 bits DATATYPE swapping C, 64 bits OUT FIFO ciphertext C ai16069b 1. K: key; C: cipher text; I: input block; O: output block; P: plain text. Figure 197.
Page 513 RM0033 Cryptographic processor (CRYP) DES and TDES Cipher block chaining (DES/TDES-CBC) mode • DES/TDES-CBC mode encryption Figure 198 illustrates the DES and Triple-DES Cipher block chaining (DES/TDES- CBC) mode encryption. This mode begins by dividing a plaintext message into 64-bit data blocks.
Page 514: Figure 198. Des/Tdes-Cbc Mode Encryption
Cryptographic processor (CRYP) RM0033 Figure 198. DES/TDES-CBC mode encryption IN FIFO plaintext P P, 64 bits DATATYPE swapping AHB2 data write (before CRYP is enabled) Ps, 64 bits IV0(L/R) I, 64 bits DEA, encrypt O is written back into IV at the DEA, decrypt same time as it is pushed into...
Page 515: Aes Cryptographic Core
RM0033 Cryptographic processor (CRYP) Figure 199. DES/TDES-CBC mode decryption IN FIFO ciphertext C C, 64 bits DATATYPE swapping I, 64 bits DEA, decrypt I is written back into IV at the same time as P is pushed into DEA, encrypt the OUT FIFO DEA, decrypt AHB2 data write...
Page 516: Figure 200. Aes-Ecb Mode Encryption
Cryptographic processor (CRYP) RM0033 ECB decryption, AES-CBC encryption and AES-CBC decryption.This reference manual only gives a brief explanation of each mode. AES Electronic codebook (AES-ECB) mode • AES-ECB mode encryption Figure 200 illustrates the AES Electronic codebook (AES-ECB) mode encryption. In AES-ECB encryption, a 128- bit plaintext data block (P) is used after bit/byte/half- word swapping (refer to Section 19.3.3: Data type on page...
Page 517: Figure 201. Aes-Ecb Mode Decryption
RM0033 Cryptographic processor (CRYP) Figure 201. AES-ECB mode decryption IN FIFO ciphertext C C, 128 bits DATATYPE swapping I, 128 bits 128/192 or 256 K 0...3 (1) AEA, decrypt O, 128 bits DATATYPE swapping P, 128 bits OUT FIFO plaintext P MS19023V1 1.
Page 518: Figure 202. Aes-Cbc Mode Encryption
Cryptographic processor (CRYP) RM0033 block of data.) The AES-CBC decryption process continues in this manner until the last complete ciphertext block has been decrypted. Ciphertext representing a partial data block must be decrypted in a manner specified for the application. Figure 202.
Page 519: Figure 203. Aes-Cbc Mode Decryption
RM0033 Cryptographic processor (CRYP) Figure 203. AES-CBC mode decryption IN FIFO ciphertext C C, 128 bits DATATYPE swapping I, 128 bits 128, 192 or 256 AEA, decrypt K 0... I is written back into IV at the same time as P is pushed into the OUT FIFO AHB2 data write (before CRYP...
Page 520: Figure 204. Aes-Ctr Mode Encryption
Cryptographic processor (CRYP) RM0033 Figure 204 Figure 205 illustrate AES-CTR encryption and decryption, respectively. Figure 204. AES-CTR mode encryption IN FIFO plaintext P P, 128 bits DATATYPE AHB2 data write swapping (before CRYP is enabled) IV0...1(L/R) Ps, 128 bits I, 128 bits 128, 192 or 256 AEA, encrypt...
Page 521: Figure 205. Aes-Ctr Mode Decryption
RM0033 Cryptographic processor (CRYP) Figure 205. AES-CTR mode decryption IN FIFO ciphertext P C, 128 bits DATATYPE AHB2 data write swapping (before CRYP is enabled) IV0...1(L/R) Cs, 128 bits I, 128 bits 128, 192 or 256 AEA, encrypt K0...3 (I + 1) is written O, 128 bits back into IV at same time...
Page 522: Data Type
Cryptographic processor (CRYP) RM0033 19.3.3 Data type Data enter the CRYP processor 32 bits (word) at a time as they are written into the CRYP_DIN register. The principle of the DES is that streams of data are processed 64 bits by 64 bits and, for each 64-bit block, the bits are numbered from M1 to M64, with M1 the left- most bit and M64 the right-most bit of the block.
Page 523 RM0033 Cryptographic processor (CRYP) Table 74. Data types DATATYPE in System memory data Swapping performed CRYP_CR (plaintext or cypher) Example: TDES block value 0xABCD77206973FE01 is represented in system memory as: system memory Byte (8-bit) swapping TDES block size = 64bit = 2x 32 bit 20 77 CD AB 0xAB CD...
Page 524: Initialization Vectors - Cryp_Iv0
Cryptographic processor (CRYP) RM0033 Figure 207. 64-bit block construction according to DATATYPE DATATYPE = 11b bit swapping operation bit 31 bit 30 bit 2 bit 1 bit 0 second word written into the CRYP_DIN register first word written into the CRYP_DIN register IN FIFO bit 31 bit 30...
Page 525 RM0033 Cryptographic processor (CRYP) During the DES or TDES CBC encryption, the CRYP_IV0(L/R) bits are XORed with the 64- bit data block popped off the IN FIFO after swapping (according to the DATATYPE value), that is, with the M1...64 bits of the data block. When the output of the DEA3 block is available, it is copied back into the CRYP_IV0(L/R) vector, and this new content is XORed with the next 64-bit data block popped off the IN FIFO, and so on.
Page 526: Cryp Busy State
Cryptographic processor (CRYP) RM0033 Figure 208. Initialization vectors use in the TDES-CBC encryption TDES-CBC en cryption ex ample, DATATYPE = 11b second word written into the CRYP_DIN register bit 31 bit 30 bit 2 bit 1 bit 0 bit 31 bit 30 bit 2 bit 1...
Page 527: Procedure To Perform An Encryption Or A Decryption
RM0033 Cryptographic processor (CRYP) the CBC, CTR mode, the initialization vectors CRYP_IVx(L/R)R (x = 0..3) are updated as well. A write operation to the key registers (CRYP_Kx(L/R)R, x = 0..3), the initialization registers (CRYP_IVx(L/R)R, x = 0..3), or to bits [9:2] in the CRYP_CR register are ignored when the cryptographic processor is busy (bit BUSY = 1b in the CRYP_SR register), and the registers are not modified.
Page 528: Context Swapping
Cryptographic processor (CRYP) RM0033 the DES/TDES. The DMA should be configured to set an interrupt on transfer completion of the output data to indicate that the processing is finished. Enable the cryptographic processor by writing the CRYPEN bit to 1. Enable the DMA requests by setting the DIEN and DOEN bits in the CRYP_DMACR register.
Page 529 RM0033 Cryptographic processor (CRYP) Case of the AES and DES Context saving Stop DMA transfers on the IN FIFO by clearing the DIEN bit in the CRYP_DMACR register. Wait until both the IN and OUT FIFOs are empty (IFEM=1 and OFNE=0 in the CRYP_SR register) and the BUSY bit is cleared.
Page 530: Cryp Interrupts
Cryptographic processor (CRYP) RM0033 the IN FIFO that have not been processed and save them in the memory until the FIFO is empty. Configure and execute the other processing. Context restoration Configure the processor as in Section 19.3.6: Procedure to perform an encryption or a decryption on page 527, Initialization...
Page 531: Cryp Dma Interface
RM0033 Cryptographic processor (CRYP) Figure 209. CRYP interrupt mapping diagram CRYPEN IN FIFO Interrupt - INMIS INRIS INMIS INIM Global Interrupt OUTRIS OUTMIS OUT FIFO Interrupt - OUTMIS OUTIM ai16077 19.5 CRYP DMA interface The cryptographic processor provides an interface to connect to the DMA controller. The DMA operation is controlled through the CRYP DMA control register, CRYP_DMACR.
Page 532 Cryptographic processor (CRYP) RM0033 Bits 31:18 Reserved, must be kept at reset value Bits 17:16 Reserved, must be kept at reset value Bit 15 CRYPEN: Cryptographic processor enable 0: CRYP processor is disabled 1: CRYP processor is enabled Note: The CRYPEN bit is automatically cleared by hardware when the key preparation process ends (ALGOMODE=111b) or GCM_CCM init Phase Bit 14 FFLUSH: FIFO flush When CRYPEN = 0, writing this bit to 1 flushes the IN and OUT FIFOs (that is...
Page 533 RM0033 Cryptographic processor (CRYP) Bits 5:3 ALGOMODE[2:0]: Algorithm mode 000: TDES-ECB (triple-DES Electronic codebook): no feedback between blocks of data. Initialization vectors (CRYP_IV0(L/R)) are not used, three key vectors (K1, K2, and K3) are used (K0 is not used). 001: TDES-CBC (triple-DES Cipher block chaining): output block is XORed with the subsequent input block before its entry into the algorithm.
Page 534: Cryp Status Register (Cryp_Sr)
Cryptographic processor (CRYP) RM0033 19.6.2 CRYP status register (CRYP_SR) Address offset: 0x04 Reset value: 0x0000 0003 Reserved BUSY OFFU OFNE IFNF IFEM Reserved Bits 31:5 Reserved, must be kept at reset value Bit 4 BUSY: Busy bit 0: The CRYP Core is not processing any data. The reason is either that: –...
Page 535: Cryp Data Input Register (Cryp_Din)
RM0033 Cryptographic processor (CRYP) 19.6.3 CRYP data input register (CRYP_DIN) Address offset: 0x08 Reset value: 0x0000 0000 The CRYP_DIN register is the data input register. It is 32-bit wide. It is used to enter up to four 64-bit (TDES) or two 128-bit (AES) plaintext (when encrypting) or ciphertext (when decrypting) blocks into the input FIFO, one 32-bit word at a time.
Page 536: Cryp Data Output Register (Cryp_Dout)
Cryptographic processor (CRYP) RM0033 19.6.4 CRYP data output register (CRYP_DOUT) Address offset: 0x0C Reset value: 0x0000 0000 The CRYP_DOUT register is the data output register. It is read-only and 32-bit wide. It is used to retrieve up to four 64-bit (TDES mode) or two 128-bit (AES mode) ciphertext (when encrypting) or plaintext (when decrypting) blocks from the output FIFO, one 32-bit word at a time.
Page 537: Cryp Dma Control Register (Cryp_Dmacr)
RM0033 Cryptographic processor (CRYP) 19.6.5 CRYP DMA control register (CRYP_DMACR) Address offset: 0x10 Reset value: 0x0000 0000 Reserved DOEN DIEN Reserved Bits 31:2 Reserved, must be kept at reset value Bit 1 DOEN: DMA output enable 0: DMA for outgoing data transfer is disabled 1: DMA for outgoing data transfer is enabled Bit 0 DIEN: DMA input enable 0: DMA for incoming data transfer is disabled...
Page 538: Cryp Raw Interrupt Status Register (Cryp_Risr)
Cryptographic processor (CRYP) RM0033 19.6.7 CRYP raw interrupt status register (CRYP_RISR) Address offset: 0x18 Reset value: 0x0000 0001 The CRYP_RISR register is the raw interrupt status register. It is a read-only register. On a read, this register gives the current raw status of the corresponding interrupt prior to masking.
Page 539: Cryp Key Registers (Cryp_K0
RM0033 Cryptographic processor (CRYP) Bits 31:2 Reserved, must be kept at reset value Bit 1 OUTMIS: Output FIFO service masked interrupt status Gives the interrupt state after masking of the output FIFO service interrupt. 0: Interrupt not pending 1: Interrupt pending Bit 0 INMIS: Input FIFO service masked interrupt status Gives the interrupt state after masking of the input FIFO service interrupt.
Page 540 Cryptographic processor (CRYP) RM0033 CRYP_K1LR (address offset: 0x28) k1.1 k1.2 k1.3 k1.4 k1.5 k1.6 k1.7 k1.8 k1.9 k1.10 k1.11 k1.12 k1.13 k1.14 k1.15 k1.16 b191 b190 b189 b188 b187 b186 b185 b184 b183 b182 b181 b180 b179 b178 b177 b176 k1.17 k1.18 k1.19...
Page 541: Cryp Initialization Vector Registers (Cryp_Iv0
RM0033 Cryptographic processor (CRYP) CRYP_K3RR (address offset: 0x3C) k3.33 k3.34 k3.35 k3.36 k3.37 k3.38 k3.39 k3.40 k3.41 k3.42 k3.43 k3.44 k3.45 k3.46 k3.47 k3.48 k3.49 k3.50 k3.51 k3.52 k3.53 k3.54 k3.55 k3.56 k3.57 k3.58 k3.59 k3.60 k3.61 k3.62 k3.63 k3.64 Note: Write accesses to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register).
Page 542: Cryp Register Map
Cryptographic processor (CRYP) RM0033 CRYP_IV1LR (address offset: 0x48) IV64 IV65 IV66 IV67 IV68 IV69 IV70 IV71 IV72 IV73 IV74 IV75 IV76 IV77 IV78 IV79 IV80 IV81 IV82 IV83 IV84 IV85 IV86 IV87 IV88 IV89 IV90 IV91 IV92 IV93 IV94 IV95 CRYP_IV1RR (address offset: 0x4C) IV96 IV97...
Page 543 RM0033 Cryptographic processor (CRYP) Table 75. CRYP register map and reset values (continued) Register Offset name and reset value CRYP_IMSC 0x14 Reserved Reset value CRYP_RISR 0x18 Reserved Reset value CRYP_MISR 0x1C Reserved Reset value CRYP_K0LR CRYP_K0LR 0x20 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_K0RR CRYP_K0RR 0x24...
Page 544: Random Number Generator (Rng)
Random number generator (RNG) RM0033 Random number generator (RNG) This section applies to the whole STM32F20x and STM32F21x family, unless otherwise specified. 20.1 RNG introduction The RNG processor is a random number generator, based on a continuous analog noise, that provides a random 32-bit value to the host when read. The RNG passed the FIPS PUB 140-2 (2001 October 10) tests with a success ratio of 99%.
Page 545: Operation
RM0033 Random number generator (RNG) The analog circuit is made of several ring oscillators whose outputs are XORed to generate the seeds. The RNG_LFSR is clocked by a dedicated clock (RNG_CLK) at a constant frequency, so that the quality of the random number is independent of the HCLK frequency. The contents of the RNG_LFSR are transferred into the data register (RNG_DR) when a significant number of seeds have been introduced into the RNG_LFSR.
Page 546: Rng Control Register (Rng_Cr)
Random number generator (RNG) RM0033 20.4.1 RNG control register (RNG_CR) Address offset: 0x00 Reset value: 0x0000 0000 Reserved RNGEN Reserved Reserved Bits 31:4 Reserved, must be kept at reset value Bit 3 IE: Interrupt enable 0: RNG Interrupt is disabled 1: RNG Interrupt is enabled.
Page 547: Rng Data Register (Rng_Dr)
RM0033 Random number generator (RNG) Bit 2 SECS: Seed error current status 0: No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered. 1: One of the following faulty sequences has been detected: –...
Page 548: Rng Register Map
Random number generator (RNG) RM0033 20.4.4 RNG register map Table 76 gives the RNG register map and reset values. Table 76. RNG register map and reset map Register size Register name Offset reset value RNG_CR 0x00 Reserved 0x0000000 RNG_SR 0x04 Reserved 0x0000000 RNG_DR...
Page 549: Hash Processor (Hash)
RM0033 Hash processor (HASH) Hash processor (HASH) This section applies only to STM32F21x devices. 21.1 HASH introduction The hash processor is a fully compliant implementation of the secure hash algorithm (SHA-1), the MD5 (message-digest algorithm 5) hash algorithm and the HMAC (keyed-hash message authentication code) algorithm suitable for a variety of applications.
Page 550: Figure 211. Block Diagram
Hash processor (HASH) RM0033 Figure 211. Block diagram 32-bit AHB2 bus IN buffer Data register Control and status HASH_DIN registers write into HASH_DIN or write DCAL bit to 1 Interrupt registers or 1 complete block transferred by the DMA HASH_IMR 16 ×...
Page 551: Figure 212. Block Diagram
RM0033 Hash processor (HASH) Figure 212. Block diagram 32-bit AHB2 bus IN buffer Data register Control and status HASH_DIN registers write into HASH_DIN or write DCAL bit to 1 Interrupt registers or 1 complete block transferred by the DMA HASH_IMR 16 ×...
Page 552: Duration Of The Processing
Hash processor (HASH) RM0033 bits can be grouped as bytes (8 bits) or words (32 bits) (but some implementations also use half-words (16 bits), and implicitly, uses the big-endian byte (half-word) ordering. This convention is mainly important for padding (see Section 1.3.4: Message padding on page 12).
Page 553: Figure 213. Bit, Byte And Half-Word Swapping
RM0033 Hash processor (HASH) Figure 213. Bit, byte and half-word swapping A-In case of binary data hash, all bits should be swapped as below Bit s w a p pi n g ope r a t i o n D A T A TYPE = bx 1 1 Bits entred with little-Endian format H A S H_D I N b i t 3 1...
Page 554: Message Digest Computing
Hash processor (HASH) RM0033 The least significant bit of the message has to be at position 0 (right) in the first word entered into the hash processor, the 32nd bit of the bit string has to be at position 0 in the second word entered into the hash processor and so on.
Page 555: Message Padding
RM0033 Hash processor (HASH) 21.3.4 Message padding Message padding consists in appending a “1” followed by m “0”s followed by a 64-bit integer to the end of the original message to produce a padded message block of length 512. The “1”...
Page 556: Hash Operation
Hash processor (HASH) RM0033 21.3.5 Hash operation The hash function (SHA-1, and MD5) is selected when the INIT bit is written to ‘1’ in the HASH_CR register while the MODE bit is at ‘0’ in HASH_CR. The algorithm (SHA-1, or MD5) is selected at the same time (that is when the INIT bit is set) using the ALGO bits.
Page 557: Context Swapping
RM0033 Hash processor (HASH) Note: The computation latency of the HMAC primitive depends on the lengths of the keys and message. You could the HMAC as two nested underlying hash functions with the same key length (long or short). 21.3.7 Context swapping It is possible to interrupt a hash/HMAC process to perform another processing with a higher priority, and to complete the interrupted process later on, when the higher-priority task is...
Page 558: Hash Interrupt
Hash processor (HASH) RM0033 Procedure where the data are loaded by DMA In this case it is not possible to predict if a DMA transfer is in progress or if the process is ongoing. Thus, you must stop the DMA transfers, then wait until the HASH is ready in order to interrupt the processing of a message.
Page 559: Hash Registers
RM0033 Hash processor (HASH) 21.4 HASH registers The HASH core is associated with several control and status registers and five message digest registers. All these registers are accessible through word accesses only, else an AHB error is generated. 21.4.1 HASH control register (HASH_CR) Address offset: 0x00 Reset value: 0x0000 0000 LKEY...
Page 560 Hash processor (HASH) RM0033 Bits 11:8 NBW: Number of words already pushed This bitfield reflects the number of words in the message that have already been pushed into the IN FIFO. NBW increments (+1) when a write access is performed to the HASH_DIN register while DINNE = 1.
Page 561 RM0033 Hash processor (HASH) Bit 3 DMAE: DMA enable 0: DMA transfers disabled 1: DMA transfers enabled. A DMA request is sent as soon as the HASH core is ready to receive data. Note: 1: This bit is cleared by hardware when the DMA asserts the DMA terminal count signal (while transferring the last data of the message).
Page 562: Hash Data Input Register (Hash_Din)
Hash processor (HASH) RM0033 21.4.2 HASH data input register (HASH_DIN) Address offset: 0x04 Reset value: 0x0000 0000 HASH_DIN is the data input register. It is 32-bit wide. It is used to enter the message by blocks of 512 bits. When the HASH_DIN register is written to, the value presented on the AHB databus is ‘pushed’...
Page 563: Hash Start Register (Hash_Str)
RM0033 Hash processor (HASH) 21.4.3 HASH start register (HASH_STR) Address offset: 0x08 Reset value: 0x0000 0000 The HASH_STR register has two functions: • It is used to define the number of valid bits in the last word of the message entered in the hash processor (that is the number of valid least significant bits in the last data written into the HASH_DIN register) •...
Page 564: Hash Digest Registers (Hash_Hr0
Hash processor (HASH) RM0033 21.4.4 HASH digest registers (HASH_HR0..4) Address offset: 0x0C to 0x1C Reset value: 0x0000 0000 These registers contain the message digest result named as: H0, H1, H2, H3 and H4, respectively, in the SHA1 algorithm description A, B, C and D, respectively, in the MD5 algorithm description Note that in this case, the HASH_H4 is not used, and is read as zero.
Page 565: Hash Interrupt Enable Register (Hash_Imr)
RM0033 Hash processor (HASH) HASH_HR4 Address offset: 0x1C Note: When starting a digest computation for a new bit stream (by writing the INIT bit to 1), these registers assume their reset values. 21.4.5 HASH interrupt enable register (HASH_IMR) Address offset: 0x20 Reset value: 0x0000 0000 Reserved DCIE...
Page 566: Hash Status Register (Hash_Sr)
Hash processor (HASH) RM0033 21.4.6 HASH status register (HASH_SR) Address offset: 0x24 Reset value: 0x0000 0001 Reserved BUSY DMAS DCIS DINIS Reserved rc_w0 rc_w0 Bits 31:4 Reserved, forced by hardware to 0. Bit 3 BUSY: Busy bit 0: No block is currently being processed 1: The hash core is processing a block of data Bit 2 DMAS: DMA Status This bit provides information on the DMA interface activity.
Page 567: Hash Context Swap Registers (Hash_Csrx)
RM0033 Hash processor (HASH) 21.4.7 HASH context swap registers (HASH_CSRx) Address offset: 0x0F8 to 0x1C0 • For HASH_CSR0 register: Reset value is 0x0000 0002. • For others registers: Reset value is 0x0000 0000 These registers contain the complete internal register states of the hash processor, and are useful when a context swap has to be done because a high-priority task has to use the hash processor while it is already in use by another task.
Page 568: Hash Register Map
Hash processor (HASH) RM0033 21.4.8 HASH register map Table 9 gives the summary HASH register map and reset values. Table 77. HASH register map and reset values Register size Register name Offset reset value HASH_CR 0x00 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 HASH_DIN DATAIN 0x04...
Page 569 RM0033 Hash processor (HASH) Table 77. HASH register map and reset values (continued) Register size Register name Offset reset value HASH_HR2 0x318 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HASH_HR3 0x31C Reset value...
Page 570: Real-Time Clock (Rtc)
Real-time clock (RTC) RM0033 Real-time clock (RTC) This section applies to the whole STM32F20x and STM32F21x family, unless otherwise specified. 22.1 Introduction The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time- of-day clock/calendar, two programmable alarm interrupts, and a periodic programmable wakeup flag with interrupt capability.
Page 571: Rtc Main Features
RM0033 Real-time clock (RTC) 22.2 RTC main features The RTC unit main features are the following (see Figure 215: RTC block diagram): • Calendar with seconds, minutes, hours (12 or 24 format), day (day of week), date (day of month), month, and year. •...
Page 572: Rtc Functional Description
Real-time clock (RTC) RM0033 Figure 215. RTC block diagram AFI_TIMESTAMP Time stamp Time stamp flag registe rs AFO_CALIB (512 Hz) Output RTC_AFO Alarm control (RTC_ALRMAR ALRAF RTC_AF1 RTC_AFI register) ck_apre ck_spre RTCCLK (default 256 Hz) (default 1 Hz) LSE (32.768 Hz) Calendar HSE (1 MHz max) RTC_PRER...
Page 573: Real-Time Clock And Calendar
RM0033 Real-time clock (RTC) is given by the following formula: ck_spre RTCCLK ----------------------------------------------------------------------------------------------- CK_SPRE × PREDIV_S PREDIV_A The ck_spre clock can be used either to update the calendar or as timebase for the 16-bit wakeup auto-reload timer. To obtain short timeout periods, the 16-bit wakeup auto-reload timer can also run with the RTCCLK divided by the programmable 4-bit asynchronous prescaler (see Section 22.3.4: Periodic auto-wakeup...
Page 574: Rtc Initialization And Configuration
Real-time clock (RTC) RM0033 The wakeup timer clock input can be: • RTC clock (RTCCLK) divided by 2, 4, 8, or 16. When RTCCLK is LSE(32.768kHz), this allows configuring the wakeup interrupt period from 122 µs to 32 s, with a resolution down to 61µs. •...
Page 575 RM0033 Real-time clock (RTC) Calendar initialization and configuration To program the initial time and date calendar values, including the time format and the prescaler configuration, the following sequence is required: Set INIT bit to 1 in the RTC_ISR register to enter initialization mode. In this mode, the calendar counter is stopped and its value can be updated.
Page 576: Reading The Calendar
Real-time clock (RTC) RM0033 Programming the wakeup timer The following sequence is required to configure or change the wakeup timer auto-reload value (WUT[15:0] in RTC_WUTR): Clear WUTE in RTC_CR to disable the wakeup timer. Poll WUTWF until it is set in RTC_ISR to make sure the access to wakeup auto-reload counter and to WUCKSEL[2:0] bits is allowed.
Page 577: Rtc Reference Clock Detection
RM0033 Real-time clock (RTC) the RTC backup registers (RTC_BKPxR), the wakeup timer register (RTC_WUTR), the Alarm A and Alarm B registers (RTC_ALRMAR and RTC_ALRMBR). In addition, when the RTC is clocked by the LSE, it goes on running under system reset if the reset source is different from a backup domain reset one.
Page 578: Rtc Coarse Digital Calibration
Real-time clock (RTC) RM0033 22.3.9 RTC coarse digital calibration The coarse digital calibration can be used to compensate crystal inaccuracy by adding (positive calibration) or masking (negative calibration) clock cycles at the output of the asynchronous prescaler (ck_apre). Positive and negative calibration are selected by setting the DCS bit in RTC_CALIBR register to ‘0’...
Page 579: Tamper Detection
RM0033 Real-time clock (RTC) mapped. When a timestamp event occurs, the timestamp flag bit (TSF) in RTC_ISR register is set. By setting the TSIE bit in the RTC_CR register, an interrupt is generated when a timestamp event occurs. If a new timestamp event is detected while the timestamp flag (TSF) is already set, the timestamp overflow flag (TSOVF) flag is set and the timestamp registers (RTC_TSTR and RTC_TSDR) maintain the results of the previous event.
Page 580: Calibration Clock Output
Real-time clock (RTC) RM0033 Edge detection on tamper inputs TAMPER pins generate tamper detection events when either a rising edge is observed or an falling edge is observed depending on the corresponding TAMPxTRG bit. The internal pull-up resistors on the TAMPER inputs are deactivated when edge detection is selected. Caution: To avoid losing tamper detection events, the signal used for edge detection is logically ANDed with TAMPxE in order to detect a tamper detection event in case it occurs before the...
Page 581: Alarm Output
RM0033 Real-time clock (RTC) 22.3.13 Alarm output Three functions can be selected on Alarm output: ALRAF, ALRBF and WUTF. These functions reflect the contents of the corresponding flags in the RTC_ISR register. The OSEL[1:0] control bits in the RTC_CR register are used to activate the alarm alternate function output (AFO_ALARM) in RTC_AF1, and to select the function which is output on AFO_ALARM.
Page 582: Table 79. Interrupt Control Bits
Real-time clock (RTC) RM0033 To enable the RTC Tamper interrupt, the following sequence is required: Configure and enable the EXTI Line 21 in interrupt mode and select the rising edge sensitivity. Configure and Enable the TAMP_STAMP IRQ channel in the NVIC. Configure the RTC to detect the RTC tamper event.
Page 583: Rtc Registers
Bits 14:12 MNT[2:0]: Minute tens in BCD format Bit 11:8 MNU[3:0]: Minute units in BCD format Bit 7 Reserved, must be kept at reset value. Bits 6:4 ST[2:0]: Second tens in BCD format Bits 3:0 SU[3:0]: Second units in BCD format Note: This register is write protected.
Page 584: Rtc Date Register (Rtc_Dr)
Real-time clock (RTC) RM0033 22.6.2 RTC date register (RTC_DR) The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page 575 Reading the calendar on page 576.
Page 585: Rtc Control Register (Rtc_Cr)
RM0033 Real-time clock (RTC) 22.6.3 RTC control register (RTC_CR) Address offset: 0x08 Backup domain reset value: 0x0000 0000 System reset: not affected OSEL[1:0] SUB1H ADD1H Reserved Res. TSIE WUTIE ALRBIE ALRAIE WUTE ALRBE ALRAE Res. REFCKON TSEDGE WUCKSEL[2:0] Bits 31:24 Reserved, must be kept at reset value. Bit 23 COE: Calibration output enable This bit enables the AFO_CALIB RTC output 0: Calibration output disabled...
Page 586 Real-time clock (RTC) RM0033 Bit 14 WUTIE: Wakeup timer interrupt enable 0: Wakeup timer interrupt disabled 1: Wakeup timer interrupt enabled Bit 13 ALRBIE: Alarm B interrupt enable 0: Alarm B Interrupt disable 1: Alarm B Interrupt enable Bit 12 ALRAIE: Alarm A interrupt enable 0: Alarm A interrupt disabled 1: Alarm A interrupt enabled Bit 11 TSE: Time stamp enable...
Page 587: Rtc Initialization And Status Register (Rtc_Isr)
RM0033 Real-time clock (RTC) Note: WUT = Wakeup unit counter value. WUT = (0x0000 to 0xFFFF) + 0x10000 added when WUCKSEL[2:1 = 11]. Bits 7, 6 and 4 of this register can be written in initialization mode only (RTC_ISR/INITF = 1). Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1.
Page 588 Real-time clock (RTC) RM0033 Bit 8 ALRAF: Alarm A flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR). This flag is cleared by software by writing 0. Bit 7 INIT: Initialization mode 0: Free running mode 1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER).
Page 589: Rtc Prescaler Register (Rtc_Prer)
RM0033 Real-time clock (RTC) Note: The ALRAF, ALRBF, WUTF and TSF bits are cleared 2 APB clock cycles after programming them to 0. This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure is described in RTC register write protection on page 574.
Page 590: Rtc Calibration Register (Rtc_Calibr)
Real-time clock (RTC) RM0033 Bits 31:16 Reserved Bits 15:0 WUT[15:0]: Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer.
Page 591: Rtc Alarm A Register (Rtc_Alrmar)
Bit 7 MSK1: Alarm A seconds mask 0: Alarm A set if the seconds match 1: Seconds don’t care in Alarm A comparison Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. RM0033 Rev 8...
Page 592: Rtc Alarm B Register (Rtc_Alrmbr)
Bit 7 MSK1: Alarm B seconds mask 0: Alarm B set if the seconds match 1: Seconds don’t care in Alarm B comparison Bits 6:4 ST[2:0]: Second tens in BCD format Bits 3:0 SU[3:0]: Second units in BCD format 592/1378...
Page 593: Rtc Write Protection Register (Rtc_Wpr)
Backup domain reset value: 0x0000 0000 System reset: not affected HT[1:0] HU[3:0] Reserved MNT[2:0] MNU[3:0] ST[2:0] SU[3:0] Res. Res. Bits 31:23 Reserved, must be kept at reset value. Bit 22 PM: AM/PM notation 0: AM or 24-hour format 1: PM Bits 21:20 HT[1:0]: Hour tens in BCD format.
Page 594: Rtc Time Stamp Date Register (Rtc_Tsdr)
RM0033 Bits 11:8 MNU[3:0]: Minute units in BCD format. Bit 7 Reserved, must be kept at reset value. Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. Note: The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset.
Page 595: Rtc Tamper And Alternate Function Configuration Register
RM0033 Real-time clock (RTC) 22.6.13 RTC tamper and alternate function configuration register (RTC_TAFCR) Address offset: 0x40 Backup domain reset value: 0x0000 0000 System reset: not affected ALARMOUT TSIN TAMP1 TYPE INSEL Reserved TAMP1 TAMP1 TAMPIE Reserved Bits 31:19 Reserved. Always read as 0. Bit 18 ALARMOUTTYPE: AFO_ALARM output type 0: ALARM_AF0 is an open-drain output 1: ALARM_AF0 is a push-pull output...
Page 596: Rtc Backup Registers (Rtc_Bkpxr)
System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event. 22.6.15 RTC register map Table 80. RTC register map and reset values Offset Register RTC_TR HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0] [1:0] 0x00 Reserved Reset value RTC_DR YT[3:0] YU[3:0] WDU[2:0] MU[3:0]...
Page 597 RM0033 Real-time clock (RTC) Table 80. RTC register map and reset values (continued) Offset Register RTC_ALRMAR DU[3:0] HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0] [1:0] [1:0] 0x1C Reset value RTC_ALRMBR DU[3:0] HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0] [1:0] [1:0] 0x20 Reset value RTC_WPR...
Page 598: Inter-Integrated Circuit (I2C) Interface
Inter-integrated circuit (I2C) interface RM0033 Inter-integrated circuit (I2C) interface This section applies to the whole STM32F20x and STM32F21x family, unless otherwise specified. 23.1 C introduction C (inter-integrated circuit) bus Interface serves as an interface between the microcontroller and the serial I C bus.
Page 599: I 2 C Functional Description
RM0033 Inter-integrated circuit (I2C) interface – 1 Interrupt for successful address/ data communication – 1 Interrupt for error condition • Optional clock stretching • 1-byte buffer with DMA capability • Configurable PEC (packet error checking) generation or verification: – PEC value can be transmitted as last byte in Tx mode –...
Page 600: Figure 216. I2C Bus Protocol
Inter-integrated circuit (I2C) interface RM0033 Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is always transmitted in Master mode. A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter.
Page 601: I2C Slave Mode
RM0033 Inter-integrated circuit (I2C) interface Figure 217. I C block diagram Data register Data Noise Data shift register control filter PEC calculation Comparator Own address register Dual address register Clock Noise PEC register control filter Clock control Register (CCR) Control registers (CR1&CR2) Control Status registers...
Page 602 Inter-integrated circuit (I2C) interface RM0033 Header or address not matched: the interface ignores it and waits for another Start condition. Header matched (10-bit mode only): the interface generates an acknowledge pulse if the ACK bit is set and waits for the 8-bit slave address. Address matched: the interface generates in sequence: •...
Page 603: Figure 218. Transfer Sequence Diagram For Slave Transmitter
RM0033 Inter-integrated circuit (I2C) interface Figure 218. Transfer sequence diagram for slave transmitter 7-bit slave transmitter S Address Data1 Data2 DataN NA P ..EV1 EV3-1 EV3 EV3-2 10-bit slave transmitter S Header Address Header A Data1 ..DataN NA P EV1 EV3_1 EV3-2 Legend: S= Start, S...
Page 604: I2C Master Mode
Inter-integrated circuit (I2C) interface RM0033 Figure 219. Transfer sequence diagram for slave receiver 7-bit slave receiver S Address Data1 Data2 DataN ..10-bit slav e receiver S Header Address Data1 DataN ..Legend: S= Start, S = Repeated Start, P= Stop, A= Acknowledge, EVx= Event (with interrupt if ITEVFEN=1) EV1: ADDR=1, cleared by reading SR1 followed by reading SR2 EV2: RxNE=1 cleared by reading DR register.
Page 605 RM0033 Inter-integrated circuit (I2C) interface SCL master clock generation The CCR bits are used to generate the high and low level of the SCL clock, starting from the generation of the rising and falling edge (respectively). As a slave may stretch the SCL line, the peripheral checks the SCL input from the bus at the end of the time programmed in TRISE bits after rising edge generation.
Page 606 Inter-integrated circuit (I2C) interface RM0033 The master can decide to enter Transmitter or Receiver mode depending on the LSB of the slave address sent. • In 7-bit addressing mode, – To enter Transmitter mode, a master sends the slave address with LSB reset. –...
Page 607: Figure 220. Transfer Sequence Diagram For Master Transmitter
RM0033 Inter-integrated circuit (I2C) interface Figure 220. Transfer sequence diagram for master transmitter 7-bit master transmitter Address Data1 Data2 DataN ..EV6 EV8_1 EV8_2 10-bit master transmitter Header Address Data1 DataN ..EV8_1 EV8_2 Legend: S= Start, S = Repeated Start, P= Stop, A= Acknowledge, EVx= Event (with interrupt if ITEVFEN = 1) EV5: SB=1, cleared by reading SR1 register followed by writing DR register with Address.
Page 608 Inter-integrated circuit (I2C) interface RM0033 Master receiver Following the address transmission and after clearing ADDR, the I C interface enters Master Receiver mode. In this mode the interface receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: An acknowledge pulse if the ACK bit is set The RxNE bit is set and an interrupt is generated if the ITEVFEN and ITBUFEN bits are...
Page 609: Figure 221. Transfer Sequence Diagram For Master Receiver
RM0033 Inter-integrated circuit (I2C) interface Figure 221. Transfer sequence diagram for master receiver 7-bit master receiver Address Data1 Data2 DataN ..EV7_1 10-bit master receiver Header Address Data1 Data2 DataN Header ..EV7_1 Leg end : S= Start, S = Repeated Start, P= Stop, A= Acknowledge, NA= Non-acknowledge, EVx= Event (with interrupt if ITEVFEN=1) EV5: SB=1, cleared by reading SR1 register followed by writing DR register.
Page 610: Error Conditions
Inter-integrated circuit (I2C) interface RM0033 For N >2 -byte reception, from N-2 data reception • Wait until BTF = 1 (data N-2 in DR, data N-1 in shift register, SCL stretched low until data N-2 is read) • Set ACK low •...
Page 611: Sda/Scl Line Control
RM0033 Inter-integrated circuit (I2C) interface Overrun/underrun error (OVR) An overrun error can occur in slave mode when clock stretching is disabled and the I interface is receiving data. The interface has received a byte (RxNE=1) and the data in DR has not been read, before the next byte is received by the interface.
Page 612: Table 81. Smbus Vs. I2C
Inter-integrated circuit (I2C) interface RM0033 Similarities between SMBus and I • 2 wire bus protocol (1 Clk, 1 Data) + SMBus Alert line optional • Master-slave communication, Master provides clock • Multi master capability • SMBus data format similar to I C 7-bit addressing format (Figure 216).
Page 613 RM0033 Inter-integrated circuit (I2C) interface Address resolution protocol (ARP) SMBus slave address conflicts can be resolved by dynamically assigning a new unique address to each slave device. The Address Resolution Protocol (ARP) has the following attributes: • Address assignment uses the standard SMBus physical layer arbitration mechanism •...
Page 614: Dma Requests
Inter-integrated circuit (I2C) interface RM0033 How to use the interface in SMBus mode To switch from I C mode to SMBus mode, the following sequence should be performed. • Set the SMBus bit in the I2C_CR1 register • Configure the SMBTYPE and ENARP bits in the I2C_CR1 register as required for the application If you want to configure the device as a master, follow the Start condition generation procedure in...
Page 615 RM0033 Inter-integrated circuit (I2C) interface Set the I2C_DR register address in the DMA_SxPAR register. The data will be moved to this address from the memory after each TxE event. Set the memory address in the DMA_SxMA0R register (and in DMA_SxMA1R register in the case of a bouble buffer mode).
Page 616: Packet Error Checking
Inter-integrated circuit (I2C) interface RM0033 23.3.8 Packet error checking A PEC calculator has been implemented to improve the reliability of communication. The PEC is calculated by using the C(x) = x + x + 1 CRC-8 polynomial serially on each bit. •...
Page 617: Figure 222. I2C Interrupt Mapping Diagram
RM0033 Inter-integrated circuit (I2C) interface Table 82. I C Interrupt requests (continued) Interrupt event Event flag Enable control bit Bus error BERR Arbitration loss (Master) ARLO Acknowledge failure Overrun/Underrun ITERREN PEC error PECERR Timeout/Tlow error TIMEOUT SMBus Alert SMBALERT Note: SB, ADDR, ADD10, STOPF, BTF, RxNE and TxE are logically ORed on the same interrupt channel.
Page 618: I 2 C Debug Mode
Inter-integrated circuit (I2C) interface RM0033 23.5 C debug mode ® When the microcontroller enters the debug mode (Cortex -M3 core halted), the SMBUS timeout either continues to work normally or stops, depending on the DBG_I2Cx_SMBUS_TIMEOUT configuration bits in the DBG module. For more details, refer to Section 32.16.2: Debug support for timers, watchdog, bxCAN and I C on...
Page 619 RM0033 Inter-integrated circuit (I2C) interface Bit 11 POS: Acknowledge/PEC Position (for data reception) This bit is set and cleared by software and cleared by hardware when PE=0. 0: ACK bit controls the (N)ACK of the current byte being received in the shift register. The PEC bit indicates that current byte in shift register is a PEC.
Page 620: I 2 C Control Register 2 (I2C_Cr2)
Inter-integrated circuit (I2C) interface RM0033 Bit 2 Reserved, must be kept at reset value Bit 1 SMBUS: SMBus mode 0: I C mode 1: SMBus mode Bit 0 PE: Peripheral enable 0: Peripheral disable 1: Peripheral enable Note: If this bit is reset while a communication is on going, the peripheral is disabled at the end of the current communication, when back to IDLE state.
Page 621 RM0033 Inter-integrated circuit (I2C) interface Bit 9 ITEVTEN: Event interrupt enable 0: Event interrupt disabled 1: Event interrupt enabled This interrupt is generated when: – SB = 1 (Master) – ADDR = 1 (Master/Slave) – ADD10= 1 (Master) – STOPF = 1 (Slave) –...
Page 622: I 2 C Own Address Register 1 (I2C_Oar1)
Inter-integrated circuit (I2C) interface RM0033 23.6.3 C Own address register 1 (I2C_OAR1) Address offset: 0x08 Reset value: 0x0000 ADD[9:8] ADD[7:1] ADD0 MODE Reserved Bit 15 ADDMODE Addressing mode (slave mode) 0: 7-bit slave address (10-bit address not acknowledged) 1: 10-bit slave address (7-bit address not acknowledged) Bit 14 Should always be kept at 1 by software.
Page 623: C Data Register (I2C_Dr)
RM0033 Inter-integrated circuit (I2C) interface 23.6.5 C Data register (I2C_DR) Address offset: 0x10 Reset value: 0x0000 DR[7:0] Reserved Bits 15:8 Reserved, must be kept at reset value Bits 7:0 DR[7:0] 8-bit data register Byte received or to be transmitted to the bus. –...
Page 624 Inter-integrated circuit (I2C) interface RM0033 Bit 15 SMBALERT: SMBus alert In SMBus host mode: 0: no SMBALERT 1: SMBALERT event occurred on pin In SMBus slave mode: 0: no SMBALERT response address header 1: SMBALERT response address header to SMBALERT LOW received –...
Page 625 RM0033 Inter-integrated circuit (I2C) interface Bit 9 ARLO: Arbitration lost (master mode) 0: No Arbitration Lost detected 1: Arbitration Lost detected Set by hardware when the interface loses the arbitration of the bus to another master – Cleared by software writing 0, or by hardware when PE=0. After an ARLO event the interface switches back automatically to Slave mode (MSL=0).
Page 626 Inter-integrated circuit (I2C) interface RM0033 Bit 2 BTF: Byte transfer finished 0: Data byte transfer not done 1: Data byte transfer succeeded – Set by hardware when NOSTRETCH=0 and: – In reception when a new byte is received (including ACK pulse) and DR has not been read yet (RxNE=1).
Page 627: I 2 C Status Register 2 (I2C_Sr2)
RM0033 Inter-integrated circuit (I2C) interface 23.6.7 C Status register 2 (I2C_SR2) Address offset: 0x18 Reset value: 0x0000 Note: Reading I2C_SR2 after reading I2C_SR1 clears the ADDR flag, even if the ADDR flag was set after reading I2C_SR1. Consequently, I2C_SR2 must be read only when ADDR is found set in I2C_SR1 or when the STOPF bit is cleared.
Page 628: I 2 C Clock Control Register (I2C_Ccr)
Inter-integrated circuit (I2C) interface RM0033 Bit 2 TRA: Transmitter/receiver 0: Data bytes received 1: Data bytes transmitted This bit is set depending on the R/W bit of the address byte, at the end of total address phase. It is also cleared by hardware after detection of Stop condition (STOPF=1), repeated Start condition, loss of bus arbitration (ARLO=1), or when PE=0.
Page 629: C Trise Register (I2C_Trise)
RM0033 Inter-integrated circuit (I2C) interface Bit 14 DUTY: Fm mode duty cycle 0: Fm mode t high 1: Fm mode t = 16/9 (see CCR) high Bits 13:12 Reserved, must be kept at reset value Bits 11:0 CCR[11:0]: Clock control register in Fm/Sm mode (Master mode) Controls the SCL clock in master mode.
Page 630: I2C Register Map
Inter-integrated circuit (I2C) interface RM0033 23.6.10 C register map The table below provides the I C register map and reset values. Table 83. I C register map and reset values Offset Register I2C_CR1 0x00 Reserved Reset value I2C_CR2 FREQ[5:0] 0x04 Reserved Reset value I2C_OAR1...
Page 631: Universal Synchronous Asynchronous Receiver
RM0033 Universal synchronous asynchronous receiver transmitter (USART) Universal synchronous asynchronous receiver transmitter (USART) This section applies to the whole STM32F20x and STM32F21x family, unless otherwise specified. 24.1 USART introduction The universal synchronous asynchronous receiver transmitter (USART) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format.
Page 632: Usart Functional Description
Universal synchronous asynchronous receiver transmitter (USART) RM0033 • Separate enable bits for transmitter and receiver • Transfer detection flags: – Receive buffer full – Transmit buffer empty – End of transmission flags • Parity control: – Transmits parity bit – Checks parity of received data byte •...
Page 633 RM0033 Universal synchronous asynchronous receiver transmitter (USART) Through these pins, serial data is transmitted and received in normal USART mode as frames comprising: • An Idle Line prior to transmission or reception • A start bit • A data word (8 or 9 bits) least significant bit first •...
Page 634: Figure 223. Usart Block Diagram
Universal synchronous asynchronous receiver transmitter (USART) RM0033 Figure 223. USART block diagram PRDATA PWDATA Write Read (Data register) DR (CPU or DMA) (CPU or DMA) Receive data register (RDR) Transmit data register (TDR) IrDA SW_RX Receive Shift Register Transmit Shift Register ENDEC block IRDA_OUT...
Page 635: Usart Character Description
RM0033 Universal synchronous asynchronous receiver transmitter (USART) 24.3.1 USART character description Word length may be selected as being either 8 or 9 bits by programming the M bit in the USART_CR1 register (see Figure 224). The TX pin is in low state during the start bit. It is in high state during the stop bit. An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next frame which contains data (The number of “1”...
Page 636: Transmitter
Universal synchronous asynchronous receiver transmitter (USART) RM0033 24.3.2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the transmit enable bit (TE) is set, the data in the transmit shift register is output on the TX pin and the corresponding clock pulses are output on the CK pin.
Page 637: Figure 225. Configurable Stop Bits
RM0033 Universal synchronous asynchronous receiver transmitter (USART) Figure 225. Configurable stop bits 8-bit Word length (M bit is reset) Possible Next data frame parity Data frame Next Start start Stop Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 CLOCK **** ** LBCL bit controls last data clock pulse a) 1 Stop Bit Possible...
Page 638: Figure 226. Tc/Txe Behavior When Transmitting
Universal synchronous asynchronous receiver transmitter (USART) RM0033 When a transmission is taking place, a write instruction to the USART_DR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission.
Page 639: Receiver
RM0033 Universal synchronous asynchronous receiver transmitter (USART) Idle characters Setting the TE bit drives the USART to send an idle frame before the first data frame. 24.3.3 Receiver The USART can receive data words of either 8 or 9 bits depending on the M bit in the USART_CR1 register.
Page 640 Universal synchronous asynchronous receiver transmitter (USART) RM0033 3rd, 5th and 7th bits and sampling on the 8th, 9th and 10th bits). If this condition is not met, the start detection aborts and the receiver returns to the idle state (no flag is set). If, for one of the samplings (sampling on the 3rd, 5th and 7th bits or sampling on the 8th, 9th and 10th bits), 2 out of the 3 bits are found at 0, the start bit is validated but the NE noise flag bit is set.
Page 641 RM0033 Universal synchronous asynchronous receiver transmitter (USART) Overrun error An overrun error occurs when a character is received when RXNE has not been reset. Data can not be transferred from the shift register to the RDR register until the RXNE bit is cleared.
Page 642: Figure 228. Data Sampling When Oversampling By 16
Universal synchronous asynchronous receiver transmitter (USART) RM0033 Programming the ONEBIT bit in the USART_CR3 register selects the method used to evaluate the logic level. There are two options: • the majority vote of the three samples in the center of the received bit. In this case, when the 3 samples used for the majority vote are not equal, the NF bit is set •...
Page 643: Table 84. Noise Detection From Sampled Data
RM0033 Universal synchronous asynchronous receiver transmitter (USART) Figure 229. Data sampling when oversampling by 8 RX line sampled values Sample clock (x8) One bit time MSv31153V1 Table 84. Noise detection from sampled data Sampled value NE status Received bit value Framing error A framing error is detected when: The stop bit is not recognized on reception at the expected time, following either a de-...
Page 644: Fractional Baud Rate Generation
Universal synchronous asynchronous receiver transmitter (USART) RM0033 Configurable stop bits during reception The number of stop bits to be received can be configured through the control bits of Control Register 2 - it can be either 1 or 2 in normal mode and 0.5 or 1.5 in Smartcard mode. 0.5 stop bit (reception in Smartcard mode): No sampling is done for 0.5 stop bit.
Page 645 RM0033 Universal synchronous asynchronous receiver transmitter (USART) How to derive USARTDIV from USART_BRR register values when OVER8=0 Example 1: If DIV_Mantissa = 0d27 and DIV_Fraction = 0d12 (USART_BRR = 0x1BC), then Mantissa (USARTDIV) = 0d27 Fraction (USARTDIV) = 12/16 = 0d0.75 Therefore USARTDIV = 0d27.75 Example 2: To program USARTDIV = 0d25.62...
Page 646: Oversampling By 16
Universal synchronous asynchronous receiver transmitter (USART) RM0033 Then, USART_BRR = 0x195 => USARTDIV = 0d25.625 Example 3: To program USARTDIV = 0d50.99 This leads to: DIV_Fraction = 8*0d0.99 = 0d7.92 The nearest real number is 0d8 = 0x8 => overflow of the DIV_frac[2:0] => carry must be added up to the mantissa DIV_Mantissa = mantissa (0d50.990 + carry) = 0d51 = 0x33 Then, USART_BRR = 0x0330 =>...
Page 647: Oversampling By 8
RM0033 Universal synchronous asynchronous receiver transmitter (USART) Table 86. Error calculation for programmed baud rates at f = 8 MHz or f =12 MHz, PCLK PCLK oversampling by 8 Oversampling by 8 (OVER8 = 1) Baud rate = 8 MHz = 12 MHz PCLK PCLK...
Page 648: Oversampling By 8
Universal synchronous asynchronous receiver transmitter (USART) RM0033 Table 87. Error calculation for programmed baud rates at f = 16 MHz or f = 24 MHz, PCLK PCLK oversampling by 16 (continued) Oversampling by 16 (OVER8 = 0) Baud rate = 16 MHz = 24 MHz f PCLK f PCLK...
Page 649: Oversampling By 16
RM0033 Universal synchronous asynchronous receiver transmitter (USART) Table 89. Error calculation for programmed baud rates at f = 8 MHz or f = 16 MHz, PCLK PCLK oversampling by 16 Oversampling by 16 (OVER8=0) Baud rate = 8 MHz = 16 MHz PCLK PCLK Value...
Page 650: Oversampling By 16
Universal synchronous asynchronous receiver transmitter (USART) RM0033 Table 90. Error calculation for programmed baud rates at f = 8 MHz or f = 16 MHz, PCLK PCLK oversampling by 8 (continued) Oversampling by 8 (OVER8=1) Baud rate = 8 MHz = 16 MHz PCLK PCLK...
Page 651: Oversampling By 8
RM0033 Universal synchronous asynchronous receiver transmitter (USART) Table 91. Error calculation for programmed baud rates at f = 30 MHz or f = 60 MHz, PCLK PCLK (1)(2)(3) oversampling by 16 (continued) Oversampling by 16 (OVER8=0) Baud rate = 30 MHz = 60 MHz PCLK PCLK...
Page 652: Usart Receiver Tolerance To Clock Deviation
Universal synchronous asynchronous receiver transmitter (USART) RM0033 Table 92. Error calculation for programmed baud rates at f = 30 MHz or f = 60 MHz, PCLK PCLK (1) (2)(3) oversampling by 8 (continued) Oversampling by 8 (OVER8=1) Baud rate = 30 MHz =60 MHz PCLK PCLK...
Page 653: Multiprocessor Communication
RM0033 Universal synchronous asynchronous receiver transmitter (USART) Table 93. USART receiver’s tolerance when DIV fraction is 0 OVER8 bit = 0 OVER8 bit = 1 M bit ONEBIT=0 ONEBIT=1 ONEBIT=0 ONEBIT=1 3.75% 4.375% 2.50% 3.75% 3.41% 3.97% 2.27% 3.41% Table 94. USART receiver tolerance when DIV_Fraction is different from 0 OVER8 bit = 0 OVER8 bit = 1 M bit...
Page 654: Figure 230. Mute Mode Using Idle Line Detection
Universal synchronous asynchronous receiver transmitter (USART) RM0033 Figure 230. Mute mode using Idle line detection RXNE RXNE Data 1 Data 2 Data 3 Data 4 IDLE Data 5 Data 6 Mute mode Normal mode RWU written to 1 Idle frame detected MSv40881V1 Address mark detection (WAKE=1) In this mode, bytes are recognized as addresses if their MSB is a ‘1 else they are...
Page 655: Parity Control
RM0033 Universal synchronous asynchronous receiver transmitter (USART) 24.3.7 Parity control Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the USART_CR1 register. Depending on the frame length defined by the M bit, the possible USART frame formats are as listed in Table Table 95.
Page 656: Lin (Local Interconnection Network) Mode
Universal synchronous asynchronous receiver transmitter (USART) RM0033 24.3.8 LIN (local interconnection network) mode The LIN mode is selected by setting the LINEN bit in the USART_CR2 register. In LIN mode, the following bits must be kept cleared: • STOP[1:0] and CLKEN in the USART_CR2 register •...
Page 657: Figure 232. Break Detection In Lin Mode (11-Bit Break Length - Lbdl Bit Is Set)
RM0033 Universal synchronous asynchronous receiver transmitter (USART) Figure 232. Break detection in LIN mode (11-bit break length - LBDL bit is set) Case 1: break signal not long enough => break discarded, LBD is not set Break frame RX line Capture strobe Break state Idle...
Page 658: Usart Synchronous Mode
Universal synchronous asynchronous receiver transmitter (USART) RM0033 Figure 233. Break detection in LIN mode vs. Framing error detection Case 1: break occurring after an Idle RX line data 1 IDLE BREAK data 2 (0x55) data 3 (header) 1 data time 1 data time RXNE /FE LBDF...
Page 659: Figure 234. Usart Example Of Synchronous Transmission
RM0033 Universal synchronous asynchronous receiver transmitter (USART) has been written). This means that it is not possible to receive a synchronous data without transmitting data. The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly.
Page 660: Single-Wire Half-Duplex Communication
Universal synchronous asynchronous receiver transmitter (USART) RM0033 Figure 236. USART data clock timing diagram (M=1) Idle or Idle or next preceding Start M=1 (9 data bits) Stop transmission transmission Clock (CPOL=0, CPHA=0 Clock (CPOL=0, CPHA=1 Clock (CPOL=1, CPHA=0 Clock (CPOL=1, CPHA=1 Data on TX (from master)
Page 661: Smartcard
RM0033 Universal synchronous asynchronous receiver transmitter (USART) As soon as HDSEL is written to 1: • the TX and RX lines are internally connected • the RX pin is no longer used • the TX pin is always released when no data is transmitted. Thus, it acts as a standard I/O in idle or in reception.
Page 662: Figure 239. Parity Error Detection Using The 1.5 Stop Bits
Universal synchronous asynchronous receiver transmitter (USART) RM0033 shifting on the next baud clock edge. In Smartcard mode this transmission is further delayed by a guaranteed 1/2 baud clock. • If a parity error is detected during reception of a frame programmed with a 0.5 or 1.5 stop bit period, the transmit line is pulled low for a baud clock period after the completion of the receive frame.
Page 663: Irda Sir Endec Block
RM0033 Universal synchronous asynchronous receiver transmitter (USART) prescaler register USART_GTPR. CK frequency can be programmed from f /2 to f /62, where f is the peripheral input clock. 24.3.12 IrDA SIR ENDEC block The IrDA mode is selected by setting the IREN bit in the USART_CR3 register. In IrDA mode, the following bits must be kept cleared: •...
Page 664: Figure 240. Irda Sir Endec- Block Diagram
Universal synchronous asynchronous receiver transmitter (USART) RM0033 IrDA low-power mode Transmitter: In low-power mode the pulse width is not maintained at 3/16 of the bit period. Instead, the width of the pulse is 3 times the low-power baud rate which can be a minimum of 1.42 MHz. Generally this value is 1.8432 MHz (1.42 MHz <...
Page 665: Continuous Communication Using Dma
RM0033 Universal synchronous asynchronous receiver transmitter (USART) 24.3.13 Continuous communication using DMA The USART is capable of continuous communication using the DMA. The DMA requests for Rx buffer and Tx buffer are generated independently. Note: You should refer to product specs for availability of the DMA controller. If DMA is not available in the product, you should use the USART as explained in Section 24.3.2 24.3.3.
Page 666: Figure 242. Transmission Using Dma
Universal synchronous asynchronous receiver transmitter (USART) RM0033 Figure 242. Transmission using DMA Idle preamble Frame 1 Frame 2 Frame 3 TX line set by hardware set by hardware cleared by DMA read cleared by DMA read set by hardware TXE flag ignored by the DMA DMA request because DMA transfer is complete...
Page 667: Hardware Flow Control
RM0033 Universal synchronous asynchronous receiver transmitter (USART) Figure 243. Reception using DMA Frame 1 Frame 2 Frame 3 TX line set by hardware cleared by DMA read RXNE flag DMA request USART_DR DMA reads USART_DR cleared DMA TCIF flag set by hardware by software (Transfer complete) software configures the...
Page 668: Figure 245. Rts Flow Control
Universal synchronous asynchronous receiver transmitter (USART) RM0033 RTS flow control If the RTS flow control is enabled (RTSE=1), then RTS is asserted (tied low) as long as the USART receiver is ready to receive a new data. When the receive register is full, RTS is deasserted, indicating that the transmission is expected to stop at the end of the current frame.
Page 669: Figure 246. Cts Flow Control
RM0033 Universal synchronous asynchronous receiver transmitter (USART) Figure 246. CTS flow control Transmit data register Data 2 empty Data 3 empty Stop Start Stop Start Idle Data 1 Data 2 Data 3 Writing data 3 in TDR Transmission of Data 3 is delayed until CTS = 0 MSv31167V2 Note:...
Page 670: Usart Interrupts
Universal synchronous asynchronous receiver transmitter (USART) RM0033 24.4 USART interrupts Table 96. USART interrupt requests Enable control Interrupt event Event flag Transmit Data Register Empty TXEIE CTS flag CTSIE Transmission Complete TCIE Received Data Ready to be Read RXNE RXNEIE Overrun Error Detected Idle Line Detected IDLE...
Page 671: Usart Mode Configuration
RM0033 Universal synchronous asynchronous receiver transmitter (USART) 24.5 USART mode configuration Table 97. USART mode configuration USART USART USART USART USART modes UART4 UART5 Asynchronous mode Hardware flow control Multibuffer communication (DMA) Multiprocessor communication Synchronous Smartcard Half-duplex (single-wire mode) IrDA 1.
Page 672 Universal synchronous asynchronous receiver transmitter (USART) RM0033 Bits 31:10 Reserved, must be kept at reset value Bit 9 CTS: CTS flag This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software (by writing it to 0).
Page 673 RM0033 Universal synchronous asynchronous receiver transmitter (USART) Bit 3 ORE: Overrun error This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RXNE=1. An interrupt is generated if RXNEIE=1 in the USART_CR1 register.
Page 674: Data Register (Usart_Dr)
Universal synchronous asynchronous receiver transmitter (USART) RM0033 24.6.2 Data register (USART_DR) Address offset: 0x04 Reset value: 0xXXXX XXXX Bits 31:9 Reserved, must be kept at reset value Bits 8:0 DR[8:0]: Data value Contains the Received or Transmitted data character, depending on whether it is read from or written to.
Page 675 RM0033 Universal synchronous asynchronous receiver transmitter (USART) Bits 31:16 Reserved, must be kept at reset value Bit 15 OVER8: Oversampling mode 0: oversampling by 16 1: oversampling by 8 Note: Oversampling by 8 is not available in the Smartcard, IrDA and LIN modes: when SCEN=1,IREN=1 or LINEN=1 then OVER8 is forced to ‘0 by hardware.
Page 676 Universal synchronous asynchronous receiver transmitter (USART) RM0033 Bit 5 RXNEIE: RXNE interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An USART interrupt is generated whenever ORE=1 or RXNE=1 in the USART_SR register Bit 4 IDLEIE: IDLE interrupt enable This bit is set and cleared by software.
Page 677: Control Register 2 (Usart_Cr2)
RM0033 Universal synchronous asynchronous receiver transmitter (USART) 24.6.5 Control register 2 (USART_CR2) Address offset: 0x10 Reset value: 0x0000 0000 Reserved LINEN STOP[1:0] CLKEN CPOL CPHA LBCL Res. LBDIE LBDL Res. ADD[3:0] Res. Bits 31:15 Reserved, must be kept at reset value Bit 14 LINEN: LIN mode enable This bit is set and cleared by software.
Page 678: Control Register 3 (Usart_Cr3)
Universal synchronous asynchronous receiver transmitter (USART) RM0033 Bit 8 LBCL: Last bit clock pulse This bit allows the user to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in synchronous mode. 0: The clock pulse of the last data bit is not output to the CK pin 1: The clock pulse of the last data bit is output to the CK pin Note: 1: The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected...
Page 679 RM0033 Universal synchronous asynchronous receiver transmitter (USART) Bit 9 CTSE: CTS enable 0: CTS hardware flow control disabled 1: CTS mode enabled, data is only transmitted when the CTS input is asserted (tied to 0). If the CTS input is deasserted while a data is being transmitted, then the transmission is completed before stopping.
Page 680 Universal synchronous asynchronous receiver transmitter (USART) RM0033 Bit 2 IRLP: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes 0: Normal mode 1: Low-power mode Bit 1 IREN: IrDA mode enable This bit is set and cleared by software. 0: IrDA disabled 1: IrDA enabled Bit 0 EIE: Error interrupt enable...
Page 681: Guard Time And Prescaler Register (Usart_Gtpr)
RM0033 Universal synchronous asynchronous receiver transmitter (USART) 24.6.7 Guard time and prescaler register (USART_GTPR) Address offset: 0x18 Reset value: 0x0000 0000 Reserved GT[7:0] PSC[7:0] Bits 31:16 Reserved, must be kept at reset value Bits 15:8 GT[7:0]: Guard time value This bit-field gives the Guard time value in terms of number of baud clocks. This is used in Smartcard mode.
Page 682: Usart Register Map
Universal synchronous asynchronous receiver transmitter (USART) RM0033 24.6.8 USART register map The table below gives the USART register map and reset values. Table 98. USART register map and reset values Offset Register USART_SR 0x00 Reserved Reset value USART_DR DR[8:0] 0x04 Reserved Reset value DIV_Fraction...
Page 683: Serial Peripheral Interface (Spi)
RM0033 Serial peripheral interface (SPI) Serial peripheral interface (SPI) This section applies to the whole STM32F20x and STM32F21x family, unless otherwise specified. 25.1 SPI introduction The SPI interface provides two main functions, supporting either the SPI protocol or the I audio protocol.
Page 684: Spi And I
Serial peripheral interface (SPI) RM0033 25.2 SPI and I S main features 25.2.1 SPI features • Full-duplex synchronous transfers on three lines • Simplex synchronous transfers on two lines with or without a bidirectional data line • 8- or 16-bit transfer frame format selection •...
Page 685: I 2 S Features
RM0033 Serial peripheral interface (SPI) 25.2.2 S features • Half-duplex communication (only transmitter or receiver) • Master or slave operations • 8-bit programmable linear prescaler to reach accurate audio sample frequencies (from 8 kHz to 192 kHz) • Data format may be 16-bit, 24-bit or 32-bit •...
Page 686: Spi Functional Description
Serial peripheral interface (SPI) RM0033 25.3 SPI functional description 25.3.1 General description The block diagram of the SPI is shown in Figure 248. Figure 248. SPI block diagram Address and data bus Read Rx buffer SPI_CR2 MOSI RXNE TXDM RXDM SSOE Shift register MISO...
Page 687: Figure 249. Single Master/ Single Slave Application
RM0033 Serial peripheral interface (SPI) A basic example of interconnections between a single master and a single slave is illustrated in Figure 249. Figure 249. Single master/ single slave application Master Slave MSBit LSBit MSBit LSBit MISO MISO 8-bit shift register 8-bit shift register MOSI MOSI...
Page 688 Serial peripheral interface (SPI) RM0033 Clock phase and clock polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits in the SPI_CR1 register. The CPOL (clock polarity) bit controls the steady state value of the clock when no data is being transferred.
Page 689: Configuring The Spi In Slave Mode
RM0033 Serial peripheral interface (SPI) Figure 250. Data clock timing diagram CPHA =1 CPOL = 1 CPOL = 0 MOSI LSBit MSBit MISO LSBit MSBit (to slave) Capture strobe CPHA =0 CPOL = 1 CPOL = 0 MOSI LSBit MSBit MISO MSBit LSBit...
Page 690 Serial peripheral interface (SPI) RM0033 Note: It is recommended to enable the SPI slave before the master sends the clock. If not, undesired data transmission might occur. The data register of the slave needs to be ready before the first edge of the communication clock or before the end of the ongoing communication.
Page 691: Figure 251. Ti Mode - Slave Mode, Single Transfer
RM0033 Serial peripheral interface (SPI) SPI TI protocol in slave mode In slave mode, the SPI interface is compatible with the TI protocol. The FRF bit of the SPI_CR2 register can be used to configure the slave SPI serial communications to be compliant with this protocol.
Page 692: Configuring The Spi In Master Mode
Serial peripheral interface (SPI) RM0033 Figure 252. TI mode - Slave mode, continuous transfer input trigger sampling trigger sampling trigger sampling input DONTCARE MSBIN LSBIN MSBIN LSBIN DONTCARE MOSI input MISO LSBOUT MSBOUT LSBOUT 1 or 0 MSBOUT output FRAME 1 FRAME 2 ai18435 25.3.3...
Page 693: Figure 253. Ti Mode - Master Mode, Single Transfer
RM0033 Serial peripheral interface (SPI) Receive sequence For the receiver, when data transfer is complete: • The data in the shift register is transferred to the RX Buffer and the RXNE flag is set • An interrupt is generated if the RXNEIE bit is set in the SPI_CR2 register At the last sampling clock edge the RXNE bit is set, a copy of the data byte received in the shift register is moved to the Rx buffer.
Page 694: Configuring The Spi For Half-Duplex Communication
Serial peripheral interface (SPI) RM0033 Figure 254. TI mode - master mode, continuous transfer output trigger sampling trigger sampling trigger sampling output MOSI DONTCARE MSBOUT LSBOUT MSBOUT LSBOUT output MISO LSBIN MSBIN LSBIN DONTCARE 1 or 0 MSBIN intput FRAME 1 FRAME 2 ai18437 25.3.4...
Page 695: Data Transmission And Reception Procedures
RM0033 Serial peripheral interface (SPI) 25.3.5 Data transmission and reception procedures Rx and Tx buffers In reception, data are received and then stored into an internal Rx buffer while In transmission, data are first stored into an internal Tx buffer before being transmitted. A read access of the SPI_DR register returns the Rx buffered value whereas a write access to the SPI_DR stores the written data into the Tx buffer.
Page 696 Serial peripheral interface (SPI) RM0033 pin. The software must have written the data to be sent before the SPI master device initiates the transfer. • In unidirectional receive-only mode (BIDIMODE=0 and RXONLY=1) – The sequence begins when the slave device receives the clock signal and the first bit of the data on its MOSI pin.
Page 697: Figure 255. Txe/Rxne/Bsy Behavior In Master / Full-Duplex Mode
RM0033 Serial peripheral interface (SPI) Enable the SPI by setting the SPE bit to 1. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag). Wait until TXE=1 and write the second data item to be transmitted. Then wait until RXNE=1 and read the SPI_DR to get the first received data item (this clears the RXNE bit).
Page 698: Figure 256. Txe/Rxne/Bsy Behavior In Slave / Full-Duplex Mode
Serial peripheral interface (SPI) RM0033 Figure 256. TXE/RXNE/BSY behavior in Slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in case of continuous transfers Example in Slave mode with CPOL=1, CPHA=1 DATA 1 = 0xF1 DATA 2 = 0xF2 DATA 3 = 0xF3 MISO/MOSI (out) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 set by hardware...
Page 699: Figure 257. Txe/Bsy Behavior In Master Transmit-Only Mode (Bidimode=0 And Rxonly=0)
RM0033 Serial peripheral interface (SPI) Figure 257. TXE/BSY behavior in Master transmit-only mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers Example in Master mode with CPOL=1, CPHA=1 DATA 1 = 0xF1 DATA 2 = 0xF2 DATA 3 = 0xF3 MISO/MOSI (out) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 set by hardware...
Page 700: Figure 259. Rxne Behavior In Receive-Only Mode (Bidirmode=0 And Rxonly=1)
Serial peripheral interface (SPI) RM0033 Set the RXONLY bit in the SPI_CR1 register. Enable the SPI by setting the SPE bit to 1: In master mode, this immediately activates the generation of the SCK clock, and data are serially received until the SPI is disabled (SPE=0). In slave mode, data are received when the SPI master device drives NSS low and generates the SCK clock.
Page 701: Crc Calculation
RM0033 Serial peripheral interface (SPI) In slave mode, the continuity of the communication is decided by the SPI master device. In any case, even if the communication is continuous, the BSY flag goes low between each transfer for a minimum duration of one SPI clock cycle (see Figure 258).
Page 702 Serial peripheral interface (SPI) RM0033 Program the CPOL, CPHA, LSBFirst, BR, SSM, SSI and MSTR values. Program the polynomial in the SPI_CRCPR register. Enable the CRC calculation by setting the CRCEN bit in the SPI_CR1 register. This also clears the SPI_RXCRCR and SPI_TXCRCR registers. Enable the SPI by setting the SPE bit in the SPI_CR1 register.
Page 703: Status Flags
RM0033 Serial peripheral interface (SPI) 25.3.7 Status flags Four status flags are provided for the application to completely monitor the state of the SPI bus. Tx buffer empty flag (TXE) When it is set, this flag indicates that the Tx buffer is empty and the next data to be transmitted can be loaded into the buffer.
Page 704: Disabling The Spi
Serial peripheral interface (SPI) RM0033 25.3.8 Disabling the SPI When a transfer is terminated, the application can stop the communication by disabling the SPI peripheral. This is done by clearing the SPE bit. For some configurations, disabling the SPI and entering the Halt mode while a transfer is ongoing can cause the current transfer to be corrupted and/or the BSY flag might become unreliable.
Page 705: Spi Communication Using Dma (Direct Memory Addressing)
RM0033 Serial peripheral interface (SPI) In slave receive-only mode (MSTR=0, BIDIMODE=0, RXONLY=1) or bidirectional receive mode (MSTR=0, BIDIMODE=1, BIDOE=0) You can disable the SPI (write SPE=1) at any time: the current transfer will complete before the SPI is effectively disabled Then, if you want to enter the Halt mode, you must first wait until BSY = 0 before entering the Halt mode (or disabling the peripheral clock).
Page 706: Figure 261. Transmission Using Dma
Serial peripheral interface (SPI) RM0033 Figure 261. Transmission using DMA Example with CPOL=1, CPHA=1 DATA 1 = 0xF1 DATA 2 = 0xF2 DATA 3 = 0xF3 MISO/MOSI (out) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 set by hardware set by hardware cleared by DMA write...
Page 707: Error Flags
RM0033 Serial peripheral interface (SPI) DMA capability with CRC When SPI communication is enabled with CRC communication and DMA mode, the transmission and reception of the CRC at the end of communication are automatic that is without using the bit CRCNEXT. After the CRC reception, the CRC must be read in the SPI_DR register to clear the RXNE flag.
Page 708: Spi Interrupts
Serial peripheral interface (SPI) RM0033 CRC error This flag is used to verify the validity of the value received when the CRCEN bit in the SPI_CR1 register is set. The CRCERR flag in the SPI_SR register is set if the value received in the shift register does not match the receiver SPI_RXCRCR value.
Page 709: S Functional Description
RM0033 Serial peripheral interface (SPI) 25.4 S functional description 25.4.1 S general description The block diagram of the I S is shown in Figure 264. Figure 264. I S block diagram Address and data bus Tx buffer BSY OVR MODF CRC TxE RxNE SIDE 16-bit...
Page 710: Supported Audio Protocols
Serial peripheral interface (SPI) RM0033 The I S shares three common pins with the SPI: • SD: Serial Data (mapped on the MOSI pin) to transmit or receive the two time- multiplexed data channels (in half-duplex mode only). • WS: Word Select (mapped on the NSS pin) is the data control signal output in master mode and input in slave mode.
Page 711: Figure 265. I S Philips Protocol Waveforms (16/32-Bit Full Accuracy, Cpol = 0)
RM0033 Serial peripheral interface (SPI) The I S interface supports four audio standards, configurable using the I2SSTD[1:0] and PCMSYNC bits in the SPI_I2SCFGR register. S Philips standard For this standard, the WS signal is used to indicate which channel is being transmitted. It is activated one CK clock cycle before the first bit (MSB) is available.
Page 712: Figure 267. Transmitting 0X8Eaa33
Serial peripheral interface (SPI) RM0033 Figure 267. Transmitting 0x8EAA33 First write to Data register Second write to Data register 0x8EAA 0x33XX Only the 8 MSB are sent to compare the 24 bits 8 LSBs have no meaning and can be anything MS19593V1 •...
Page 713: Figure 271. Msb Justified 16-Bit Or 32-Bit Full-Accuracy Length With Cpol = 0
RM0033 Serial peripheral interface (SPI) For transmission, each time an MSB is written to SPI_DR, the TXE flag is set and its interrupt, if allowed, is generated to load SPI_DR with the new value to send. This takes place even if 0x0000 have not yet been sent because it is done by hardware. For reception, the RXNE flag is set and its interrupt, if allowed, is generated when the first 16 MSB half-word is received.
Page 714: Figure 273. Msb Justified 16-Bit Extended To 32-Bit Packet Frame With Cpol = 0
Serial peripheral interface (SPI) RM0033 Figure 273. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 Transmission Reception 16-bit data 16-bit remaining 0 forced Channel left 32-bit Channel right MS30102V1 LSB justified standard This standard is similar to the MSB justified standard (no difference for the 16-bit and 32-bit full-accuracy frame formats).
Page 715: Figure 276. Operations Required To Transmit 0X3478Ae
RM0033 Serial peripheral interface (SPI) Figure 276. Operations required to transmit 0x3478AE First write to Data register Second write to Data register conditioned by TXE=1 conditioned by TXE=1 0xXX34 0x78AE Only the 8 LSB of the half-word are significant. A field of 0x00 is forced instead of the 8 MSBs.
Page 716: Figure 279. Example Of Lsb Justified 16-Bit Extended To 32-Bit Packet Frame
Serial peripheral interface (SPI) RM0033 Figure 279. Example of LSB justified 16-bit extended to 32-bit packet frame Only one access to the SPIx-DR register 0x76A3 MS19598V1 In transmission mode, when TXE is asserted, the application has to write the data to be transmitted (in this case 0x76A3).
Page 717: Clock Generator
RM0033 Serial peripheral interface (SPI) Figure 281. PCM standard waveforms (16-bit extended to 32-bit packet frame) short frame Up to 13-bits long frame 16 bits MS30107V1 Note: For both modes (master and slave) and for both synchronizations (short and long), the number of bits between two consecutive pieces of data (and so two synchronization signals) needs to be specified (DATLEN and CHLEN bits in the SPI_I2SCFGR register) even in slave mode.
Page 718: Table 100. Audio Frequency Precision (For Pllm Vco = 1 Mhz Or 2 Mhz)
Serial peripheral interface (SPI) RM0033 Figure 283. I S clock generator architecture I²SxCLK 8-bit linear divider + reshaping stage Div2 Divider by 4 MCKOE I²SDIV[7:0] MCKOE ODD MS30109V1 1. Where x could be 2 or 3. Figure 282 presents the communication clock architecture. To achieve high-quality audio performance, the I2SxCLK clock source can be either the PLLI2S output (through R division factor) or an external clock (mapped to I2S_CKIN pin).
Page 719: I 2 S Master Mode
RM0033 Serial peripheral interface (SPI) Table 100. Audio frequency precision (for PLLM VCO = 1 MHz or 2 MHz) 16-bit 8000 0.0000% 8000 32-bit 8000 0.0000% 16-bit 16000 0.0000% 16000 32-bit 16000 0.0000% 16-bit 32000 0.0000% 32000 32-bit 32000 0.0000% 16-bit 48000 0.0000%...
Page 720 Serial peripheral interface (SPI) RM0033 computed depending on the state of the MCK output, for more details refer to Section 25.4.3: Clock generator). Set the I2SMOD bit in SPI_I2SCFGR to activate the I S functionalities and choose the S standard through the I2SSTD[1:0] and PCMSYNC bits, the data length through the DATLEN[1:0] bits and the number of bits per channel by configuring the CHLEN bit.
Page 721: I 2 S Slave Mode
RM0033 Serial peripheral interface (SPI) For more details about the read operations depending on the I S standard mode selected, refer to Section 25.4.2: Supported audio protocols. If data are received while the previously received data have not been read yet, an overrun is generated and the OVR flag is set.
Page 722 Serial peripheral interface (SPI) RM0033 Transmission sequence The transmission sequence begins when the external master device sends the clock and when the NSS_WS signal requests the transfer of data. The slave has to be enabled before the external master starts the communication. The I S data register has to be loaded before the master initiates the communication.
Page 723: Status Flags
RM0033 Serial peripheral interface (SPI) For more details about the read operations depending the I S standard mode selected, refer Section 25.4.2: Supported audio protocols. If data are received while the precedent received data have not yet been read, an overrun is generated and the OVR flag is set.
Page 724: Error Flags
Serial peripheral interface (SPI) RM0033 slave transmission mode, this flag is not reliable and I S needs to be switched off and switched on before resuming the communication. In reception mode, this flag is refreshed when data are received into SPI_DR. It indicates from which channel side data have been received.
Page 725: Dma Features
RM0033 Serial peripheral interface (SPI) 25.4.9 DMA features DMA is working in exactly the same way as for the SPI mode. There is no difference on the S. Only the CRC feature is not available in I S mode since there is no data transfer protection system.
Page 726: Spi And I S Registers
Serial peripheral interface (SPI) RM0033 25.5 SPI and I S registers The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). 25.5.1 SPI control register 1 (SPI_CR1) (not used in I S mode) Address offset: 0x00 Reset value: 0x0000 BIDI BIDI...
Page 727 RM0033 Serial peripheral interface (SPI) Bit 10 RXONLY: Receive only This bit combined with the BIDImode bit selects the direction of transfer in 2-line unidirectional mode. This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. 0: Full duplex (Transmit and receive) 1: Output disabled (Receive-only mode) Note: This bit is not used in I...
Page 728: Spi Control Register 2 (Spi_Cr2)
Serial peripheral interface (SPI) RM0033 Bit 2 MSTR: Master selection 0: Slave configuration 1: Master configuration Note: This bit should not be changed when communication is ongoing. It is not used in I S mode. Bit1 CPOL: Clock polarity 0: CK to 0 when idle 1: CK to 1 when idle Note: This bit should not be changed when communication is ongoing.
Page 729: Spi Status Register (Spi_Sr)
RM0033 Serial peripheral interface (SPI) Bit 2 SSOE: SS output enable 0: SS output is disabled in master mode and the cell can work in multimaster configuration 1: SS output is enabled in master mode and when the cell is enabled. The cell cannot work in a multimaster environment.
Page 730: Spi Data Register (Spi_Dr)
Serial peripheral interface (SPI) RM0033 Bit 4 CRCERR: CRC error flag 0: CRC value received matches the SPI_RXCRCR value 1: CRC value received does not match the SPI_RXCRCR value This flag is set by hardware and cleared by software writing 0. Note: This bit is not used in I S mode.
Page 731: Spi Crc Polynomial Register (Spi_Crcpr) (Not Used In I
RM0033 Serial peripheral interface (SPI) 25.5.5 SPI CRC polynomial register (SPI_CRCPR) (not used in I mode) Address offset: 0x10 Reset value: 0x0007 CRCPOLY[15:0] Bits 15:0 CRCPOLY[15:0]: CRC polynomial register This register contains the polynomial for the CRC calculation. The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be configured as required.
Page 732: Spi_I S Configuration Register (Spi_I2Scfgr)
Serial peripheral interface (SPI) RM0033 Bits 15:0 TXCRC[15:0]: Tx CRC register When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register.
Page 733: Spi_I 2 S Prescaler Register (Spi_I2Spr)
RM0033 Serial peripheral interface (SPI) Bits 5:4 I2SSTD: I2S standard selection 00: I S Philips standard. 01: MSB justified standard (left justified) 10: LSB justified standard (right justified) 11: PCM standard For more details on I S standards, refer to Section 25.4.2: Supported audio protocols.
Page 734 Serial peripheral interface (SPI) RM0033 Bits 15:10 Reserved, must be kept at reset value. Bit 9 MCKOE: Master clock output enable 0: Master clock output is disabled 1: Master clock output is enabled Note: This bit should be configured when the I S is disabled.
Page 735: Spi Register Map
RM0033 Serial peripheral interface (SPI) 25.5.10 SPI register map The table provides shows the SPI register map and reset values. Table 102. SPI register map and reset values Offset Register SPI_CR1 BR [2:0] 0x00 Reserved Reset value SPI_CR2 0x04 Reserved Reset value SPI_SR 0x08...
Page 736: Secure Digital Input/Output Interface (Sdio)
Secure digital input/output interface (SDIO) RM0033 Secure digital input/output interface (SDIO) This section applies to the whole STM32F20x and STM32F21x family, unless otherwise specified. 26.1 SDIO main features The SD/SDIO MMC card host interface (SDIO) provides an interface between the APB2 peripheral bus and MultiMediaCards (MMCs), SD memory cards, SDIO cards and CE-ATA devices.
Page 737: Sdio Bus Topology
RM0033 Secure digital input/output interface (SDIO) 26.2 SDIO bus topology Communication over the bus is based on command and data transfers. The basic transaction on the MultiMediaCard/SD/SD I/O bus is the command/response transaction. These types of bus transaction transfer their information directly within the command or response structure.
Page 738: Figure 286. Sdio (Multiple) Block Write Operation
Secure digital input/output interface (SDIO) RM0033 Figure 286. SDIO (multiple) block write operation From host to card From card to host data from host to card Stop command stops data transfer SDMMC_CMD Command Response Command Response SDMMC_D Busy Busy Data block crc Data block crc Data stop operation Block write operation...
Page 739: Sdio Functional Description
RM0033 Secure digital input/output interface (SDIO) 26.3 SDIO functional description The SDIO consists of two parts: • The SDIO adapter block provides all functions specific to the MMC/SD/SD I/O card such as the clock generation unit, command and data transfer. •...
Page 740: Sdio Adapter
Secure digital input/output interface (SDIO) RM0033 Table 103. SDIO I/O definitions Direction Description MultiMediaCard/SD/SDIO card clock. This pin is the clock from SDIO_CK Output host to card. MultiMediaCard/SD/SDIO card command. This pin is the SDIO_CMD Bidirectional bidirectional command/response signal. MultiMediaCard/SD/SDIO card data. These pins are the SDIO_D[7:0] Bidirectional bidirectional databus.
Page 741: Figure 291. Control Unit
RM0033 Secure digital input/output interface (SDIO) Control unit The control unit contains the power management functions and the clock divider for the memory card clock. There are three power phases: • power-off • power-up • power-on Figure 291. Control unit Control unit Power management Adapter...
Page 742: Figure 292. Sdio Adapter Command Path
Secure digital input/output interface (SDIO) RM0033 Command path The command path unit sends commands to and receives responses from the cards. Figure 292. SDIO adapter command path Status Control Command To control unit flag logic timer Adapter registers SDMMC_CMDin Argument SDMMC_CMDout Shift register...
Page 743: Figure 293. Command Path State Machine (Cpsm)
RM0033 Secure digital input/output interface (SDIO) Figure 293. Command path state machine (CPSM) CE-ATA Command On reset Completion signal Wait_CPL received or CPSM disabled or Command CRC failed CPSM Enabled and Idle Response received or Response Received in CE-ATA pending command disabled or command mode and no interrupt and CRC failed...
Page 744: Table 104. Command Format
Secure digital input/output interface (SDIO) RM0033 Figure 294. SDIO command transfer at least 8 SDMMC_CK cycles SDMMC_CK Command Response Command State Idle Send Wait Receive Idle Send SDMMC_CMD Hi-Z Controller drives Hi-Z Card drives Hi-Z Controller drives ai14807b • Command format –...
Page 745: Table 105. Short Response Format
RM0033 Secure digital input/output interface (SDIO) Table 105. Short response format Bit position Width Value Description Start bit Transmission bit [45:40] Command index [39:8] Argument [7:1] CRC7(or 1111111) End bit Table 106. Long response format Bit position Width Value Description Start bit Transmission bit [133:128]...
Page 746: Figure 295. Data Path
Secure digital input/output interface (SDIO) RM0033 Data path The data path subunit transfers data to and from cards. Figure 295 shows a block diagram of the data path. Figure 295. Data path Data path Status Control Data To control unit flag logic timer...
Page 747: Figure 296. Data Path State Machine (Dpsm)
RM0033 Secure digital input/output interface (SDIO) Figure 296. Data path state machine (DPSM) On reset DPSM disabled DPSM enabled and Read Wait Read Wait Started and SD I/O mode enabled Disabled or FIFO underrun or Idle end of data or CRC fail Disabled or CRC fail or timeout Enable and not send...
Page 748: Table 108. Data Token Format
Secure digital input/output interface (SDIO) RM0033 CRC code, the DPSM moves to the Wait_R state. If not, the CRC fail status flag is set and the DPSM moves to the Idle state. – In stream mode, the DPSM receives data while the data counter is not zero. When the counter is zero, the remaining data in the shift register is written to the data FIFO, and the DPSM moves to the Wait_R state.
Page 749: Table 109. Transmit Fifo Status Flags
RM0033 Secure digital input/output interface (SDIO) Data FIFO The data FIFO (first-in-first-out) subunit is a data buffer with a transmit and receive unit. The FIFO contains a 32-bit wide, 32-word deep data buffer, and transmit and receive logic. Because the data FIFO operates in the APB2 clock domain (PCLK2), all signals from the subunits in the SDIO clock domain (SDIOCLK) are resynchronized.
Page 750: Sdio Apb2 Interface
Secure digital input/output interface (SDIO) RM0033 Table 110. Receive FIFO status flags Flag Description RXFIFOF Set to high when all 32 receive FIFO words contain valid data RXFIFOE Set to high when the receive FIFO does not contain valid data. Set to high when 8 or more receive FIFO words contain valid data.
Page 751: Card Functional Description
RM0033 Secure digital input/output interface (SDIO) DMA2_Stream6 Channel4 destination address register with the SDIO_FIFO register address. Program DMA2_Stream3 or DMA2_Stream6 Channel4 control register (memory increment, not peripheral increment, peripheral and source width is word size). Program DMA2_Stream3 or DMA2_Stream6 Channel4 to select the peripheral as flow controller (set PFCTRL bit in DMA_S3CR or DMA_S6CR configuration register).
Page 752: Card Identification Process
Secure digital input/output interface (SDIO) RM0033 Cards that store the card identification number (CID) and card specific data (CSD) in the payload memory are able to communicate this information only under data-transfer V conditions. When the SDIO card host module and the card have incompatible V ranges, the card is not able to complete the identification cycle and cannot send CSD data.
Page 753: Block Write
RM0033 Secure digital input/output interface (SDIO) The bus is activated. The SDIO card host broadcasts SD_APP_OP_COND (ACMD41). The cards respond with the contents of their operation condition registers. The incompatible cards are placed in the inactive state. The SDIO card host broadcasts ALL_SEND_CID (CMD2) to all active cards. The cards send back their unique card identification numbers (CIDs) and enter the Identification state.
Page 754: Block Read
Secure digital input/output interface (SDIO) RM0033 select a different card), which will place the card in the Disconnect state and release the SDIO_D line(s) without interrupting the write operation. When selecting the card again, it will reactivate busy indication by pulling SDIO_D to low if programming is still in progress and the write buffer is unavailable.
Page 755 RM0033 Secure digital input/output interface (SDIO) The maximum clock frequency for a stream write operation is given by the following equation fields of the card-specific data register: 2 writebllen × ) NSAC – ( Maximumspeed MIN TRANSPEED ------------------------------------------------------------------------- TAAC × R2WFACTOR •...
Page 756: Erase: Group Erase And Sector Erase
Secure digital input/output interface (SDIO) RM0033 26.4.8 Erase: group erase and sector erase The erasable unit of the MultiMediaCard is the erase group. The erase group is measured in write blocks, which are the basic writable units of the card. The size of the erase group is a card-specific parameter and defined in the CSD.
Page 757 RM0033 Secure digital input/output interface (SDIO) at the specified address) followed by 16 CRC bits. The address field in the write protect commands is a group address in byte units. The card ignores all LSBs below the group size. Mechanical write protect switch A mechanical sliding tab on the side of the card allows the user to set or clear the write protection on a card.
Page 758 Secure digital input/output interface (SDIO) RM0033 When a password replacement is done, the block size must take into account that both the old and the new passwords are sent with the command. Send LOCK/UNLOCK (CMD42) with the appropriate data block size on the data line including the 16-bit CRC.
Page 759: Card Status Register
RM0033 Secure digital input/output interface (SDIO) When the password is previously set (PWD_LEN is not 0), the card is locked automatically after power-on reset. An attempt to lock a locked card or to lock a card that does not have a password fails and the LOCK_UNLOCK_FAILED error bit is set in the card status register.
Page 760: Table 111. Card Status
Secure digital input/output interface (SDIO) RM0033 Type: • E: error bit • S: status bit • R: detected and set for the actual command response • X: detected and set during command execution. The SDIO card host must poll the card by issuing the status command to read these bits.
Page 761 RM0033 Secure digital input/output interface (SDIO) Table 111. Card status (continued) Clear Bits Identifier Type Value Description condition ‘0’ = card When set, signals that the card is locked CARD_IS_LOCKED unlocked by the host ‘1’ = card locked Set when a sequence or password error LOCK_UNLOCK_ ’0’= no error has been detected in lock/unlock card...
Page 762: Sd Status Register
Secure digital input/output interface (SDIO) RM0033 Table 111. Card status (continued) Clear Bits Identifier Type Value Description condition 0 = Idle 1 = Ready 2 = Ident The state of the card when receiving the 3 = Stby command. If the command execution 4 = Tran causes a state change, it will be visible to 12:9...
Page 763: Table 112. Sd Status
RM0033 Secure digital input/output interface (SDIO) Clear condition: • A: according to the card current state • B: always related to the previous command. Reception of a valid command clears it (with a delay of one command) • C: clear by read Table 112.
Page 764: Table 113. Speed Class Code Field
Secure digital input/output interface (SDIO) RM0033 SIZE_OF_PROTECTED_AREA Setting this field differs between standard- and high-capacity cards. In the case of a standard-capacity card, the capacity of protected area is calculated as follows: Protected area = SIZE_OF_PROTECTED_AREA_* MULT * BLOCK_LEN. SIZE_OF_PROTECTED_AREA is specified by the unit in MULT*BLOCK_LEN. In the case of a high-capacity card, the capacity of protected area is specified in this field: Protected area = SIZE_OF_PROTECTED_AREA SIZE_OF_PROTECTED_AREA is specified by the unit in bytes.
Page 765: Table 115. Au_Size Field
RM0033 Secure digital input/output interface (SDIO) AU_SIZE This 4-bit field indicates the AU size and the value can be selected in the power of 2 base from 16 KB. Table 115. AU_SIZE field AU_SIZE Value definition Not defined 16 KB 32 KB 64 KB 128 KB...
Page 766: Sd I/O Mode
Secure digital input/output interface (SDIO) RM0033 ERASE_TIMEOUT This 6-bit field indicates TERASE and the value indicates the erase timeout from offset when multiple AUs are being erased as specified by ERASE_SIZE. The range of ERASE_TIMEOUT can be defined as up to 63 seconds and the card manufacturer can choose any combination of ERASE_SIZE and ERASE_TIMEOUT depending on the implementation.
Page 767: Commands And Responses
RM0033 Secure digital input/output interface (SDIO) The interrupt period is applicable for both memory and I/O operations. The definition of the interrupt period for operations with single blocks is different from the definition for multiple- block data transfers. SD I/O suspend and resume Within a multifunction SD I/O or a card with both I/O and memory functions, there are multiple devices (I/O and memory) that share access to the MMC/SD bus.
Page 768: Table 120. Block-Oriented Write Commands
Secure digital input/output interface (SDIO) RM0033 To use one of the manufacturer-specific ACMDs the SD card Host must perform the following steps: Send APP_CMD (CMD55) The card responds to the MultiMediaCard/SD module, indicating that the APP_CMD bit is set and an ACMD is now expected. Send the required ACMD The card responds to the MultiMediaCard/SD module, indicating that the APP_CMD bit is set and that the accepted command is interpreted as an ACMD.
Page 769: Table 121. Block-Oriented Write Protection Commands
RM0033 Secure digital input/output interface (SDIO) Table 120. Block-oriented write commands (continued) Response Type Argument Abbreviation Description index format Continuously writes blocks of data [31:0] data until a STOP_TRANSMISSION CMD25 adtc WRITE_MULTIPLE_BLOCK address follows or the requested number of blocks has been received. Programming of the card identification register.
Page 770: Table 123. I/O Mode Commands
Secure digital input/output interface (SDIO) RM0033 Table 122. Erase commands (continued) Response Type Argument Abbreviation Description index format Reserved. This command index cannot be used in order to maintain backward compatibility with older CMD37 versions of the MultiMediaCards Erases all previously selected write CMD38 ac [31:0] stuff bits ERASE...
Page 771: Response Formats
RM0033 Secure digital input/output interface (SDIO) Table 125. Application-specific commands (continued) Response Type Argument Abbreviation Description index format CMD57 Reserved. CMD59 CMD60 Reserved for manufacturer. CMD63 26.5 Response formats All responses are sent via the MCCMD command line SDIO_CMD. The response transmission always starts with the left bit of the bit string corresponding to the response code word.
Page 772: R3 (Ocr Register)
Secure digital input/output interface (SDIO) RM0033 CMD9. Only the bits [127...1] of the CID and CSD are transferred, the reserved bit [0] of these registers is replaced by the end bit of the response. The card indicates that an erase is in progress by holding MCDAT low.
Page 773: R4B
RM0033 Secure digital input/output interface (SDIO) Table 129. R4 response (continued) Bit position Width (bits Value Description [7:1] CRC7 End bit 26.5.6 For SD I/O only: an SDIO card receiving the CMD5 will respond with a unique SDIO response R4. The format is: Table 130.
Page 774: Sdio I/O Card-Specific Operations
Secure digital input/output interface (SDIO) RM0033 Table 131. R5 response (continued) Bit position Width (bits Value Description RCA [31:16] of winning [31:16] card or of the host [39:8] Argument field Not defined. May be used [15:0] for IRQ data [7:1] CRC7 End bit 26.5.8...
Page 775: Sdio I/O Read Wait Operation By Sdio_D2 Signaling
RM0033 Secure digital input/output interface (SDIO) 26.6.1 SDIO I/O read wait operation by SDIO_D2 signaling It is possible to start the readwait interval before the first block is received: when the data path is enabled (SDIO_DCTRL[0] bit set), the SDIO-specific operation is enabled (SDIO_DCTRL[11] bit set), read wait starts (SDI0_DCTRL[10] =0 and SDI_DCTRL[8] =1) and data direction is from card to SDIO (SDIO_DCTRL[1] = 1), the DPSM directly moves from Idle to Readwait.
Page 776: Ce-Ata Specific Operations
Secure digital input/output interface (SDIO) RM0033 26.7 CE-ATA specific operations The following features are CE-ATA specific operations: • sending the command completion signal disable to the CE-ATA device • receiving the command completion signal from the CE-ATA device • signaling the completion of the CE-ATA command to the CPU, using the status bit and/or interrupt.
Page 777: Hw Flow Control
RM0033 Secure digital input/output interface (SDIO) 26.8 HW flow control The HW flow control functionality is used to avoid FIFO underrun (TX mode) and overrun (RX mode) errors. The behavior is to stop SDIO_CK and freeze SDIO state machines. The data transfer is stalled while the FIFO is unable to transmit or receive data.
Page 778: Sdi Clock Control Register (Sdio_Clkcr)
Secure digital input/output interface (SDIO) RM0033 26.9.2 SDI clock control register (SDIO_CLKCR) Address offset: 0x04 Reset value: 0x0000 0000 The SDIO_CLKCR register controls the SDIO_CK output clock. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CLKDIV Reserved rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw...
Page 779: Sdio Argument Register (Sdio_Arg)
RM0033 Secure digital input/output interface (SDIO) Note: While the SD/SDIO card or MultiMediaCard is in identification mode, the SDIO_CK frequency must be less than 400 kHz. The clock frequency can be changed to the maximum card bus frequency when relative card addresses are assigned to all cards.
Page 780: Sdio Command Response Register (Sdio_Respcmd)
Secure digital input/output interface (SDIO) RM0033 Bit 11 SDIOSuspend: SD I/O suspend command If this bit is set, the command to be sent is a suspend command (to be used only with SDIO card). Bit 10 CPSMEN: Command path state machine (CPSM) Enable bit If this bit is set, the CPSM is enabled.
Page 781: Sdio Response 1
RM0033 Secure digital input/output interface (SDIO) 26.9.6 SDIO response 1..4 register (SDIO_RESPx) Address offset: (0x10 + (4 × x)); x = 1..4 Reset value: 0x0000 0000 The SDIO_RESP1/2/3/4 registers contain the status of a card, which is part of the received response.
Page 782: Sdio Data Length Register (Sdio_Dlen)
Secure digital input/output interface (SDIO) RM0033 26.9.8 SDIO data length register (SDIO_DLEN) Address offset: 0x28 Reset value: 0x0000 0000 The SDIO_DLEN register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATALENGTH Reserved...
Page 783: Sdio Data Control Register (Sdio_Dctrl)
RM0033 Secure digital input/output interface (SDIO) 26.9.9 SDIO data control register (SDIO_DCTRL) Address offset: 0x2C Reset value: 0x0000 0000 The SDIO_DCTRL register control the data path state machine (DPSM). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DBLOCKSIZE Reserved rw rw rw rw rw rw rw rw rw rw rw rw...
Page 784: Sdio Data Counter Register (Sdio_Dcount)
Secure digital input/output interface (SDIO) RM0033 Bit 2 DTMODE: Data transfer mode selection 1: Stream or SDIO multibyte data transfer. 0: Block data transfer 1: Stream or SDIO multibyte data transfer Bit 1 DTDIR: Data transfer direction selection 0: From controller to card. 1: From card to controller.
Page 785: Sdio Status Register (Sdio_Sta)
RM0033 Secure digital input/output interface (SDIO) 26.9.11 SDIO status register (SDIO_STA) Address offset: 0x34 Reset value: 0x0000 0000 The SDIO_STA register is a read-only register. It contains two types of flag: • Static flags (bits [23:22,10:0]): these bits remain asserted until they are cleared by writing to the SDIO Interrupt Clear register (see SDIO_ICR) •...
Page 786: Sdio Interrupt Clear Register (Sdio_Icr)
Secure digital input/output interface (SDIO) RM0033 Bit 4 TXUNDERR: Transmit FIFO underrun error Bit 3 DTIMEOUT: Data timeout Bit 2 CTIMEOUT: Command response timeout The Command TimeOut period has a fixed value of 64 SDIO_CK clock periods. Bit 1 DCRCFAIL: Data block sent/received (CRC check failed) Bit 0 CCRCFAIL: Command response received (CRC check failed) 26.9.12 SDIO interrupt clear register (SDIO_ICR)
Page 787 RM0033 Secure digital input/output interface (SDIO) Bit 7 CMDSENTC: CMDSENT flag clear bit Set by software to clear the CMDSENT flag. 0: CMDSENT not cleared 1: CMDSENT cleared Bit 6 CMDRENDC: CMDREND flag clear bit Set by software to clear the CMDREND flag. 0: CMDREND not cleared 1: CMDREND cleared Bit 5 RXOVERRC: RXOVERR flag clear bit...
Page 788: Sdio Mask Register (Sdio_Mask)
Secure digital input/output interface (SDIO) RM0033 26.9.13 SDIO mask register (SDIO_MASK) Address offset: 0x3C Reset value: 0x0000 0000 The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1b. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:24 Reserved, must be kept at reset value...
Page 789 RM0033 Secure digital input/output interface (SDIO) Bit 16 TXFIFOFIE: Tx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO full. 0: Tx FIFO full interrupt disabled 1: Tx FIFO full interrupt enabled Bit 15 RXFIFOHFIE: Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full.
Page 790: Sdio Fifo Counter Register (Sdio_Fifocnt)
Secure digital input/output interface (SDIO) RM0033 Bit 6 CMDRENDIE: Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response. 0: Command response received interrupt disabled 1: command Response Received interrupt enabled Bit 5 RXOVERRIE: Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error.
Page 791: Sdio Data Fifo Register (Sdio_Fifo)
RM0033 Secure digital input/output interface (SDIO) 26.9.15 SDIO data FIFO register (SDIO_FIFO) Address offset: 0x80 Reset value: 0x0000 0000 The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.
Page 792 Secure digital input/output interface (SDIO) RM0033 Table 134. SDIO register map (continued) Offset Register 0x34 SDIO_STA 0x38 SDIO_ICR 0x3C SDIO_MASK 0x48 SDIO_FIFOCNT Reserved FIFOCOUNT 0x80 SDIO_FIFO FIF0Data 792/1378 RM0033 Rev 8...
Page 793: Controller Area Network (Bxcan)
RM0033 Controller area network (bxCAN) Controller area network (bxCAN) This section applies to the whole STM32F20x and STM32F21x family, unless otherwise specified. 27.1 bxCAN introduction The Basic Extended CAN peripheral, named bxCAN, interfaces the CAN network. It supports the CAN protocols version 2.0A and B. It has been designed to manage a high number of incoming messages efficiently with a minimum CPU load.
Page 794: Bxcan General Description
Controller area network (bxCAN) RM0033 Dual CAN • CAN1: Master bxCAN for managing the communication between a Slave bxCAN and the 512-byte SRAM memory • CAN2: Slave bxCAN, with no direct access to the SRAM memory. • The two bxCAN cells share the 512-byte SRAM memory (see Figure 298: Dual CAN block diagram)
Page 795: Control, Status And Configuration Registers
RM0033 Controller area network (bxCAN) 27.3.2 Control, status and configuration registers The application uses these registers to: • Configure CAN parameters, e.g. baud rate • Request transmissions • Handle receptions • Manage interrupts • Get diagnostic information 27.3.3 Tx mailboxes Three transmit mailboxes are provided to the software for setting up messages.
Page 796: Bxcan Operating Modes
Controller area network (bxCAN) RM0033 Figure 298. Dual CAN block diagram CAN 1 (Master) with 512 bytes SRAM Master Tx Mailboxes Re ceive FIFO 0 R eceive FIFO 1 Mailbox 0 Mailbox 0 Mailbox 0 Master Control Master Status Tx Status Rx FIFO 0 Status Transmission Scheduler...
Page 797: Initialization Mode
RM0033 Controller area network (bxCAN) mode. Before entering normal mode bxCAN always has to synchronize on the CAN bus. To synchronize, bxCAN waits until the CAN bus is idle, this means 11 consecutive recessive bits have been monitored on CANRX. 27.4.1 Initialization mode The software initialization can be done while the hardware is in Initialization mode.
Page 798: Test Mode
Controller area network (bxCAN) RM0033 bxCAN can be woken up (exit Sleep mode) either by software clearing the SLEEP bit or on detection of CAN bus activity. On CAN bus activity detection, hardware automatically performs the wakeup sequence by clearing the SLEEP bit if the AWUM bit in the CAN_MCR register is set. If the AWUM bit is cleared, software has to clear the SLEEP bit when a wakeup interrupt occurs, in order to exit from Sleep mode.
Page 799: Loop Back Mode
RM0033 Controller area network (bxCAN) remain in recessive state. Silent mode can be used to analyze the traffic on a CAN bus without affecting it by the transmission of dominant bits (Acknowledge Bits, Error Frames). Figure 300. bxCAN in silent mode bxCAN CANTX CANRX 27.5.2...
Page 800: Debug Mode
Controller area network (bxCAN) RM0033 Figure 302. bxCAN in combined mode bxCAN CANTX CANRX 27.6 Debug mode ® When the microcontroller enters the debug mode (Cortex -M3 core halted), the bxCAN continues to work normally or stops, depending on: • the DBG_CAN1_STOP bit for CAN1 or the DBG_CAN2_STOP bit for CAN2 in the DBG module.
Page 801: Figure 303. Transmit Mailbox States
RM0033 Controller area network (bxCAN) The transmit mailboxes can be configured as a transmit FIFO by setting the TXFP bit in the CAN_MCR register. In this mode the priority order is given by the transmit request order. This mode is very useful for segmented transmission. Abort A transmission request can be aborted by the user setting the ABRQ bit in the CAN_TSR register.
Page 802: Time Triggered Communication Mode
Controller area network (bxCAN) RM0033 27.7.2 Time triggered communication mode In this mode, the internal counter of the CAN hardware is activated and used to generate the Time Stamp value stored in the CAN_RDTxR/CAN_TDTxR registers, respectively (for Rx and Tx mailboxes). The internal counter is incremented each CAN bit time (refer to Section 27.7.7: Bit timing).
Page 803: Identifier Filtering
RM0033 Controller area network (bxCAN) FIFO management Starting from the empty state, the first valid message received is stored in the FIFO which becomes pending_1. The hardware signals the event setting the FMP[1:0] bits in the CAN_RFR register to the value 01b. The message is available in the FIFO output mailbox. The software reads out the mailbox content and releases it by setting the RFOM bit in the CAN_RFR register.
Page 804 Controller area network (bxCAN) RM0033 otherwise needed to perform filtering by software. Each filter bank x consists of two 32-bit registers, CAN_FxR0 and CAN_FxR1. Scalable width To optimize and adapt the filters to the application needs, each filter bank can be scaled independently.
Page 805: Figure 305. Filter Bank Scale Configuration - Register Organization
RM0033 Controller area network (bxCAN) Figure 305. Filter bank scale configuration - register organization Filter Num. One 32-Bit Filter - Identifier Mask CAN_FxR1[31:24] CAN_FxR1[23:16] CAN_FxR1[15:8] CAN_FxR1[7:0] Mask CAN_FxR2[31:24] CAN_FxR2[23:16] CAN_FxR2[15:8] CAN_FxR2[7:0] Mapping STID[10:3] STID[2:0] EXID[17:13] EXID[12:5] EXID[4:0] Two 32-Bit Filters - Identifier List CAN_FxR1[31:24] CAN_FxR1[23:16] CAN_FxR1[15:8]...
Page 806: Figure 306. Example Of Filter Numbering
Controller area network (bxCAN) RM0033 Figure 306. Example of filter numbering Filter Filter Filter Filter FIFO0 FIFO1 Bank Num. Bank Num. ID List (32-bit) ID Mask (16-bit) ID Mask (32-bit) ID List (32-bit) Deactivated ID List (16-bit) ID Mask (16-bit) Deactivated ID Mask (16-bit) ID List (32-bit)
Page 807: Message Storage
RM0033 Controller area network (bxCAN) Figure 307. Filtering mechanism - example Example of 3 filter banks in 32-bit Unidentified List mode and the remaining in 32-bit Identifier Mask mode Message Received Identifier Data Ctrl Filter bank Receive FIFO Identifier Identifier Message Stored Identifier...
Page 808: Table 135. Transmit Mailbox Mapping
Controller area network (bxCAN) RM0033 Table 135. Transmit mailbox mapping Offset to transmit mailbox base address Register name CAN_TIxR CAN_TDTxR CAN_TDLxR CAN_TDHxR Receive mailbox When a message has been received, it is available to the software in the FIFO output mailbox.
Page 809: Error Management
RM0033 Controller area network (bxCAN) 27.7.6 Error management The error management as described in the CAN protocol is handled entirely by hardware using a Transmit Error Counter (TEC value, in CAN_ESR register) and a Receive Error Counter (REC value, in the CAN_ESR register), which get incremented or decremented according to the error condition.
Page 810: Figure 309. Bit Timing
Controller area network (bxCAN) RM0033 A valid edge is defined as the first transition in a bit time from dominant to recessive bus level provided the controller itself does not send a recessive bit. If a valid edge is detected in BS1 instead of SYNC_SEG, BS1 is extended by up to SJW so that the sample point is delayed.
Page 811: Bxcan Interrupts
RM0033 Controller area network (bxCAN) Figure 310. CAN frames Inter-Frame Space Inter-Frame Space Data Frame (Standard identifier) or Overload Frame 44 + 8 * N Arbitration Field Ctrl Field Data Field CRC Field Ack Field 8 * N Inter-Frame Space Inter-Frame Space Data Frame (Extended Identifier) or Overload Frame...
Page 812: Figure 311. Event Flags And Interrupt Generation
Controller area network (bxCAN) RM0033 Figure 311. Event flags and interrupt generation CAN_IER TRANSMIT INTERRUPT TMEIE & RQCP0 CAN_TSR RQCP1 RQCP2 FMPIE0 & FIFO 0 FMP0 INTERRUPT FFIE0 & CAN_RF0R FULL0 FOVIE0 & FOVR0 & FMPIE1 FIFO 1 FMP1 INTERRUPT &...
Page 813: Can Registers
RM0033 Controller area network (bxCAN) – Wakeup condition, SOF monitored on the CAN Rx signal. – Entry into Sleep mode. 27.9 CAN registers The peripheral registers have to be accessed by words (32 bits). 27.9.1 Register access protection Erroneous access to certain configuration registers can cause the hardware to temporarily disturb the whole CAN network.
Page 814 Controller area network (bxCAN) RM0033 Bit 7 TTCM: Time triggered communication mode 0: Time Triggered Communication mode disabled. 1: Time Triggered Communication mode enabled Note: For more information on Time Triggered Communication mode refer to Section 27.7.2: Time triggered communication mode.
Page 815 RM0033 Controller area network (bxCAN) Bit 0 INRQ Initialization request The software clears this bit to switch the hardware into normal mode. Once 11 consecutive recessive bits have been monitored on the Rx signal the CAN hardware is synchronized and ready for transmission and reception.
Page 816 Controller area network (bxCAN) RM0033 Bit 2 ERRI Error interrupt This bit is set by hardware when a bit of the CAN_ESR has been set on error detection and the corresponding interrupt in the CAN_IER is enabled. Setting this bit generates a status change interrupt if the ERRIE bit in the CAN_IER register is set.
Page 817 RM0033 Controller area network (bxCAN) Bit 26 TME0 Transmit mailbox 0 empty This bit is set by hardware when no transmit request is pending for mailbox 0. Bits 25:24 CODE[1:0] Mailbox code In case at least one transmit mailbox is free, the code value is equal to the number of the next transmit mailbox free.
Page 818 Controller area network (bxCAN) RM0033 Bit 7 ABRQ0 Abort request for mailbox0 Set by software to abort the transmission request for the corresponding mailbox. Cleared by hardware when the mailbox becomes empty. Setting this bit has no effect when the mailbox is not pending for transmission. Bits 6:4 Reserved, must be kept at reset value.
Page 819 RM0033 Controller area network (bxCAN) Bits 1:0 FMP0[1:0] FIFO 0 message pending These bits indicate how many messages are pending in the receive FIFO. FMP is increased each time the hardware stores a new message in to the FIFO. FMP is decreased each time the software releases the output mailbox by setting the RFOM0 bit.
Page 820 Controller area network (bxCAN) RM0033 Bits 31:18 Reserved, must be kept at reset value. Bit 17 SLKIE Sleep interrupt enable 0: No interrupt when SLAKI bit is set. 1: Interrupt generated when SLAKI bit is set. Bit 16 WKUIE Wakeup interrupt enable 0: No interrupt when WKUI is set.
Page 821 RM0033 Controller area network (bxCAN) Bit 2 FFIE0 FIFO full interrupt enable 0: No interrupt when FULL bit is set. 1: Interrupt generated when FULL bit is set. Bit 1 FMPIE0 FIFO message pending interrupt enable 0: No interrupt generated when state of FMP[1:0] bits are not 00b. 1: Interrupt generated when state of FMP[1:0] bits are not 00b.
Page 822 Controller area network (bxCAN) RM0033 Bit 2 BOFF Bus-off flag This bit is set by hardware when it enters the bus-off state. The bus-off state is entered on TEC overflow, greater than 255, refer to Section 27.7.6: Error management. Bit 1 EPVF: Error passive flag This bit is set by hardware when the Error Passive limit has been reached (Receive Error Counter or Transmit Error Counter>127).
Page 823: Can Mailbox Registers
RM0033 Controller area network (bxCAN) Bits 19:16 TS1[3:0] Time segment 1 These bits define the number of time quanta in Time Segment 1 x (TS1[3:0] + 1) For more information on bit timing refer to Section 27.7.7: Bit timing. Bits 15:10 Reserved, must be kept at reset value. Bits 9:0 BRP[9:0] Baud rate prescaler These bits define the length of a time quanta.
Page 824 Controller area network (bxCAN) RM0033 CAN TX mailbox identifier register (CAN_TIxR) (x=0..2) Address offsets: 0x180, 0x190, 0x1A0 Reset value: 0xXXXX XXXX (except bit 0, TXRQ = 0) All TX registers are write protected when the mailbox is pending transmission (TMEx reset). This register also implements the TX request control (bit 0) - reset value 0.
Page 825 RM0033 Controller area network (bxCAN) CAN mailbox data length control and time stamp register (CAN_TDTxR) (x=0..2) All bits of this register are write protected when the mailbox is not in empty state. Address offsets: 0x184, 0x194, 0x1A4 Reset value: 0xXXXX XXXX TIME[15:0] DLC[3:0] Reserved...
Page 826 Controller area network (bxCAN) RM0033 CAN mailbox data low register (CAN_TDLxR) (x=0..2) All bits of this register are write protected when the mailbox is not in empty state. Address offsets: 0x188, 0x198, 0x1A8 Reset value: 0xXXXX XXXX DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0] Bits 31:24 DATA3[7:0] Data byte 3...
Page 827 RM0033 Controller area network (bxCAN) CAN receive FIFO mailbox identifier register (CAN_RIxR) (x=0..1) Address offsets: 0x1B0, 0x1C0 Reset value: 0xXXXX XXXX All RX registers are write protected. STID[10:0]/EXID[28:18] EXID[17:13] EXID[12:0] Res. Bits 31:21 STID[10:0]/EXID[28:18] Standard identifier or extended identifier The standard identifier or the MSBs of the extended identifier (depending on the IDE bit value).
Page 828 Controller area network (bxCAN) RM0033 CAN receive FIFO mailbox data length control and time stamp register (CAN_RDTxR) (x=0..1) Address offsets: 0x1B4, 0x1C4 Reset value: 0xXXXX XXXX All RX registers are write protected. TIME[15:0] FMI[7:0] DLC[3:0] Reserved Bits 31:16 TIME[15:0] Message time stamp This field contains the 16-bit timer value captured at the SOF detection.
Page 829 RM0033 Controller area network (bxCAN) CAN receive FIFO mailbox data low register (CAN_RDLxR) (x=0..1) All bits of this register are write protected when the mailbox is not in empty state. Address offsets: 0x1B8, 0x1C8 Reset value: 0xXXXX XXXX All RX registers are write protected. DATA3[7:0] DATA2[7:0] DATA1[7:0]...
Page 830: Can Filter Registers
Controller area network (bxCAN) RM0033 27.9.4 CAN filter registers CAN filter master register (CAN_FMR) Address offset: 0x200 Reset value: 0x2A1C 0E01 All bits of this register are set and cleared by software. Reserved CAN2SB[5:0] FINIT Reserved Reserved Bits 31:14 Reserved, must be kept at reset value. Bits 13:8 CAN2SB[5:0] CAN2 start bank These bits are set and cleared by software.
Page 831 RM0033 Controller area network (bxCAN) CAN filter mode register (CAN_FM1R) Address offset: 0x204 Reset value: 0x0000 0000 This register can be written only when the filter initialization mode is set (FINIT=1) in the CAN_FMR register. FBM27 FBM26 FBM25 FBM24 FBM23 FBM22 FBM21 FBM20 FBM19 FBM18 FBM17 FBM16 Reserved FBM15 FBM14 FBM13 FBM12 FBM11 FBM10 FBM9...
Page 832 Controller area network (bxCAN) RM0033 CAN filter FIFO assignment register (CAN_FFA1R) Address offset: 0x214 Reset value: 0x0000 0000 This register can be written only when the filter initialization mode is set (FINIT=1) in the CAN_FMR register. FFA27 FFA26 FFA25 FFA24 FFA23 FFA22 FFA21...
Page 833 RM0033 Controller area network (bxCAN) Filter bank i register x (CAN_FiRx) (i=0..27, x=1, 2) Address offsets: 0x240..0x31C Reset value: 0xXXXX XXXX There are 28 filter banks, i=0 .. 27. Each filter bank i is composed of two 32-bit registers, CAN_FiR[2:1]. This register can only be modified when the FACTx bit of the CAN_FAxR register is cleared or when the FINIT bit of the CAN_FMR register is set.
Page 834: Bxcan Register Map
Controller area network (bxCAN) RM0033 27.9.5 bxCAN register map Refer to Section 2.3: Memory map for the register boundary addresses. The registers from offset 0x200 to 31C are present only in CAN1. Table 137. bxCAN register map and reset values Offset Register CAN_MCR...
Page 835 RM0033 Controller area network (bxCAN) Table 137. bxCAN register map and reset values (continued) Offset Register CAN_TDH0R DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0] 0x18C Reset value CAN_TI1R STID[10:0]/EXID[28:18] EXID[17:0] 0x190 Reset value CAN_TDT1R TIME[15:0] DLC[3:0] 0x194 Reserved Reserved Reset value CAN_TDL1R DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0]...
Page 836 Controller area network (bxCAN) RM0033 Table 137. bxCAN register map and reset values (continued) Offset Register CAN_RDT1R TIME[15:0] FMI[7:0] DLC[3:0] 0x1C4 Reserved Reset value CAN_RDL1R DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0] 0x1C8 Reset value CAN_RDH1R DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0] 0x1CC Reset value 0x1D0- Reserved 0x1FF...
Page 837 RM0033 Controller area network (bxCAN) Table 137. bxCAN register map and reset values (continued) Offset Register CAN_F1R2 FB[31:0] 0x24C Reset value CAN_F27R1 FB[31:0] 0x318 Reset value CAN_F27R2 FB[31:0] 0x31C Reset value RM0033 Rev 8 837/1378...
Page 838: Ethernet (Eth): Media Access Control (Mac) With
Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Ethernet (ETH): media access control (MAC) with DMA controller This section applies to the whole STM32F20x and STM32F21x family, unless otherwise specified. 28.1 Ethernet introduction Portions Copyright (c) 2004, 2005 Synopsys, Inc. All rights reserved. Used with permission. The Ethernet peripheral enables the STM32F20x and STM32F21x to transmit and receive data over Ethernet in compliance with the IEEE 802.3-2002 standard.
Page 839: Mac Core Features
RM0033 Ethernet (ETH): media access control (MAC) with DMA controller 28.2.1 MAC core features • Supports 10/100 Mbit/s data transfer rates with external PHY interfaces • IEEE 802.3-compliant MII interface to communicate with an external Fast Ethernet • Supports both full-duplex and half-duplex operations –...
Page 840: Dma Features
Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Store-and-Forward mode • Option to forward under-sized good frames • Supports statistics by generating pulses for frames dropped or corrupted (due to overflow) in the Receive FIFO • Supports Store and Forward mechanism for transmission to the MAC core •...
Page 841: Ethernet Pins
RM0033 Ethernet (ETH): media access control (MAC) with DMA controller 28.3 Ethernet pins Table 138 shows the MAC signals and the corresponding MII/RMII signal mapping. All MAC signals are mapped onto AF11, some signals are mapped onto different I/O pins, and should be configured in Alternate function mode (for more details, refer to Section 6.3.2: I/O pin multiplexer and...
Page 842: Ethernet Functional Description: Smi, Mii And Rmii
Ethernet (ETH): media access control (MAC) with DMA controller RM0033 28.4 Ethernet functional description: SMI, MII and RMII The Ethernet peripheral consists of a MAC 802.3 (media access control) with a dedicated DMA controller. It supports both default media-independent interface (MII) and reduced media-independent interface (RMII) through one selection bit (refer to SYSCFG_PMC register).
Page 843: Table 139. Management Frame Format
RM0033 Ethernet (ETH): media access control (MAC) with DMA controller 160 ns each, and the minimum period for MDC must be 400 ns. In idle state the SMI management interface drives the MDC clock signal low. • MDIO: data input/output bitstream to transfer status information to/from the PHY device synchronously with the MDC clock signal Figure 314.
Page 844: Figure 315. Mdio Timing And Frame Structure - Write Cycle
Ethernet (ETH): media access control (MAC) with DMA controller RM0033 For a write transaction, the MAC controller drives a <10> pattern during the TA field. The PHY device must drive a high-impedance state for the 2 bits of TA. • Data: the data field is 16-bit.
Page 845: Media-Independent Interface: Mii
RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Figure 316. MDIO timing and frame structure - Read cycle 32 1's 0 1 1 MDIO A4 A3 A2 A1 A0 R4 R3 R2 R1 R0 D15 D14 D1 D0 Start Register address Turn Preamble...
Page 846: Figure 317. Media Independent Interface Signals
Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Figure 317. Media independent interface signals TX _CLK TXD[3:0] TX_EN RX_CLK RXD[3:0] STM32 MCU External RX_ER RX_DV MDIO ai15622c • MII_TX_CLK: continuous clock that provides the timing reference for the TX data transfer.
Page 847: Table 141. Tx Interface Signal Encoding
RM0033 Ethernet (ETH): media access control (MAC) with DMA controller that follows the final nibble. In order to receive the frame correctly, the MII_RX_DV signal must encompass the frame, starting no later than the SFD field. • MII_RX_ER: receive error must be asserted for one or more clock periods (MII_RX_CLK) to indicate to the MAC sublayer that an error was detected somewhere in the frame.
Page 848: Reduced Media-Independent Interface: Rmii
Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Figure 318. MII clock sources STM32 External TX _CLK 25 MHz RX _CLK For 10/100 Mbit/s 25 MHz ai15623b 28.4.3 Reduced media-independent interface: RMII The reduced media-independent interface (RMII) specification reduces the pin count between the microcontroller Ethernet peripheral and the external Ethernet in 10/100 Mbit/s.
Page 849: Mii/Rmii Selection
RM0033 Ethernet (ETH): media access control (MAC) with DMA controller RMII clock sources As described in the RMII clock sources section, the STM32F20x and STM32F21xSTM32F107xx could provide this 50 MHz clock signal on its MCO output pin and you then have to configure this output value through PLL configuration. Figure 320.
Page 850: Ethernet Functional Description: Mac 802.3
Ethernet (ETH): media access control (MAC) with DMA controller RM0033 To save a pin, the two input clock signals, RMII_REF_CK and MII_RX_CLK, are multiplexed on the same GPIO pin. 28.5 Ethernet functional description: MAC 802.3 The IEEE 802.3 International Standard for local area networks (LANs) employs the CSMA/CD (carrier sense multiple access with collision detection) as the access method.
Page 851: Figure 322. Address Field Format
RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Figure 323 Figure 324 describe the frame structure (untagged and tagged) that includes the following fields: • Preamble: 7-byte field used for synchronization purposes (PLS circuitry) Hexadecimal value: 55-55-55-55-55-55-55 Bit pattern: 01010101 01010101 01010101 01010101 01010101 01010101 01010101 (right-to-left bit transmission) •...
Page 852 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 hexadecimal). This constant field is used to distinguish tagged and untagged MAC frames. – 2-byte field containing the Tag control information field subdivided as follows: a 3- bit user priority, a canonical format indicator (CFI) bit and a 12-bit VLAN Identifier. The length of the tagged MAC frame is extended by 4 bytes by the QTag Prefix.
Page 853: Figure 323. Mac Frame Format
RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Figure 323. MAC frame format 7 bytes Preamble 1 byte 6 bytes Destination address Bytes within frame transmitted 6 bytes Source address top to bottom 2 bytes MAC client length/type MAC client data 46-1500 bytes 4 bytes...
Page 854: Mac Frame Transmission
Ethernet (ETH): media access control (MAC) with DMA controller RM0033 28.5.2 MAC frame transmission The DMA controls all transactions for the transmit path. Ethernet frames read from the system memory are pushed into the FIFO by the DMA. The frames are then popped out and transferred to the MAC core.
Page 855 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller The CRC generator calculates the 32-bit CRC for the FCS field of the Ethernet frame. The encoding is defined by the following polynomial. G x ( ) Transmit protocol The MAC controls the operation of Ethernet frame transmission. It performs the following functions to meet the IEEE 802.3/802.3z specifications.
Page 856 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 configured for 96 bit times, the MAC follows the rule of deference specified in Section 4.2.3.2.1 of the IEEE 802.3 specification. The MAC resets its IFG counter if a carrier is detected during the first two-thirds (64-bit times for all IFG values) of the IFG interval.
Page 857 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller frame is being transmitted. As soon as the first frame has been transferred and the status is received from the MAC, it is pushed to the DMA. If the DMA has already completed sending the second packet to the FIFO, the second transmission must wait for the status of the first packet before proceeding to the next frame.
Page 858 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 is set in the ETH_ETH_DMAOMR register). If the core is configured for Threshold (cut- through) mode, the Transmit checksum offload is bypassed. You must make sure the Transmit FIFO is deep enough to store a complete frame before that frame is transferred to the MAC Core transmitter.
Page 859 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller error, it inserts an IPv4 header checksum if the Ethernet Type field indicates an IPv4 payload. • TCP/UDP/ICMP checksum The TCP/UDP/ICMP checksum processes the IPv4 or IPv6 header (including extension headers) and determines whether the encapsulated payload is TCP, UDP or ICMP.
Page 860: Figure 325. Transmission Bit Order
Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Figure 325. Transmission bit order Bibit stream MII_TXD[3:0] Nibble stream ai15632 MII/RMII transmit timing diagrams Figure 326. Transmission with no collision MII_TX_CLK MII_TX_EN MII_TXD[3:0] MII_CS MII_COL ai15631 860/1378 RM0033 Rev 8...
Page 861: Mac Frame Reception
RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Figure 327. Transmission with collision MII_TX_CLK MII_TX_EN MII_TXD[3:0] MII_CS MII_COL ai15651 Figure 328 shows a frame transmission in MII and RMII. Figure 328. Frame transmission in MMI and RMII modes MII_RX_CLK MII_TX_EN MII_TXD[3:0]...
Page 862 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 packet has been transferred. Upon completion of the EOF frame transfer, the status word is popped out and sent to the DMA controller. In Rx FIFO Store-and-forward mode (configured by the RSF bit in the ETH_DMAOMR register), a frame is read only after being written completely into the Receive FIFO.
Page 863: Table 143. Frame Statuses
RM0033 Ethernet (ETH): media access control (MAC) with DMA controller type (Ethernet Type field) and the IP header version, or when the received frame does not have enough bytes, as indicated by the IPv4 header’s Length field (or when fewer than 20 bytes are available in an IPv4 or IPv6 header).
Page 864 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 the frame is dropped and the Rx Status Word is immediately updated (with zero frame length, CRC error and Runt Error bits set), indicating the filter fail. In Ethernet power down mode, all received frames are dropped, and are not forwarded to the application.
Page 865: Figure 329. Receive Bit Order
RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Receive status word At the end of the Ethernet frame reception, the MAC outputs the receive status to the application (DMA). The detailed description of the receive status is the same as for bits[31:0] in RDES0, given in RDES0: Receive descriptor Word0 on page 897.
Page 866: Mac Interrupts
Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Figure 330. Reception with no error MII_RX_CLK MII_RX_DV MII_RXD[3:0] PREAMBLE MII_RX_ERR ai15634 Figure 331. Reception with errors MII_RX_CLK MII_RX_DV MII_RXD[3:0] PREAMBLE MII_RX_ERR ai15635 Figure 332. Reception with false carrier indication MII_RX_CLK MII_RX_DV MII_RXD[3:0]...
Page 867: Mac Filtering
RM0033 Ethernet (ETH): media access control (MAC) with DMA controller The interrupt register bits only indicate the block from which the event is reported. You have to read the corresponding status registers and other registers to clear the interrupt. For example, bit 3 of the Interrupt register, set high, indicates that the Magic packet or Wake-on- LAN frame is received in Power-down mode.
Page 868 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Multicast destination address filter The MAC can be programmed to pass all multicast frames by setting the PAM bit in the Frame filter register. If the PAM bit is reset, the MAC performs the filtering for multicast addresses based on the HM bit in the Frame filter register.
Page 869: Table 144. Destination Address Filtering
RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Table 145 summarize destination and source address filtering based on the type of frame received. Table 144. Destination address filtering Frame DAIF PAM DB DA filter operation type Pass Broadcast Pass Fail Pass all frames...
Page 870: Mac Loopback Mode
Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Table 145. Source address filtering Frame type SAIF SA filter operation Pass all frames Pass status on perfect/Group filter match but do not drop frames that fail Unicast Fail status on perfect/group filter match but do not drop frame Pass on perfect/group filter match and drop frames that fail Fail on perfect/group filter match and drop frames that fail 28.5.6...
Page 871: Power Management: Pmt
RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Received frames are considered “good” if none of the following errors exists: + CRC error + Runt Frame (shorter than 64 bytes) + Alignment error (in 10/ 100 Mbit/s only) + Length error (non-Type frames only) + Out of Range (non-Type frames only, longer than maximum size) + MII_RXER Input error...
Page 872: Figure 334. Wakeup Frame Filter Register
Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Figure 334. Wakeup frame filter register Filter 0 Byte Mask Wakeup frame filter reg0 Filter 1 Byte Mask Wakeup frame filter reg1 Filter 2 Byte Mask Wakeup frame filter reg2 Filter 3 Byte Mask Wakeup frame filter reg3 Filter 3...
Page 873 SRAM. To disable the Ethernet DMA, clear the ST bit and the SR bit (for the transmit DMA and the receive DMA, respectively) in the ETH_DMAOMR register.
Page 874: Precision Time Protocol (Ieee1588 Ptp)
Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Disable the transmit DMA and wait for any previous frame transmissions to complete. These transmissions can be detected when the transmit interrupt ETH_DMASR register[0] is received. Disable the MAC transmitter and MAC receiver by clearing the RE and TE bits in the ETH_MACCR configuration register.
Page 875: Figure 335. Networked Time Synchronization
RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Figure 335. Networked time synchronization Master clock time Slave clock time Sync message Data at slave clock Follow_up message containing value of t1 Delay_Req message Delay_Resp message containing value of t4 time ai15669 The master broadcasts PTP Sync messages to all its nodes.
Page 876 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 be greater than or equal to the resolution of time stamp counter. The synchronization accuracy target between the master node and the slaves is around 100 ns. The generation, update and modification of the System Time are described in System Time correction methods.
Page 877: Figure 336. System Time Update Using The Fine Correction Method
RM0033 Ethernet (ETH): media access control (MAC) with DMA controller The accumulator and the addend are 32-bit registers. Here, the accumulator acts as a high- precision frequency multiplier or divider. Figure 336 shows this algorithm. Figure 336. System time update using the Fine correction method Addend register Addend update Accumulator register...
Page 878 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 The algorithm is as follows: • At time MasterSyncTime (n) the master sends the slave clock a Sync message. The slave receives this message when its local clock is SlaveClockTime (n) and computes MasterClockTime (n) as: MasterClockTime (n) = MasterSyncTime (n) + MasterToSlaveDelay (n) •...
Page 879: Figure 337. Ptp Trigger Output To Tim2 Itr1 Connection
RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Programming steps for system time update in the Coarse correction method To synchronize or update the system time in one process (coarse correction method), perform the following steps: Write the offset (positive or negative) in the Time stamp update high and low registers. Set bit 3 (TSSTU) in the Time stamp control register.
Page 880: Ethernet Functional Description: Dma Controller Operation
Ethernet (ETH): media access control (MAC) with DMA controller RM0033 PTP pulse-per-second output signal This PTP pulse output is used to check the synchronization between all nodes in the network. To be able to test the difference between the local slave clock and the master reference clock, both clocks were given a pulse-per-second (PPS) output signal that may be connected to an oscilloscope if necessary.
Page 881: Initialization Of A Transfer Using Dma
RM0033 Ethernet (ETH): media access control (MAC) with DMA controller enables the use of two physically addressed buffers, instead of two contiguous buffers in memory. A data buffer resides in the Host’s physical memory space, and consists of an entire frame or part of a frame, but cannot exceed a single frame. Buffers contain only data. The buffer status is maintained in the descriptor.
Page 882: Host Data Buffer Alignment
Ethernet (ETH): media access control (MAC) with DMA controller RM0033 always accessed in the maximum possible burst size (limited by PBL) for the 16 bytes to be read. The Transmit DMA initiates a data transfer only when there is sufficient space in the Transmit FIFO to accommodate the configured burst or the number of bytes until the end of frame (when it is less than the configured burst length).
Page 883: Dma Arbiter
(TDES0[31]) after setting up the corresponding data buffer(s) with Ethernet frame data. Once the ST bit (ETH_DMAOMR register[13]) is set, the DMA enters the Run state. While in the Run state, the DMA polls the transmit descriptor list for frames requiring transmission.
Page 884 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Unavailable (ETH_DMASR register[2]) and Normal Interrupt Summary (ETH_DMASR register[16]) bits are set. The transmit engine proceeds to Step 9. If the acquired descriptor is flagged as owned by DMA (TDES0[31] is set), the DMA decodes the transmit data buffer address from the acquired descriptor.
Page 885: Figure 340. Txdma Operation In Default Mode
RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Figure 340. TxDMA operation in Default mode Start TxDMA Stop TxDMA Start (Re-)fetch next descriptor (AHB) Poll demand error? TxDMA suspended bit set? Transfer data from buffer(s) (AHB) error? Frame xfer complete? Close intermediate Wait for Tx status...
Page 886 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 The DMA operates as described in steps 1–6 of the TxDMA (default mode). Without closing the previous frame’s last descriptor, the DMA fetches the next descriptor. If the DMA owns the acquired descriptor, the DMA decodes the transmit buffer address in this descriptor.
Page 887: Figure 341. Txdma Operation In Osf Mode
RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Figure 341. TxDMA operation in OSF mode Start TxDMA Stop TxDMA Start (Re-)fetch next descriptor (AHB) Poll error? demand TxDMA suspended bit set? Previous frame Transfer data from status available buffer(s) (AHB) Time stamp...
Page 888: Figure 342. Normal Transmit Descriptor
Ethernet (ETH): media access control (MAC) with DMA controller RM0033 indicates the last buffer of the frame. After the last buffer of the frame has been transmitted, the DMA writes back the final status information to the transmit descriptor 0 (TDES0) word of the descriptor that has the last segment set in transmit descriptor 0 (TDES0[29]).
Page 889 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller • TDES0: Transmit descriptor Word0 The application software has to program the control bits [30:26]+[23:20] plus the OWN bit [31] during descriptor initialization. When the DMA updates the descriptor (or writes it back), it resets all the control bits plus the OWN bit, and reports only the status bits.
Page 890 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Bit 21 TER: Transmit end of ring When set, this bit indicates that the descriptor list reached its final descriptor. The DMA returns to the base address of the list, creating a descriptor ring. Bit 20 TCH: Second address chained When set, this bit indicates that the second address in the descriptor is the next descriptor address rather than the second buffer address.
Page 891 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Bit 11 LCA: Loss of carrier When set, this bit indicates that a loss of carrier occurred during frame transmission (that is, the MII_CRS signal was inactive for one or more transmit clock periods during frame transmission).
Page 892 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 28:16 TBS2: Transmit buffer 2 size These bits indicate the second data buffer size in bytes. This field is not valid if TDES0[20] is set. 15:13 Reserved, must be kept at reset value. 12:0 TBS1: Transmit buffer 1 size These bits indicate the first data buffer byte size, in bytes.
Page 893 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Bits 31:0 TBAP2: Transmit buffer 2 address pointer (Next descriptor address) / Transmit frame time stamp high These bits have two different functions: they indicate to the DMA the location of data in memory, and after all data are transferred, the DMA can then use these bits to pass back time stamp data.
Page 894: Figure 343. Enhanced Transmit Descriptor
Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Figure 343. Enhanced transmit descriptor Ctrl Res. Ctrl Reserved Status [16:0] TDES 0 [30:26] [23:20] [19:18] Reserved Buffer 2 byte count Reserved Buffer 1 byte count TDES 1 [31:29] [28:16] [15:13] [12:0] TDES 2...
Page 895: Rx Dma Configuration
RM0033 Ethernet (ETH): media access control (MAC) with DMA controller • TDES7: Transmit descriptor Word7 31 30 29 28 27 26 25 23 22 21 20 19 18 17 16 15 14 13 12 11 10 TTSH Bits 31:0 TTSH: Transmit frame time stamp high This field is updated by DMA with the 32 most significant bits of the time stamp captured for the corresponding transmit frame.
Page 896: Figure 344. Receive Dma Operation
Ethernet (ETH): media access control (MAC) with DMA controller RM0033 The DMA does not acknowledge accepting the status until it has completed the time stamp write-back and is ready to perform status write-back to the descriptor. If software has enabled time stamping through CSR, when a valid time stamp value is not available for the frame (for example, because the receive FIFO was full before the time stamp could be written to it), the DMA writes all ones to RDES2 and RDES3.
Page 897 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Receive descriptor acquisition The receive engine always attempts to acquire an extra descriptor in anticipation of an incoming frame. Descriptor acquisition is attempted if any of the following conditions is/are satisfied: •...
Page 898: Figure 345. Normal Rx Dma Descriptor Structure
Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Normal Rx DMA descriptors The normal receive descriptor structure consists of four 32-bit words (16 bytes). These are shown in Figure 345. The bit descriptions of RDES0, RDES1, RDES2 and RDES3 are given below.
Page 899 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Bit 15 ES: Error summary Indicates the logical OR of the following bits: RDES0[1]: CRC error RDES0[3]: Receive error RDES0[4]: Watchdog timeout RDES0[6]: Late collision RDES0[7]: Giant frame (This is not applicable when RDES0[7] indicates an IPV4 header checksum error.) RDES0[11]: Overflow error RDES0[14]: Descriptor error.
Page 900 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Bit 5 FT: Frame type When set, this bit indicates that the Receive frame is an Ethernet-type frame (the LT field is greater than or equal to 0x0600). When this bit is reset, it indicates that the received frame is an IEEE802.3 frame.
Page 901: Table 146. Receive Descriptor 0 - Encoding For Bits 7, 5 And
RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Table 146. Receive descriptor 0 - encoding for bits 7, 5 and 0 (normal descriptor format only, EDFE=0) Bit 5: Bit 7: IPC Bit 0: payload frame checksum checksum Frame status type error error...
Page 902 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Bit 14 RCH: Second address chained When set, this bit indicates that the second address in the descriptor is the next descriptor address rather than the second buffer address. When this bit is set, RBS2 (RDES1[28:16]) is a “don’t care”...
Page 903 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller • RDES3: Receive descriptor Word3 RDES3 contains the address pointer either to the second data buffer in the descriptor or to the next descriptor, or it contains time stamp data. 31 30 29 28 27 26 25 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RBP2 / RTSH...
Page 904: Figure 346. Enhanced Receive Descriptor Field Format With Ieee1588 Time Stamp Enabled
Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Figure 346. Enhanced receive descriptor field format with IEEE1588 time stamp enabled RDES 0 Status [30:0] Reserved Buffer 2 byte count CTRL Buffer 1 byte count RDES 1 Res. [30:29] [28:16] [15:14] [12:0]...
Page 905 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Bits 11:8 PMT: PTP message type These bits are encoded to give the type of the message received. – 0000: No PTP message received – 0001: SYNC (all clock types) –...
Page 906: Dma Interrupts
Ethernet (ETH): media access control (MAC) with DMA controller RM0033 31 30 29 28 27 26 25 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RTSL rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 RTSL: Receive frame time stamp low The DMA updates this field with the 32 least significant bits of the time stamp captured for the corresponding receive frame.
Page 907: Ethernet Interrupts
RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Figure 347. Interrupt scheme MMCI PMTI TBUS TSTI TBUIE NISE ERIE Interrupt FBES TPSS FBEIE TJTS TPSSIE TJTIE AISE ROIE TUIE RPSS RWTS RBUIE RPSSIE RWTIE ETIE AI15646 28.7 Ethernet interrupts The Ethernet controller has two interrupt vectors: one dedicated to normal Ethernet operations and the other, used only for the Ethernet wakeup event (with wakeup frame or Magic Packet detection) when it is mapped on EXTI lIne19.
Page 908: Ethernet Register Descriptions
Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Note: Reading the PMT control and status register automatically clears the Wakeup Frame Received and Magic Packet Received PMT interrupt flags. However, since the registers for these flags are in the CLK_RX domain, there may be a significant delay before this update is visible by the firmware.
Page 909 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Bits 19:17 IFG: Interframe gap These bits control the minimum interframe gap between frames during transmission. 000: 96 bit times 001: 88 bit times 010: 80 bit times …. 111: 40 bit times Note: In Half-duplex mode, the minimum IFG can be configured for 64 bit times (IFG = 100) only.
Page 910 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Bit 7 APCS: Automatic pad/CRC stripping When this bit is set, the MAC strips the Pad/FCS field on incoming frames only if the length’s field value is less than or equal to 1 500 bytes. All received frames with length field greater than or equal to 1 501 bytes are passed on to the application without stripping the Pad/FCS field.
Page 911 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Ethernet MAC frame filter register (ETH_MACFFR) Address offset: 0x0004 Reset value: 0x0000 0000 The MAC frame filter register contains the filter controls for receiving frames. Some of the controls from this register go to the address check block of the MAC, which performs the first level of address filtering.
Page 912 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Bits 7:6 PCF: Pass control frames These bits control the forwarding of all control frames (including unicast and multicast PAUSE frames). Note that the processing of PAUSE control frames depends only on RFCE in Flow Control Register[2].
Page 913 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller is a 32-bit value coded by the following polynomial (for more details refer to Section 28.5.3: MAC frame reception): G x ( ) The most significant bit determines the register to be used (hash table high/hash table low), and the other 5 bits determine which bit within the register.
Page 914 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Bits 31:16 Reserved, must be kept at reset value. Bits 15:11 PA: PHY address This field tells which of the 32 possible PHY devices are being accessed. Bits 10:6 MR: MII register These bits select the desired MII register in the selected PHY device.
Page 915 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Ethernet MAC flow control register (ETH_MACFCR) Address offset: 0x0018 Reset value: 0x0000 0000 The Flow control register controls the generation and reception of the control (Pause Command) frames by the MAC. A write to a register with the Busy bit set to '1' causes the MAC to generate a pause control frame.
Page 916 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Bit 2 RFCE: Receive flow control enable When this bit is set, the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause Time) time. When this bit is reset, the decode function of the Pause frame is disabled. Bit 1 TFCE: Transmit flow control enable In Full-duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames.
Page 917: Figure 348. Ethernet Mac Remote Wakeup Frame Filter Register (Eth_Macrwuffr)
RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Bits 31:17 Reserved, must be kept at reset value. Bit 16 VLANTC: 12-bit VLAN tag comparison When this bit is set, a 12-bit VLAN identifier, rather than the complete 16-bit VLAN tag, is used for comparison and filtering.
Page 918 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Ethernet MAC PMT control and status register (ETH_MACPMTCSR) Address offset: 0x002C Reset value: 0x0000 0000 The ETH_MACPMTCSR programs the request wakeup events and monitors the wakeup events. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved Res.
Page 919 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Ethernet MAC debug register (ETH_MACDBGR) Address offset: 0x0034 Reset value: 0x0000 0000 This debug register gives the status of all the main modules of the transmit and receive data paths and the FIFOs. An all-zero status indicates that the MAC core is in Idle state (and FIFOs are empty) and no activity is going on in the data paths.
Page 920 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Bits 9:8 RFFL: Rx FIFO fill level This gives the status of the Rx FIFO fill-level: 00: RxFIFO empty 01: RxFIFO fill-level below flow-control de-activate threshold 10: RxFIFO fill-level above flow-control activate threshold 11: RxFIFO full Bit 7 Reserved, must be kept at reset value.
Page 921 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Ethernet MAC interrupt status register (ETH_MACSR) Address offset: 0x0038 Reset value: 0x0000 0000 The ETH_MACSR register contents identify the events in the MAC that can generate an interrupt. TSTS MMCTS MMCRS MMCS PMTS Reserved Reserved...
Page 922 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Ethernet MAC interrupt mask register (ETH_MACIMR) Address offset: 0x003C Reset value: 0x0000 0000 The ETH_MACIMR register bits make it possible to mask the interrupt signal due to the corresponding event in the ETH_MACSR register. TSTIM PMTIM Reserved...
Page 923 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Ethernet MAC address 0 low register (ETH_MACA0LR) Address offset: 0x0044 Reset value: 0xFFFF FFFF The MAC address 0 low register holds the lower 32 bits of the 6-byte first MAC address of the station.
Page 924 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Bits 29:24 MBC: Mask byte control These bits are mask control bits for comparison of each of the MAC address1 bytes. When they are set high, the MAC core does not compare the corresponding byte of received DA/SA with the contents of the MAC address1 registers.
Page 925 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Bit 31 AE: Address enable When this bit is set, the address filters use the MAC address2 for perfect filtering. When reset, the address filters ignore the address for filtering. Bit 30 SA: Source address When this bit is set, the MAC address 2 [47:0] is used for comparison with the SA fields of the received frame.
Page 926 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Ethernet MAC address 3 high register (ETH_MACA3HR) Address offset: 0x0058 Reset value: 0x0000 FFFF The MAC address 3 high register holds the upper 16 bits of the 6-byte second MAC address of the station.
Page 927: Mmc Register Description
RM0033 Ethernet (ETH): media access control (MAC) with DMA controller 28.8.2 MMC register description Ethernet MMC control register (ETH_MMCCR) Address offset: 0x0100 Reset value: 0x0000 0000 The Ethernet MMC Control register establishes the operating mode of the management counters. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved rw rw rw rw rw rw Bits 31:6 Reserved, must be kept at reset value.
Page 928 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 caused the interrupt is read. The least significant byte lane (bits [7:0]) of the respective counter must be read in order to clear the interrupt bit. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 16 15 14 13 12 11 10 Reserved Reserved...
Page 929 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Bit 15 TGFMSCS: Transmitted good frames more single collision status This bit is set when the transmitted, good frames after more than a single collision, counter reaches half the maximum value. Bit 14 TGFSCS: Transmitted good frames single collision status This bit is set when the transmitted, good frames after a single collision, counter reaches half the maximum value.
Page 930 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR) Address offset: 0x0110 Reset value: 0x0000 0000 The Ethernet MMC transmit interrupt mask register maintains the masks for interrupts generated when the transmit statistic counters reach half their maximum value. (MSB of the counter is set).
Page 931 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Ethernet MMC transmitted good frames after more than a single collision counter register (ETH_MMCTGFMSCCR) Address offset: 0x0150 Reset value: 0x0000 0000 This register contains the number of successfully transmitted frames after more than a single collision in Half-duplex mode.
Page 932: Ieee 1588 Time Stamp Registers
Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Ethernet MMC received frames with alignment error counter register (ETH_MMCRFAECR) Address offset: 0x0198 Reset value: 0x0000 0000 This register contains the number of frames received with alignment (dribble) error. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RFAEC Bits 31:0 RFAEC: Received frames alignment error counter Received frames with alignment error counter...
Page 933 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Bits 31:19 Reserved, must be kept at reset value. Bit 18 TSPFFMAE: Time stamp PTP frame filtering MAC address enable When set, this bit uses the MAC address (except for MAC address 0) to filter the PTP frames when PTP is sent directly over Ethernet.
Page 934: Table 147. Time Stamp Snapshot Dependency On Registers Bits
Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Bit 4 TSITE: Time stamp interrupt trigger enable When this bit is set, a time stamp interrupt is generated when the system time becomes greater than the value written in the Target time register. When the Time stamp trigger interrupt is generated, this bit is cleared.
Page 935 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Ethernet PTP subsecond increment register (ETH_PTPSSIR) Address offset: 0x0704 Reset value: 0x0000 0000 This register contains the 8-bit value by which the subsecond register is incremented. In Coarse update mode (TSFCU bit in ETH_PTPTSCR), the value in this register is added to the system time every clock cycle of HCLK.
Page 936 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Ethernet PTP time stamp low register (ETH_PTPTSLR) Address offset: 0x070C Reset value: 0x0000 0000 This register contains the least significant (lower) 32 time bits. This read-only register contains the subsecond system time value. 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STSS Bit 31 STPNS: System time positive or negative sign...
Page 937 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Ethernet PTP time stamp low update register (ETH_PTPTSLUR) Address offset: 0x0714 Reset value: 0x0000 0000 This register contains the least significant (lower) 32 bits of the time to be written to, added to, or subtracted from the System Time value.
Page 938 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Ethernet PTP target time high register (ETH_PTPTTHR) Address offset: 0x071C Reset value: 0x0000 0000 This register contains the higher 32 bits of time to be compared with the system time for interrupt event generation.
Page 939 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Bits 31:2 Reserved, must be kept at reset value. Bit 1 TSTTR: Time stamp target time reached When set, this bit indicates that the value of the system time is greater than or equal to the value specified in the Target time high and low registers.
Page 940: Dma Register Description
Ethernet (ETH): media access control (MAC) with DMA controller RM0033 28.8.4 DMA register description This section defines the bits for each DMA register. Non-32 bit accesses are allowed as long as the address is word-aligned. Ethernet DMA bus mode register (ETH_DMABMR) Address offset: 0x1000 Reset value: 0x0002 0101 The bus mode register establishes the bus operating modes for the DMA.
Page 941 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Bits 15:14 PM: Rx Tx priority ratio RxDMA requests are given priority over TxDMA requests in the following ratio: 00: 1:1 01: 2:1 10: 3:1 11: 4:1 This is valid only when the DA bit is cleared. Bits 13:8 PBL: Programmable burst length These bits indicate the maximum number of beats to be transferred in one DMA transaction.
Page 942 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 transmit DMA. You can issue this command anytime and the TxDMA resets it once it starts re-fetching the current descriptor from host memory. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 rw_wt Bits 31:0 TPD: Transmit poll demand When these bits are written with any value, the DMA reads the current descriptor pointed to...
Page 943 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Bits 31:0 SRL: Start of receive list This field contains the base address of the first descriptor in the receive descriptor list. The LSB bits [1/2/3:0] for 32/64/128-bit bus width) are internally ignored and taken as all-zero by the DMA.
Page 944 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Bits 31:30 Reserved, must be kept at reset value. Bit 29 TSTS: Time stamp trigger status This bit indicates an interrupt event in the MAC core's Time stamp generator block. The software must read the MAC core’s status register, clearing its source (bit 9), to reset this bit to 0.
Page 945 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Bit 16 NIS: Normal interrupt summary The normal interrupt summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the ETH_DMAIER register: –...
Page 946 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Bit 6 RS: Receive status This bit indicates the completion of the frame reception. Specific frame status information has been posted in the descriptor. Reception remains in the Running state. Bit 5 TUS: Transmit underflow status This bit indicates that the transmit buffer had an underflow during frame transmission.
Page 947 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Bits 31:27 Reserved, must be kept at reset value. Bit 26 DTCEFD: Dropping of TCP/IP checksum error frames disable When this bit is set, the core does not drop frames that only have errors detected by the receive checksum offload engine.
Page 948 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Bit 13 ST: Start/stop transmission When this bit is set, transmission is placed in the Running state, and the DMA checks the transmit list at the current position for a frame to be transmitted. Descriptor acquisition is...
Page 949 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Bit 2 OSF: Operate on second frame When this bit is set, this bit instructs the DMA to process a second frame of Transmit data even before status for first frame is obtained. Bit 1 SR: Start/stop receive When this bit is set, the receive process is placed in the Running state.
Page 950 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Ethernet DMA interrupt enable register (ETH_DMAIER) Address offset: 0x101C Reset value: 0x0000 0000 The Interrupt enable register enables the interrupts reported by ETH_DMASR. Setting a bit to 1 enables a corresponding interrupt. After a hardware or software reset, all interrupts are disabled.
Page 951 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Bit 9 RWTIE: receive watchdog timeout interrupt enable When this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER register[15]), the receive watchdog timeout interrupt is enabled. When this bit is cleared, the receive watchdog timeout interrupt is disabled. Bit 8 RPSIE: Receive process stopped interrupt enable When this bit is set with the abnormal interrupt summary enable bit (ETH_DMAIER register[15]), the receive stopped interrupt is enabled.
Page 952 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Ethernet DMA missed frame and buffer overflow counter register (ETH_DMAMFBOCR) Address offset: 0x1020 Reset value: 0x0000 0000 The DMA maintains two counters to track the number of missed frames during reception. This register reports the current value of the counter.
Page 953 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Ethernet DMA current host transmit descriptor register (ETH_DMACHTDR) Address offset: 0x1048 Reset value: 0x0000 0000 The Current host transmit descriptor register points to the start address of the current transmit descriptor read by the DMA. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 HTDAP Bits 31:0 HTDAP: Host transmit descriptor address pointer...
Page 954: Ethernet Register Maps
Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Ethernet DMA current host receive buffer address register (ETH_DMACHRBAR) Address offset: 0x1054 Reset value: 0x0000 0000 The current host receive buffer address register points to the current receive buffer address being read by the DMA.
Page 955 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Table 148. Ethernet register map and reset values (continued) Offset Register ETH_ 0x2C MACPMTCSR Reserved Reset value ETH_ MACDBGR 0x34 Reserved Reset value ETH_MACSR Reserve 0x38 Reserved Reset value ETH_MACIMR Reserve 0x3C Reserved...
Page 956 Ethernet (ETH): media access control (MAC) with DMA controller RM0033 Table 148. Ethernet register map and reset values (continued) Offset Register ETH_MMCTIMR 0x110 Reserved Reserved Reserved Reset value ETH_MMCTGFS TGFSCC 0x14C Reset value ETH_MMCTGF TGFMSCC MSCCR 0x150 Reset value ETH_MMCTGF TGFC 0x168 Reset value...
Page 957 RM0033 Ethernet (ETH): media access control (MAC) with DMA controller Table 148. Ethernet register map and reset values (continued) Offset Register ETH_PTPTSSR 0x728 Reserved Reset value ETH_PTPPPSC FREQ 0x72C Reserved Reset value ETH_DMABMR 0x1000 Reserved Reset value ETH_DMATPDR 0x1004 Reset value ETH_DMARPDR 0x1008 Reset value...
Page 958: Usb On-The-Go Full-Speed (Otg_Fs)
USB on-the-go full-speed (OTG_FS) RM0033 USB on-the-go full-speed (OTG_FS) This section applies to the whole STM32F20x and STM32F21x family, unless otherwise specified. 29.1 OTG_FS introduction Portions Copyright (c) 2004, 2005 Synopsys, Inc. All rights reserved. Used with permission. This section presents the architecture and the programming model of the OTG_FS controller.
Page 959: Otg_Fs Main Features
RM0033 USB on-the-go full-speed (OTG_FS) 29.2 OTG_FS main features The main features can be divided into three categories: general, host-mode and device- mode features. 29.2.1 General features The OTG_FS interface general features are the following: • It is USB-IF certified to the Universal Serial Bus Specification Rev 2.0 •...
Page 960: Host-Mode Features
USB on-the-go full-speed (OTG_FS) RM0033 29.2.2 Host-mode features The OTG_FS interface main features and requirements in host-mode are the following: • External charge pump for V voltage generation. • Up to 8 host channels (pipes): each channel is dynamically reconfigurable to allocate any type of USB transfer.
Page 961: Otg_Fs Functional Description
RM0033 USB on-the-go full-speed (OTG_FS) 29.3 OTG_FS functional description Figure 349. OTG full-speed block diagram ® Cortex core OTG_FS_DP Power USB2.0 OTG_FS_DM OTG FS UTMIFS clock OTG_FS_ID core controller USB suspend USB clock OTG_FS_VBUS USB clock at 48 MHz System clock domain domain Universal serial bus OTG_FS_SOF...
Page 962: Full-Speed Otg Phy
USB on-the-go full-speed (OTG_FS) RM0033 The CPU submits data over the USB by writing 32-bit words to dedicated OTG_FS locations (push registers). The data are then automatically stored into Tx-data FIFOs configured within the USB data RAM. There is one Tx-FIFO push register for each in-endpoint (peripheral mode) or out-channel (host mode).
Page 963: Otg Dual Role Device (Drd)
RM0033 USB on-the-go full-speed (OTG_FS) 29.4 OTG dual role device (DRD) Figure 350. OTG A-B device connection 5 V to V voltage regulator STM32 MCU STMPS2141STR GPIO Current-limited 5 V Pwr power distribution Overcurrent GPIO+IRQ switch VBUS PA11 OSC_IN PA12 PA10 OSC_OUT MS19904V4...
Page 964: Srp Dual Role Device
USB on-the-go full-speed (OTG_FS) RM0033 29.4.3 SRP dual role device The SRP capable bit in the global USB configuration register (SRPCAP bit in OTG_FS_GUSBCFG) enables the OTG_FS core to switch off the generation of V the A-device to save power. Note that the A-device is always in charge of driving V regardless of the host or peripheral role of the OTG_FS.
Page 965: Srp-Capable Peripheral
RM0033 USB on-the-go full-speed (OTG_FS) Figure 351. USB peripheral-only connection 5V to V Volatge regulator STM32 MCU VBUS PA11 OSC_IN PA12 OSC_OUT MS19905V4 1. Use a regulator to build a bus-powered device. 29.5.1 SRP-capable peripheral The SRP capable bit in the Global USB configuration register (SRPCAP bit in OTG_FS_GUSBCFG) enables the OTG_FS to support the session request protocol (SRP).
Page 966: Peripheral Endpoints
USB on-the-go full-speed (OTG_FS) RM0033 Soft disconnect The powered state can be exited by software with the soft disconnect feature. The DP pull- up resistor is removed by setting the soft disconnect bit in the device control register (SDIS bit in OTG_FS_DCTL), causing a device disconnect detection interrupt on the host side even though the USB cable was not really removed from the host port.
Page 967 RM0033 USB on-the-go full-speed (OTG_FS) on which the transfer is not completed in the current frame. This interrupt is asserted along with the end of periodic frame interrupt (OTG_FS_GINTSTS/EOPF). • 3 OUT endpoints – Each of them can be configured to support the isochronous, bulk or interrupt transfer type –...
Page 968: Usb Host
USB on-the-go full-speed (OTG_FS) RM0033 Endpoint status/interrupt The device endpoint-x interrupt registers (DIEPINTx/DOPEPINTx) indicate the status of an endpoint with respect to USB- and AHB-related events. The application must read these registers when the OUT endpoint interrupt bit or the IN endpoint interrupt bit in the core interrupt register (OEPINT bit in OTG_FS_GINTSTS or IEPINT bit in OTG_FS_GINTSTS, respectively) is set.
Page 969: Srp-Capable Host
RM0033 USB on-the-go full-speed (OTG_FS) the 5 V V line. The external charge pump can be driven by any GPIO output. This is required for the OTG A-host, A-device and host-only configurations. The V input ensures that valid V levels are supplied by the charge pump during USB operations while the charge pump overcurrent output can be input to any GPIO pin configured to generate port interrupts.
Page 970 USB on-the-go full-speed (OTG_FS) RM0033 valid When HNP or SRP is enabled the VBUS sensing pin (PA9) pin should be connected to . The V input ensures that valid V levels are supplied by the charge pump during USB operations. Any unforeseen V voltage drop below the V valid threshold (4.25 V) leads to an OTG interrupt triggered by the session end detected bit (SEDET bit in...
Page 971: Host Channels
RM0033 USB on-the-go full-speed (OTG_FS) Host suspend The application decides to suspend the USB activity by setting the port suspend bit in the host port control and status register (PSUSP bit in OTG_FS_HPRT). The OTG_FS core stops sending SOFs and enters the suspended state. The suspended state can be optionally exited on the remote device’s initiative (remote wakeup).
Page 972: Host Scheduler
USB on-the-go full-speed (OTG_FS) RM0033 is enabled the packet count field is read-only as the OTG FS core updates it according to the current transfer status. • The following transfer parameters can be programmed: – transfer size in bytes – number of packets making up the overall transfer size –...
Page 973: Sof Trigger
RM0033 USB on-the-go full-speed (OTG_FS) responsible for the management of the periodic and nonperiodic request queues.The periodic transmit FIFO and queue status register (HPTXSTS) and nonperiodic transmit FIFO and queue status register (HNPTXSTS) are read-only registers which can be used by the application to read the status of each request queue.
Page 974: Peripheral Sofs
USB on-the-go full-speed (OTG_FS) RM0033 is generated at any start of frame (SOF bit in OTH_FS_GINTSTS). The current frame number and the time remaining until the next SOF are tracked in the host frame number register (HFNUM). An SOF pulse signal, generated at any SOF starting token and with a width of 20 HCLK cycles, can be made available externally on the OTG_FS_SOF pin using the SOFOUTEN bit in the global control and configuration register.
Page 975: Dynamic Update Of The Otg_Fs_Hfir Register
RM0033 USB on-the-go full-speed (OTG_FS) The power consumption of the OTG PHY is controlled by three bits in the general core configuration register: • PHY power down (GCCFG/PWRDWN) It switches on/off the full-speed transceiver module of the PHY. It must be preliminarily set to allow any USB operation.
Page 976: Usb Data Fifos
USB on-the-go full-speed (OTG_FS) RM0033 Figure 354. Updating OTG_FS_HFIR dynamically Old OTG_FS_HIFR value OTG_FS_HIFR value New OTG_FS_HIFR value = 400 periods = 450 periods+HIFR write latency = 450 periods reload Latency OTG_FS_HFIR write OTG_FS_HFIR value Frame … … … … timer ai184 29.10...
Page 977: Peripheral Fifo Architecture
RM0033 USB on-the-go full-speed (OTG_FS) 29.11 Peripheral FIFO architecture Figure 355. Device-mode FIFO address mapping and AHB FIFO access mapping Single data FIFO DIEPTXF2[31:16] IN endpoint Tx FIFO #n Dedicated Tx Tx FIFO #n DFIFO push access packet FIFO #n control DIEPTXFx[15:0] from AHB (optional)
Page 978: Peripheral Tx Fifos
USB on-the-go full-speed (OTG_FS) RM0033 29.11.2 Peripheral Tx FIFOs The core has a dedicated FIFO for each IN endpoint. The application configures FIFO sizes by writing the non periodic transmit FIFO size register (OTG_FS_TX0FSIZ) for IN endpoint0 and the device IN endpoint transmit FIFOx registers (DIEPTXFx) for IN endpoint-x. 29.12 Host FIFO architecture Figure 356.
Page 979: Host Tx Fifos
RM0033 USB on-the-go full-speed (OTG_FS) 29.12.2 Host Tx FIFOs The host uses one transmit FIFO for all non-periodic (control and bulk) OUT transactions and one transmit FIFO for all periodic (isochronous and interrupt) OUT transactions. FIFOs are used as transmit buffers to hold the data (payload of the transmit packet) to be transmitted over the USB.
Page 980: Host Mode
USB on-the-go full-speed (OTG_FS) RM0033 Transmit FIFO RAM allocation: the minimum RAM space required for each IN Endpoint Transmit FIFO is the maximum packet size for that particular IN endpoint. Note: More space allocated in the transmit IN Endpoint FIFO results in better performance on the USB.
Page 981: Otg_Fs Interrupts
RM0033 USB on-the-go full-speed (OTG_FS) – It has a lot of empty space available in the receive buffer to autonomously fill it in with the data coming from the USB As the OTG_FS core is able to fill in the 1.25 Kbyte RAM buffer very efficiently, and as 1.25 Kbyte of transmit/receive data is more than enough to cover a full speed frame, the USB system is able to withstand the maximum full-speed data rate for up to one USB frame (1 ms) without any CPU intervention.
Page 982: Figure 357. Interrupt Hierarchy
USB on-the-go full-speed (OTG_FS) RM0033 Figure 357. Interrupt hierarchy Wakeup interrupt OTG_FS_WKUP Global interrupt OTG_FS Global interrupt mask (bit 0) OTG_AHBCFG AHB configuration register OTG_GINTSTS Core register interrupt 31:26 25 24 23:20 19 18 17:3 OTG_GINTMSK Core interrupt mask register OTG_GOTGINT OTG interrupt register (15 + #EP):16...
Page 983: Otg_Fs Control And Status Registers
RM0033 USB on-the-go full-speed (OTG_FS) 29.16 OTG_FS control and status registers By reading from and writing to the control and status registers (CSRs) through the AHB slave interface, the application controls the OTG_FS controller. These registers are 32 bits wide, and the addresses are 32-bit block aligned. The OTG_FS registers must be accessed by words (32 bits).
Page 984: Csr Memory Map
USB on-the-go full-speed (OTG_FS) RM0033 29.16.1 CSR memory map The host and device mode registers occupy different addresses. All registers are implemented in the AHB clock domain. Figure 358. CSR memory map 0000h Core global CSRs (1 Kbyte) 0400h Host mode CSRs (1 Kbyte) 0800h Device mode CSRs (1.5 Kbyte) 0E00h...
Page 985: Table 152. Host-Mode Control And Status Registers (Csrs)
RM0033 USB on-the-go full-speed (OTG_FS) Table 151. Core global control and status registers (CSRs) (continued) Address Acronym Register name offset OTG_FS_GINTSTS 0x014 OTG_FS core interrupt register (OTG_FS_GINTSTS) on page 997 OTG_FS_GINTMSK 0x018 OTG_FS interrupt mask register (OTG_FS_GINTMSK) on page 1001 OTG_FS_GRXSTSR 0x01C OTG_FS Receive status debug read/OTG status read and pop registers...
Page 986: Table 153. Device-Mode Control And Status Registers
USB on-the-go full-speed (OTG_FS) RM0033 Table 152. Host-mode control and status registers (CSRs) (continued) Offset Acronym Register name address OTG_FS Host port control and status register (OTG_FS_HPRT) on OTG_FS_HPRT 0x440 page 1013 0x500 0x520 OTG_FS Host channel-x characteristics register (OTG_FS_HCCHARx) OTG_FS_HCCHARx (x = 0..7, where x = Channel_number) on page 1016 0x5E0...
Page 987: Table 154. Data Fifo (Dfifo) Access Register Map
RM0033 USB on-the-go full-speed (OTG_FS) Table 153. Device-mode control and status registers (continued) Offset Acronym Register name address 0x920 OTG device endpoint x control register (OTG_FS_DIEPCTLx) (x = 1..3, OTG_FS_DIEPCTLx 0x940 where x = Endpoint_number) on page 1029 0x960 OTG_FS device endpoint-x interrupt register (OTG_FS_DIEPINTx) OTG_FS_DIEPINTx 0x908 (x = 0..3, where x = Endpoint_number) on page 1036...
Page 988: Table 155. Power And Clock Gating Control And Status Registers
USB on-the-go full-speed (OTG_FS) RM0033 Table 154. Data FIFO (DFIFO) access register map (continued) FIFO access register section Address range Access Device IN Endpoint x /Host OUT Channel x : DFIFO Write Access 0xX000–0xXFFC Device OUT Endpoint x /Host IN Channel x : DFIFO Read Access 1.
Page 989: Otg_Fs Global Registers
RM0033 USB on-the-go full-speed (OTG_FS) 29.16.2 OTG_FS global registers These registers are available in both host and device modes, and do not need to be reprogrammed when switching between these modes. Bit values in the register descriptions are expressed in binary unless otherwise specified. OTG_FS control and status register (OTG_FS_GOTGCTL) Address offset: 0x000 Reset value: 0x0001 0000...
Page 990 USB on-the-go full-speed (OTG_FS) RM0033 Bit 11 DHNPEN: Device HNP enabled The application sets this bit when it successfully receives a SetFeature.SetHNPEnable command from the connected USB host. 0: HNP is not enabled in the application 1: HNP is enabled in the application Note: Only accessible in device mode.
Page 991 RM0033 USB on-the-go full-speed (OTG_FS) The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 16 15 14 13 12 11 10 Reserved Reserved...
Page 992 USB on-the-go full-speed (OTG_FS) RM0033 OTG_FS AHB configuration register (OTG_FS_GAHBCFG) Address offset: 0x008 Reset value: 0x0000 0000 This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming.
Page 993 RM0033 USB on-the-go full-speed (OTG_FS) OTG_FS USB configuration register (OTG_FS_GUSBCFG) Address offset: 0x00C Reset value: 0x0000 1440 This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB.
Page 994: Table 156. Trdt Values
USB on-the-go full-speed (OTG_FS) RM0033 Bit 8 SRPCAP: SRP-capable The application uses this bit to control the OTG_FS controller’s SRP capabilities. If the core operates as a non-SRP-capable B-device, it cannot request the connected A-device (host) to activate V and start a session.
Page 995 RM0033 USB on-the-go full-speed (OTG_FS) OTG_FS reset register (OTG_FS_GRSTCTL) Address offset: 0x010 Reset value: 0x8000 0000 The application uses this register to reset various hardware features inside the core. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 TXFNUM Reserved Bit 31 AHBIDL: AHB master idle...
Page 996 USB on-the-go full-speed (OTG_FS) RM0033 Bit 2 FCRST: Host frame counter reset The application writes this bit to reset the frame number counter inside the core. When the frame counter is reset, the subsequent SOF sent out by the core has a frame number of 0. Note: Only accessible in host mode.
Page 997 RM0033 USB on-the-go full-speed (OTG_FS) OTG_FS core interrupt register (OTG_FS_GINTSTS) Address offset: 0x014 Reset value: 0x0400 0020 This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode, while others are valid in device mode only.
Page 998 USB on-the-go full-speed (OTG_FS) RM0033 Bit 25 HCINT: Host channels interrupt The core sets this bit to indicate that an interrupt is pending on one of the channels of the core (in host mode). The application must read the OTG_FS_HAINT register to determine the exact number of the channel on which the interrupt occurred, and then read the corresponding OTG_FS_HCINTx register to determine the exact cause of the interrupt.
Page 999 RM0033 USB on-the-go full-speed (OTG_FS) Bit 14 ISOODRP: Isochronous OUT packet dropped interrupt The core sets this bit when it fails to write an isochronous OUT packet into the RxFIFO because the RxFIFO does not have enough space to accommodate a maximum size packet for the isochronous OUT endpoint.
Page 1000 USB on-the-go full-speed (OTG_FS) RM0033 Bit 3 SOF: Start of frame In host mode, the core sets this bit to indicate that an SOF (FS), or Keep-Alive (LS) is transmitted on the USB. The application must write a 1 to this bit to clear the interrupt. In device mode, in the core sets this bit to indicate that an SOF token has been received on the USB.

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