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ST STM32F410 Reference Manual

ST STM32F410 Reference Manual

Advanced arm-based 32-bit mcus

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RM0401

Reference manual

®

STM32F410 advanced Arm

-based 32-bit MCUs

Introduction

This reference manual targets application developers. It provides complete information on

how to use the memory and the peripherals of the STM32F410 microcontrollers.

The STM32F410 is a line of microcontrollers with different memory sizes, packages and

peripherals.

For ordering information, mechanical and electrical device characteristics refer to the

datasheets.

®

®

®

For information on the Arm

Cortex

-M4 with FPU core, refer to the Cortex

-M4 with FPU

Technical Reference Manual.

Related documents

Available from STMicroelectronics web site (http://www.st.com):

• STM32F410 datasheet

• PM0214 "STM32F3 Series, STM32F4 Series, STM32L4 Series and STM32L4+ Series

®

®

®

Cortex

-M4 programming manual" for information on Arm

Cortex

-M4 with FPU

November 2018

RM0401 Rev 3

1/771

www.st.com

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Summary of Contents for ST STM32F410

Page 1 This reference manual targets application developers. It provides complete information on how to use the memory and the peripherals of the STM32F410 microcontrollers. The STM32F410 is a line of microcontrollers with different memory sizes, packages and peripherals. For ordering information, mechanical and electrical device characteristics refer to the datasheets.
Page 2: Table Of Contents
Contents RM0401 Contents Documentation conventions ....... . . 34 General information ......... 34 List of abbreviations for registers .
Page 3 RM0401 Contents 3.5.3 Erase ........... 51 3.5.4 Programming .
Page 4: Syscfg External Interrupt Configuration Register
Contents RM0401 4.3.8 Standby mode ..........82 4.3.9 Programming the RTC alternate functions to wake up the device from the Stop and Standby modes .
Page 5 RM0401 Contents 5.3.11 RCC AHB1 peripheral clock enable in low power mode register (RCC_AHB1LPENR) ........121 5.3.12 RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR) .
Page 6 Contents RM0401 6.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..C and H) ......... . 148 6.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..C and H) .
Page 7 RM0401 Contents 8.3.4 Channel selection ........166 8.3.5 Arbiter .
Page 8 Contents RM0401 9.2.2 EXTI block diagram ........203 9.2.3 Wakeup event management .
Page 9 RM0401 Contents 11.3.10 Discontinuous mode ........221 11.4 Data alignment .
Page 10 Contents RM0401 12.5 Single mode functional description ......245 12.5.1 DAC data format ......... 245 12.5.2 DAC channel conversion .
Page 11 RM0401 Contents 13.7.2 Validation conditions ........264 13.8 RNG registers .
Page 12 Contents RM0401 14.4.6 TIM1 event generation register (TIMx_EGR) ....321 14.4.7 TIM1 capture/compare mode register 1 (TIMx_CCMR1) ... 323 14.4.8 TIM1 capture/compare mode register 2 (TIMx_CCMR2) .
Page 13 RM0401 Contents 15.4.2 TIMx control register 2 (TIMx_CR2) ......371 15.4.3 TIMx slave mode control register (TIMx_SMCR) ....372 15.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER) .
Page 14 Contents RM0401 16.3.12 Debug mode ..........411 16.4 TIM9 registers .
Page 15 RM0401 Contents 17.3.3 Clock source ..........443 17.3.4 Debug mode .
Page 16 Contents RM0401 18.7.1 LPTIM interrupt and status register (LPTIM_ISR) ....461 18.7.2 LPTIM interrupt clear register (LPTIM_ICR) ....463 18.7.3 LPTIM interrupt enable register (LPTIM_IER) .
Page 17 RM0401 Contents Real-time clock (RTC) ........486 21.1 Introduction .
Page 18 Contents RM0401 21.6.15 RTC timestamp sub second register (RTC_TSSSR) ....516 21.6.16 RTC calibration register (RTC_CALR) ......516 21.6.17 RTC tamper and alternate function configuration register (RTC_TAFCR) .
Page 19 RM0401 Contents 22.7.4 FMPI2C own address 2 register (FMPI2C_OAR2) ....582 22.7.5 FMPI2C timing register (FMPI2C_TIMINGR) ....583 22.7.6 FMPI2C timeout register (FMPI2C_TIMEOUTR) .
Page 20 Contents RM0401 23.6.11 I2C register map ......... 626 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmitter (UART) .
Page 21 RM0401 Contents 25.1.3 I2S features ..........682 25.2 SPI/I2S implementation .
Page 22 Contents RM0401 25.7.5 SPI CRC polynomial register (SPI_CRCPR) (not used in I mode) ..........726 25.7.6 SPI RX CRC register (SPI_RXCRCR) (not used in I S mode) .
Page 23 RM0401 Contents 26.12 FPB (Flash patch breakpoint) ....... . . 747 26.13 DWT (data watchpoint trigger) .
Page 24 Embedded bootloader interfaces ..........43 Table 4. Memory mapping vs. Boot mode/physical remap in STM32F410 ....44 Table 5.
Page 25 STM32F410 FMPI2C implementation ........
Page 26 Table 124. STM32F410 SPI implementation ........
Page 27 RM0401 List of tables Table 138. Core debug registers ........... . 746 Table 139.
Page 28 List of figures RM0401 List of figures Figure 1. System architecture ............36 Figure 2.
Page 29 RM0401 List of figures Figure 49. Advanced-control timer block diagram ........270 Figure 50.
Page 30 List of figures RM0401 Figure 99. Counter timing diagram with prescaler division change from 1 to 4 ....343 Figure 100. Counter timing diagram, internal clock divided by 1 ......344 Figure 101.
Page 31 RM0401 List of figures Figure 149. PWM input mode timing ..........403 Figure 150.
Page 32 List of figures RM0401 Figure 196. Transfer bus diagrams for FMPI2C master transmitter ......552 Figure 197.
Page 33 RM0401 List of figures Figure 247. TXE/RXNE/BSY behavior in master / full-duplex mode (BIDIMODE=0, RXONLY=0) in the case of continuous transfers ....... 694 Figure 248.
Page 34: Documentation Conventions
Documentation conventions RM0401 Documentation conventions General information ®(a) ® The STM32F410 devices have an Arm Cortex -M4 with FPU core. List of abbreviations for registers The following abbreviations are used in register descriptions: read/write (rw) Software can read and write to this bit.
Page 35: Glossary
RM0401 Documentation conventions Glossary This section gives a brief definition of acronyms and abbreviations used in this document: • The CPU core integrates two debug ports: – JTAG debug port (JTAG-DP) provides a 5-pin standard interface based on the Joint Test Action Group (JTAG) protocol. –...
Page 36: System And Memory Overview
System and memory overview RM0401 System and memory overview System architecture In STM32F410, the main system consists of 32-bit multilayer AHB bus matrix that interconnects: • Six masters: ® – Cortex -M4 with FPU core I-bus, D-bus and S-bus –...
Page 37: I-Bus
RM0401 System and memory overview 2.1.1 I-bus ® This bus connects the Instruction bus of the Cortex -M4 with FPU core to the BusMatrix. This bus is used by the core to fetch instructions. The target of this bus is a memory containing code (internal Flash memory/SRAM1).
Page 38: Memory Organization
RM0401 Memory organization 2.2.1 Introduction Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant.
Page 39: Table 1. Register Boundary Addresses
RM0401 All the memory map areas that are not allocated to on-chip memories and peripherals are considered “Reserved”. For the detailed mapping of available memory and register areas, refer to the following table. The following table gives the boundary addresses of the peripherals available in the devices.
Page 40 RM0401 Table 1. Register boundary addresses (continued) Boundary address Peripheral 0x4001 5400- 0x4001 FFFF Reserved 0x4001 5000 - 0x4001 53FF SPI5/I2S5 0x4001 4C00- 0x4001 4FFF Reserved 0x4001 4800 - 0x4001 4BFF TIM11 0x4001 4400 - 0x4001 47FF Reserved 0x4001 4000 - 0x4001 43FF TIM9 0x4001 3C00 - 0x4001 3FFF EXTI...
Page 41: Embedded Sram
Reserved Embedded SRAM STM32F410 devices feature 32 Kbytes of system SRAM. The embedded SRAM can be accessed as bytes, half-words (16 bits) or full words (32 bits). Read and write operations are performed at CPU speed with 0 wait state.
Page 42: Bit Banding
In the STM32F410 devices both the peripheral registers and the SRAM1 are mapped to a bit-band region, so that single bit-band write and read operations are allowed. The ®...
Page 43: Boot Configuration
(typically, Flash memory). STM32F4xx microcontrollers implement a special mechanism to be able to boot from other memories (like the internal SRAM). In the STM32F410, three different boot modes can be selected through the BOOT[1:0] pins as shown in Table Table 2.
Page 44: Table 4. Memory Mapping Vs. Boot Mode/Physical Remap In Stm32F410
RM0401 The USART peripherals operate at the internal 16 MHz oscillator (HSI) frequency. The embedded bootloader code is located in system memory. It is programmed by ST during production. For additional information, refer to application note AN2606. Physical remap in STM32F410...
Page 45: Embedded Flash Memory Interface
RM0401 Embedded Flash memory interface Embedded Flash memory interface Introduction The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. The Flash memory interface accelerates code execution with a system of instruction prefetch and cache lines.
Page 46: Embedded Flash Memory
Embedded Flash memory interface RM0401 Embedded Flash memory The Flash memory has the following main features: • Capacity up to 128 Kbytes • 128 bits wide data read • Byte, half-word, word and double word write • Sector and mass erase •...
Page 47: Read Interface
RM0401 Embedded Flash memory interface Read interface 3.4.1 Relation between CPU clock frequency and Flash memory read time To correctly read data from Flash memory, the number of wait states (LATENCY) must be correctly programmed in the Flash access control register (FLASH_ACR) according to the frequency of the CPU clock (HCLK) and the supply voltage of the device.
Page 48: Adaptive Real-Time Memory Accelerator (Art Accelerator™)
Embedded Flash memory interface RM0401 Decreasing the CPU frequency Modify the CPU clock source by writing the SW bits in the RCC_CFGR register If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR Check that the new CPU clock source or/and the new CPU clock prescaler value is/are taken into account by reading the clock source status (SWS bits) or/and the AHB prescaler value (HPRE bits), respectively, in the RCC_CFGR register Program the new number of wait states to the LATENCY bits in FLASH_ACR...
Page 49: Figure 4. Sequential 32-Bit Instruction Execution
RM0401 Embedded Flash memory interface Figure 4. Sequential 32-bit instruction execution When the code is not sequential (branch), the instruction may not be present in the currently used instruction line or in the prefetched instruction line. In this case (miss), the penalty in terms of number of cycles is at least equal to the number of wait states.
Page 50: Erase And Program Operations
Embedded Flash memory interface RM0401 Instruction cache memory To limit the time lost due to jumps, it is possible to retain 64 lines of 128 bits in an instruction cache memory. This feature can be enabled by setting the instruction cache enable (ICEN) bit in the FLASH_ACR register.
Page 51: Program/Erase Parallelism
RM0401 Embedded Flash memory interface 3.5.2 Program/erase parallelism The Parallelism size is configured through the PSIZE field in the FLASH_CR register. It represents the number of bytes to be programmed each time a write operation occurs to the Flash memory. PSIZE is limited by the supply voltage and by whether the external V supply is used or not.
Page 52: Programming
Embedded Flash memory interface RM0401 Mass Erase To perform Mass Erase, the following sequence is recommended: Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register Set the MER bit in the FLASH_CR register Set the STRT bit in the FLASH_CR register Wait for the BSY bit to be cleared Note:...
Page 53: Interrupts
RM0401 Embedded Flash memory interface Programming and caches If a Flash memory write access concerns some data in the data cache, the Flash write access modifies the data in the Flash memory and the data in the cache. If an erase operation in Flash memory also concerns data in the data or instruction cache, you have to make sure that these data are rewritten before they are accessed during code execution.
Page 54: Table 10. Description Of The Option Bytes
Embedded Flash memory interface RM0401 Table 10. Description of the option bytes Option bytes (word, address 0x1FFF C000) RDP: Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0xAA: Level 0, no protection Bits 15:8 0xCC: Level 2, chip protection (debug and boot from RAM features disabled) Others: Level 1, read protection of memories (debug features limited)
Page 55: Programming User Option Bytes
RM0401 Embedded Flash memory interface Table 10. Description of the option bytes (continued) nWRP: Flash memory write protection option bytes Section 0 to 4 can be write protected nWRPi If SPRMOD is reset (default value) : 0: Write protection active on sector i. Bits 4:0 1: Write protection not active on sector i.
Page 56 Embedded Flash memory interface RM0401 Flash memory are possible in all boot configurations (Flash user boot, debug or boot from RAM). • Level 1: read protection enabled It is the default read protection level after option byte erase. The read protection Level 1 is activated by writing any value (except for 0xAA and 0xCC used to set Level 0 and Level 2, respectively) into the RDP option byte.
Page 57: Write Protections
RM0401 Embedded Flash memory interface Table 11. Access versus read protection level Debug features, Boot from RAM or Booting from Flash memory Protection from System memory bootloader Memory area Level Read Write Erase Read Write Erase Level 1 Main Flash Memory Level 2 Level 1 Option Bytes...
Page 58: Proprietary Code Readout Protection (Pcrop)
Embedded Flash memory interface RM0401 If an erase/program operation to a write-protected part of the Flash memory is attempted (sector protected by write protection bit, OTP part locked or part of the Flash memory that can never be written like the ICP), the write protection error flag (WRPERR) is set in the FLASH_SR register.
Page 59: Figure 6. Pcrop Levels
RM0401 Embedded Flash memory interface Figure 6. PCROP levels The deactivation of the SPRMOD and/or the unprotection of PCROPed user sectors can only occur when, at the same time, the RDP level changes from 1 to 0. If this condition is not respected, the user option byte modification is canceled and the write error WRPERR flag is set.
Page 60: One-Time Programmable Bytes
Embedded Flash memory interface RM0401 One-time programmable bytes Table 12 shows the organization of the one-time programmable (OTP) part of the OTP area. Table 12. OTP area organization Block [128:96] [95:64] [63:32] [31:0] Address byte 0 OTP0 OTP0 OTP0 OTP0 0x1FFF 7800 OTP0 OTP0...
Page 61: Flash Interface Registers
RM0401 Embedded Flash memory interface Flash interface registers 3.8.1 Flash access control register (FLASH_ACR) The Flash access control register is used to enable/disable the acceleration features and control the Flash memory access time according to CPU frequency. Address offset: 0x00 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res.
Page 62: Flash Key Register (Flash_Keyr)
Embedded Flash memory interface RM0401 3.8.2 Flash key register (FLASH_KEYR) The Flash key register is used to allow access to the Flash control register and so, to allow program and erase operations. Address offset: 0x04 Reset value: 0x0000 0000 Access: no wait state, word access KEY[31:16] KEY[15:0] Bits 31:0 FKEYR: FPEC key...
Page 63: Flash Status Register (Flash_Sr)
RM0401 Embedded Flash memory interface 3.8.4 Flash status register (FLASH_SR) The Flash status register gives information on ongoing program and erase operations. Address offset: 0x0C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res.
Page 64: Flash Control Register (Flash_Cr)
Embedded Flash memory interface RM0401 Bits 3:2 Reserved, must be kept cleared. Bit 1 OPERR: Operation error Set by hardware when a flash operation (programming / erase /read) request is detected and can not be run because of parallelism, alignment, or write protection error. This bit is set only if error interrupts are enabled (ERRIE = 1).
Page 65: Flash Option Control Register (Flash_Optcr)
RM0401 Embedded Flash memory interface Bits 9:8 PSIZE: Program size These bits select the program parallelism. 00 program x8 01 program x16 10 program x32 11 program x64 Bit 7 Reserved, must be kept cleared. Bits 6:3 SNB: Sector number These bits select the sector to erase.
Page 66 Embedded Flash memory interface RM0401 Bit 31 SPRMOD: Selection of Protection Mode of nWPRi bits 0: PCROP disabled, nWPRi bits used for Write Protection on sector i 1: PCROP enabled, nWPRi bits used for PCROP Protection on sector i Bits 30:21 Reserved, must be kept cleared. Bits 20:16 nWRP[4:0]: Not write protect These bits contain the value of the write-protection option bytes of sectors after reset.
Page 67 RM0401 Embedded Flash memory interface Bits 3:2 BOR_LEV: BOR reset Level These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level. By default, BOR is off. When the supply voltage (V drops below the selected BOR level, a device reset is generated.
Page 68: Flash Interface Register Map
Embedded Flash memory interface RM0401 3.8.7 Flash interface register map Table 13. Flash register map and reset values Offset Register FLASH_ACR LATENCY 0x00 Reset value FLASH_KEYR KEY[31:16] KEY[15:0] 0x04 Reset value 0 0 0 FLASH_ OPTKEYR[31:16] OPTKEYR[15:0] OPTKEYR 0x08 Reset value 0 0 0 FLASH_SR 0x0C...
Page 69: Power Controller (Pwr)
RM0401 Power controller (PWR) Power controller (PWR) Power supplies There are two main power supply schemes: • = 1.7 to 3.6 V: external power supply for I/Os with the internal regulator disabled, provided externally through V pins. Requires the use of an external power supply supervisor connected to the V and PDR_ON pins.
Page 70: Independent A/D Converter Supply And Reference Voltage
Power controller (PWR) RM0401 4.1.1 Independent A/D converter supply and reference voltage To improve conversion accuracy, the ADC has an independent power supply which can be separately filtered and shielded from noise on the PCB. • The ADC voltage supply input is available on a separate V pin.
Page 71: Voltage Regulator
RM0401 Power controller (PWR) a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED). When the backup domain is supplied by V (analog switch connected to V because is not present), the following functions are available: •...
Page 72: Power Supply Supervisor
Power controller (PWR) RM0401 regulator can be put either in main regulator mode (MR) or in low-power mode (LPR). The programmed voltage scale remains the same during Stop mode: Voltage scale 3 is automatically selected when the microcontroller enters Stop mode (see Section 4.4.1: PWR power control register (PWR_CR)).
Page 73: Brownout Reset (Bor)
RM0401 Power controller (PWR) 4.2.2 Brownout reset (BOR) During power on, the Brownout reset (BOR) keeps the device under reset until the supply voltage reaches the specified V threshold. is configured through device option bytes. By default, BOR is off. 3 programmable threshold levels can be selected: •...
Page 74: Programmable Voltage Detector (Pvd)
Power controller (PWR) RM0401 4.2.3 Programmable voltage detector (PVD) You can use the PVD to monitor the V power supply by comparing it to a threshold selected by the PLS[2:0] bits in the PWR power control register (PWR_CR) The PVD is enabled by setting the PVDE bit. A PVDO flag is available, in the PWR power control/status register (PWR_CSR), to indicate...
Page 75 RM0401 Power controller (PWR) In addition, the power consumption in Run mode can be reduced by one of the following means: • Optimizing PLL VCO frequency (see Section 4.3.1: Optimizing PLL VCO frequency) • Slowing down the system clocks (see Section 4.3.2: Slowing down system clocks) •...
Page 76: Optimizing Pll Vco Frequency
Power controller (PWR) RM0401 After waking up from Standby mode, program execution restarts in the same way as after a Reset (boot pin sampling, option bytes loading, reset vector is fetched, etc.). Only enabled NVIC interrupts with sufficient priority will wakeup and interrupt the MCU. Table 14.
Page 77: Flash Memory In Low-Power Mode For Code Execution From Ram
RM0401 Power controller (PWR) Section 5.3.8: RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)). Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting the corresponding bit in RCC_AHBxLPENR and RCC_APBxLPENR registers. 4.3.4 Flash memory in low-power mode for code execution from RAM For applications where the code is executed from RAM, the Flash memory can be put in two possible low-power mode.
Page 78: Batch Acquisition Mode
Power controller (PWR) RM0401 Table 15. Sleep-now entry and exit (continued) Sleep-now mode Description If WFI or Return from ISR was used for entry: Interrupt: Refer to Table 39: Vector table If WFE was used for entry and SEVONPEND = 0 Mode exit Wakeup event: Refer to Section 9.2.3: Wakeup event management...
Page 79: Stop Mode
RM0401 Power controller (PWR) Table 17. BAM-now entry and exit Sleep-now mode Description Set the Flash memory in low-power mode: – FISSR/FMSSR and FPDS bits of the PWR_CR register WFI (Wait for Interrupt) or WFE (Wait for Event) while: Mode entry –...
Page 80: Table 19. Stop Operating Modes
Power controller (PWR) RM0401 When the code is executed from internal SRAM and the Flash memory is configured in low- power mode before entering Stop mode, the Flash memory stays in low-power mode after waking up from Stop. In this case, only the HSI RC clock startup time and the regulator wakeup time apply.
Page 81: Table 20. Stop Mode Entry And Exit
RM0401 Power controller (PWR) Section 20.3 Section 20: Independent watchdog (IWDG). • Real-time clock (RTC): this is configured by the RTCEN bit in the Section 5.3.14: RCC Backup domain control register (RCC_BDCR) • Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Section 5.3.15: RCC clock control &...
Page 82: Standby Mode
Power controller (PWR) RM0401 Table 20. Stop mode entry and exit (continued) Stop mode Description If WFI or Return from ISR was used for entry: Any EXTI lines configured in Interrupt mode (the corresponding EXTI Interrupt vector must be enabled in the NVIC). The interrupt source can be external interrupts or peripherals with wakeup capability.
Page 83: Programming The Rtc Alternate Functions To Wake Up The Device From The Stop And Standby Modes
RM0401 Power controller (PWR) Table 21. Standby mode entry and exit Standby mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: ® – SLEEPDEEP is set in Cortex -M4 with FPU System Control register – PDDS bit is set in Power Control register (PWR_CR) –...
Page 84 Power controller (PWR) RM0401 The system can also wake up from low-power modes without depending on an external interrupt (Auto-wakeup mode), by using the RTC alarm or the RTC wakeup events. The RTC provides a programmable time base for waking up from the Stop or Standby mode at regular intervals.
Page 85 RM0401 Power controller (PWR) • To wake up the device from the Standby mode with an RTC wakeup event, it is necessary to: Enable the RTC wakeup interrupt in the RTC_CR register Configure the RTC to generate the RTC wakeup event Safe RTC alternate function wakeup flag clearing sequence If the selected RTC alternate function is set before the PWR wakeup flag (WUTF) is cleared, it will not be detected on the next event as detection is made once on the rising edge.
Page 86: Power Control Registers
Power controller (PWR) RM0401 Power control registers 4.4.1 PWR power control register (PWR_CR) Address offset: 0x00 Reset value: 0x0000 8000 (reset by wakeup from Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FISSR FMSSR Res. Res. Res.
Page 87 RM0401 Power controller (PWR) Bit 12 Reserved, must be kept at reset value. Bit 11 MRLVDS: Main regulator Low Voltage in Deep Sleep 0: Main regulator in Voltage scale 3 when the device is in Stop mode. 1: Main regulator in Low Voltage and Flash memory in Deep Sleep mode when the device is in Stop mode.
Page 88: Pwr Power Control/Status Register (Pwr_Csr)
Power controller (PWR) RM0401 Bit 2 CWUF: Clear wakeup flag This bit is always read as 0. 0: No effect. 1: Clear the WUF Wakeup Flag after 2 System clock cycles. Bit 1 PDDS: Power-down deepsleep This bit is set and cleared by software. It works together with the LPDS bit. 0: Enter Stop mode when the CPU enters deepsleep.
Page 89 RM0401 Power controller (PWR) Bit 8 EWUP1: Enable WKUP1 pin (PA0) This bit is set and cleared by software. 0: WKUP1 pin is used for general purpose I/O. An event on the WKUP1 pin does not wakeup the device from Standby mode. 1: WKUP1 pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP1 pin wakes up the system from Standby mode).
Page 90: Pwr Register Map
Power controller (PWR) RM0401 PWR register map The following table summarizes the PWR registers. Table 22. PWR - register map and reset values Offset Register PWR_CR PLS[2:0] 0x000 Reset value PWR_CSR 0x004 Reset value Refer to Section 2.2 on page 41 for the register boundary addresses.
Page 91: Reset And Clock Control (Rcc)
RM0401 Reset and clock control (RCC) Reset and clock control (RCC) Reset There are three types of reset, defined as system Reset, power Reset and backup domain Reset. 5.1.1 System reset A system reset sets all registers to their reset values except the reset flags in the clock controller CSR register and the registers in the Backup domain.
Page 92: Power Reset
In this case, whenever a Stop mode entry sequence is successfully executed, the device is reset instead of entering the Stop mode. For further information on the user option bytes, refer to the STM32F410 Flash programming manual available from your ST sales office.
Page 93: Backup Domain Reset
RM0401 Reset and clock control (RCC) 5.1.3 Backup domain reset The backup domain reset sets all RTC registers and the RCC_BDCR register to their reset values. A backup domain reset is generated when one of the following events occurs: Software reset, triggered by setting the BDRST bit in the RCC Backup domain control register (RCC_BDCR).
Page 94: Figure 12. Clock Tree
Reset and clock control (RCC) RM0401 Each clock source can be switched on or off independently when it is not used, to optimize power consumption. Figure 12. Clock tree 1. For full details about the internal and external clock source characteristics, refer to the Electrical characteristics section in the device datasheet.
Page 95 RM0401 Reset and clock control (RCC) The clock controller provides a high degree of flexibility to the application in the choice of the external crystal or the oscillator to run the core and peripherals at the highest frequency and, guarantee the appropriate frequency for peripherals that need a specific clock like RNG, I2S and low-power timer.
Page 96: Hse Clock
Reset and clock control (RCC) RM0401 5.2.1 HSE clock The high speed external clock signal (HSE) can be generated from two possible clock sources: • HSE external crystal/ceramic resonator • HSE external user clock The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time.
Page 97: Hsi Clock
Section 5.2.7: Clock security system (CSS) on page 5.2.3 PLL configuration The STM32F410 devices feature one PLL. The PLL (PLL) is clocked by the HSE or HSI oscillator and features three different output clocks: • The first output is used to generate the high speed system clock (up to 100 MHz) •...
Page 98: Lsi Clock
Reset and clock control (RCC) RM0401 The LSE oscillator is switched on and off using the LSEON bit in RCC Backup domain control register (RCC_BDCR). The LSERDY flag in the RCC Backup domain control register (RCC_BDCR) indicates if the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware.
Page 99: Rtc/Awu Clock
RM0401 Reset and clock control (RCC) CSS interrupt in the NMI ISR by setting the CSSC bit in the Clock interrupt register (RCC_CIR). If the HSE oscillator is used directly or indirectly as the system clock (indirectly meaning that it is directly used as PLL input clock, and that PLL clock is the system clock) and a failure is detected, then the system clock switches to the HSI oscillator and the HSE oscillator is disabled.
Page 100: Clock-Out Capability
Reset and clock control (RCC) RM0401 5.2.10 Clock-out capability Two microcontroller clock output (MCO) pins are available: • MCO1 You can output four different clock sources onto the MCO1 pin (PA8) using the configurable prescaler (from 1 to 5): – HSI clock –...
Page 101: Figure 14. Frequency Measurement With Tim5 In Input Capture Mode
RM0401 Reset and clock control (RCC) The basic concept consists in providing a relative measurement (e.g. HSI/LSE ratio): the precision is therefore tightly linked to the ratio between the two clock sources. The greater the ratio, the better the measurement. It is also possible to measure the LSI frequency: this is useful for applications that do not have a crystal.
Page 102: Rcc Registers
Reset and clock control (RCC) RM0401 RCC registers Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in register descriptions. 5.3.1 RCC clock control register (RCC_CR) Address offset: 0x00 Reset value: 0x0000 XX81 where X is undefined. Access: no wait state, word, half-word and byte access Res.
Page 103 RM0401 Reset and clock control (RCC) Bit 16 HSEON: HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. 0: HSE oscillator OFF 1: HSE oscillator ON Bits 15:8 HSICAL[7:0]: Internal high-speed clock calibration...
Page 104: Rcc Pll Configuration Register (Rcc_Pllcfgr)
Reset and clock control (RCC) RM0401 5.3.2 RCC PLL configuration register (RCC_PLLCFGR) Address offset: 0x04 Reset value: 0x7F00 3010 Access: no wait state, word, half-word and byte access. This register is used to configure the PLL clock outputs according to the formulas: •...
Page 105 RM0401 Reset and clock control (RCC) Bits 17:16 PLLP: Main PLL (PLL) division factor for main system clock Set and cleared by software to control the frequency of the general PLL output clock. These bits can be written only if PLL is disabled. Caution: The software has to set these bits correctly not to exceed 100 MHz on this domain.
Page 106: Rcc Clock Configuration Register (Rcc_Cfgr)
Reset and clock control (RCC) RM0401 5.3.3 RCC clock configuration register (RCC_CFGR) Address offset: 0x08 Reset value: 0x0000 0000 Access: 0 wait state 2, word, half-word and byte access ≤ ≤ 1 or 2 wait states inserted only if the access occurs during a clock source switch. MCO2 MCO2 PRE[2:0] MCO1 PRE[2:0]...
Page 107 RM0401 Reset and clock control (RCC) Bits 22:21 MCO1: Microcontroller clock output 1 Set and cleared by software. Clock source selection may generate glitches on MCO1. It is highly recommended to configure these bits only after reset before enabling the external oscillators and PLL.
Page 108 Reset and clock control (RCC) RM0401 Bits 7:4 HPRE: AHB prescaler Set and cleared by software to control AHB clock division factor. Caution: The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after HPRE write. Caution: The AHB clock frequency must be at least 25 MHz when the Ethernet is used.
Page 109: Rcc Clock Interrupt Register (Rcc_Cir)
RM0401 Reset and clock control (RCC) 5.3.4 RCC clock interrupt register (RCC_CIR) Address offset: 0x0C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access CSSC Res. Res. RDYC RDYC RDYC RDYC RDYC Reserved Res. Res. Res. CSSF Res.
Page 110 Reset and clock control (RCC) RM0401 Bit 12 PLLRDYIE: Main PLL (PLL) ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL lock. 0: PLL lock interrupt disabled 1: PLL lock interrupt enabled Bit 11 HSERDYIE: HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization.
Page 111: Rcc Ahb1 Peripheral Reset Register (Rcc_Ahb1Rstr)
RM0401 Reset and clock control (RCC) Bit 1 LSERDYF: LSE ready interrupt flag Set by hardware when the External Low Speed clock becomes stable and LSERDYDIE is set. Cleared by software setting the LSERDYC bit. 0: No clock ready interrupt caused by the LSE oscillator 1: Clock ready interrupt caused by the LSE oscillator Bit 0 LSIRDYF: LSI ready interrupt flag Set by hardware when the internal low speed clock becomes stable and LSIRDYDIE is set.
Page 112: Rcc Apb1 Peripheral Reset Register For (Rcc_Apb1Rstr)
Reset and clock control (RCC) RM0401 Bit 7 GPIOHRST: IO port H reset Set and cleared by software. 0: does not reset IO port H 1: resets IO port H Bits 6:3 Reserved, must be kept at reset value. Bit 2 GPIOCRST: IO port C reset Set and cleared by software.
Page 113 RM0401 Reset and clock control (RCC) Bit 24 I2C4RST: I2C4 reset Set and cleared by software. 0: does not reset I2C4 1: resets I2C4 Bit 23 Reserved, must be kept at reset value. Bit 22 I2C2RST: I2C2 reset Set and cleared by software. 0: does not reset I2C2 1: resets I2C2 Bit 21 I2C1RST: I2C1 reset...
Page 114: Rcc Apb2 Peripheral Reset Register (Rcc_Apb2Rstr)
Reset and clock control (RCC) RM0401 5.3.7 RCC APB2 peripheral reset register (RCC_APB2RSTR) Address offset: 0x24 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. SPI5 TIM11 TIM9 Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 115 RM0401 Reset and clock control (RCC) Bits 7:6 Reserved, must be kept at reset value. Bit 5 USART6RST: USART6 reset Set and cleared by software. 0: does not reset USART6 1: resets USART6 Bit 4 USART1RST: USART1 reset Set and cleared by software. 0: does not reset USART1 1: resets USART1 Bits 3:1 Reserved, must be kept at reset value.
Page 116: Rcc Ahb1 Peripheral Clock Enable Register (Rcc_Ahb1Enr)
Reset and clock control (RCC) RM0401 5.3.8 RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) Address offset: 0x30 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. RNGEN Res. Res. Res. Res. Res. Res. Res. Res. DMA2EN DMA1EN Res.
Page 117: Rcc Apb1 Peripheral Clock Enable Register (Rcc_Apb1Enr)
RM0401 Reset and clock control (RCC) Bit 0 GPIOAEN: IO port A clock enable Set and cleared by software. 0: IO port A clock disabled 1: IO port A clock enabled 5.3.9 RCC APB1 peripheral clock enable register (RCC_APB1ENR) Address offset: 0x40 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access.
Page 118 Reset and clock control (RCC) RM0401 Bit 17 USART2EN: USART2 clock enable Set and cleared by software. 0: USART2 clock disabled 1: USART2 clock enabled Bits 16:15 Reserved, must be kept at reset value. Bit 14 SPI2EN: SPI2 clock enable Set and cleared by software.
Page 119: Rcc Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr)
RM0401 Reset and clock control (RCC) 5.3.10 RCC APB2 peripheral clock enable register (RCC_APB2ENR) Address offset: 0x44 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. TIM11 TIM9 Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 120 Reset and clock control (RCC) RM0401 Bit 8 ADC1EN: ADC1 clock enable Set and cleared by software. 0: ADC1 clock disabled 1: ADC1 clock disabled Bits 7:6 Reserved, must be kept at reset value. Bit 5 USART6EN: USART6 clock enable Set and cleared by software.
Page 121: Rcc Ahb1 Peripheral Clock Enable In Low Power Mode Register (Rcc_Ahb1Lpenr)
RM0401 Reset and clock control (RCC) 5.3.11 RCC AHB1 peripheral clock enable in low power mode register (RCC_AHB1LPENR) Address offset: 0x50 Reset value: 0x0061 900F Access: no wait state, word, half-word and byte access. DMA2 DMA1 SRAM1 Res. Res. Res. Res.
Page 122 Reset and clock control (RCC) RM0401 Bit 7 GPIOHLPEN: IO port H clock enable during sleep mode Set and reset by software. 0: IO port H clock disabled during sleep mode 1: IO port H clock enabled during sleep mode Bits 6:3 Reserved, must be kept at reset value.
Page 123: Rcc Apb1 Peripheral Clock Enable In Low Power Mode Register (Rcc_Apb1Lpenr)
RM0401 Reset and clock control (RCC) 5.3.12 RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR) Address offset: 0x60 Reset value: 0x10E2 C80F Access: no wait state, word, half-word and byte access. I2C4 I2C2 I2C1 USART2 Res. Res. Res.
Page 124 Reset and clock control (RCC) RM0401 Bit 14 SPI2LPEN: SPI2 clock enable during Sleep mode Set and cleared by software. 0: SPI2 clock disabled during Sleep mode 1: SPI2 clock enabled during Sleep mode Bits 13:12 Reserved, must be kept at reset value. Bit 11 WWDGLPEN: Window watchdog clock enable during Sleep mode Set and cleared by software.
Page 125: Rcc Apb2 Peripheral Clock Enabled In Low Power Mode Register (Rcc_Apb2Lpenr)
RM0401 Reset and clock control (RCC) 5.3.13 RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR) Address offset: 0x64 Reset value: 0x0007 7930 Access: no wait state, word, half-word and byte access. SPI5 TIM11 TIM9 Res. Res. Res. Res.
Page 126 Reset and clock control (RCC) RM0401 Bit 8 ADC1LPEN: ADC1 clock enable during Sleep mode Set and cleared by software. 0: ADC1 clock disabled during Sleep mode 1: ADC1 clock disabled during Sleep mode Bits 7:6 Reserved, must be kept at reset value. Bit 5 USART6LPEN: USART6 clock enable during Sleep mode Set and cleared by software.
Page 127: Rcc Backup Domain Control Register (Rcc_Bdcr)
RM0401 Reset and clock control (RCC) 5.3.14 RCC Backup domain control register (RCC_BDCR) Address offset: 0x70 Reset value: 0x0000 0000, reset by Backup domain reset. Access: 0 wait state 3, word, half-word and byte access ≤ ≤ Wait states are inserted in case of successive accesses to this register. The LSEON, LSEBYP, RTCSEL and RTCEN bits in the Section 5.3.14: RCC Backup domain control register (RCC_BDCR)
Page 128: Rcc Clock Control & Status Register (Rcc_Csr)
Reset and clock control (RCC) RM0401 Bit 2 LSEBYP: External low-speed oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the LSE clock is disabled. 0: LSE oscillator not bypassed 1: LSE oscillator bypassed Bit 1 LSERDY: External low-speed oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable.
Page 129 RM0401 Reset and clock control (RCC) Bit 28 SFTRSTF: Software reset flag Set by hardware when a software reset occurs. Cleared by writing to the RMVF bit. 0: No software reset occurred 1: Software reset occurred Bit 27 PORRSTF: POR/PDR reset flag Set by hardware when a POR/PDR reset occurs.
Page 130: Rcc Spread Spectrum Clock Generation Register (Rcc_Sscgr)
Reset and clock control (RCC) RM0401 5.3.16 RCC spread spectrum clock generation register (RCC_SSCGR) Address offset: 0x80 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. The spread spectrum clock generation is available only for the main PLL. The RCC_SSCGR register must be written either before the main PLL is enabled or after the main PLL disabled.
Page 131: Rcc Dedicated Clocks Configuration Register (Rcc_Dckcfgr)
RM0401 Reset and clock control (RCC) 5.3.17 RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR) Address offset: 0x8C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. Res. Res. Res. Res. Res. I2SSCR TIMPRE Res. Res. Res. Res. Res.
Page 132: Rcc Dedicated Clocks Configuration Register 2 (Rcc_Dckcfgr2)
Reset and clock control (RCC) RM0401 5.3.18 RCC dedicated Clocks Configuration Register 2 (RCC_DCKCFGR2) Address offset: 0x94 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. LPTIM1SEL Res. Res. Res. Res. Res. Res. I2C4SEL Res. Res. Res.
Page 133: Rcc Register Map
RM0401 Reset and clock control (RCC) 5.3.19 RCC register map Table 23 gives the register map and reset values Table 23. RCC register map and reset values Addr. Register offset name 0x00 RCC_CR RCC_ 0x04 PLLCFGR 0x08 RCC_CFGR 0x0C RCC_CIR RCC_ 0x10 AHB1RSTR...
Page 134 Reset and clock control (RCC) RM0401 Table 23. RCC register map and reset values (continued) Addr. Register offset name RCC_AHB1L 0x50 PENR 0x54 to Reserved 0x5C RCC_APB1L 0x60 PENR RCC_APB2L 0x64 PENR 0x68 to Reserved 0x6C 0x70 RCC_BDCR 0x74 RCC_CSR 0x78 to Reserved 0x7C...
Page 135: General-Purpose I/Os (Gpio)
RM0401 General-purpose I/Os (GPIO) General-purpose I/Os (GPIO) GPIO introduction Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection register (GPIOx_AFRH and GPIOx_AFRL).
Page 136: Table 24. Port Bit Configuration Table
General-purpose I/Os (GPIO) RM0401 Figure 16 shows the basic structure of a 5 V tolerant I/O port bit. Table 27 gives the possible port bit configurations. Figure 16. Basic structure of a five-volt tolerant I/O port bit 1. V is a potential specific to five-volt tolerant I/Os and different from V DD_FT Table 24.
Page 137: General-Purpose I/O (Gpio)
RM0401 General-purpose I/Os (GPIO) Table 24. Port bit configuration table (continued) MODER(i) OSPEEDR(i) PUPDR(i) OTYPER(i) I/O configuration [1:0] [B:A] [1:0] PP + PU PP + PD Reserved SPEED [B:A] OD + PU OD + PD Reserved Input Floating Input Input Reserved (input floating) Input/output Analog...
Page 138: I/O Pin Multiplexer And Mapping
General-purpose I/Os (GPIO) RM0401 6.3.2 I/O pin multiplexer and mapping The microcontroller I/O pins are connected to onboard peripherals/modules through a multiplexer that allows only one peripherals alternate function (AF) connected to an I/O pin at a time. In this way, there can be no conflict between peripherals sharing the same I/O pin. Each I/O pin has a multiplexer with sixteen alternate function inputs (AF0 to AF15) that can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to 15) registers:...
Page 139: Table 25. Flexible Swj-Dp Pin Assignment
RM0401 General-purpose I/Os (GPIO) Table 25. Flexible SWJ-DP pin assignment SWJ I/O pin assigned PA13 / PA14 / Available debug ports PA15 / PB3 / PB4/ JTMS/ JTCK/ JTDI JTDO NJTRST SWDIO SWCLK Full SWJ (JTAG-DP + SW-DP) - Reset state Full SWJ (JTAG-DP + SW-DP) but without NJTRST JTAG-DP Disabled and SW-DP Enabled...
Page 140: I/O Port Control Registers
General-purpose I/Os (GPIO) RM0401 Figure 17. Selecting an alternate function 1. Configured in FS. 6.3.3 I/O port control registers Each of the GPIOs has four 32-bit memory-mapped control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The GPIOx_MODER register is used to select the I/O direction (input, output, AF, analog). The GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (push-pull or open-drain) and speed (the I/O speed pins are directly connected to the corresponding GPIOx_OSPEEDR register bits whatever the I/O direction).
Page 141: I/O Port Data Registers
RM0401 General-purpose I/Os (GPIO) 6.3.4 I/O port data registers Each GPIO has two 16-bit memory-mapped data registers: input and output data registers (GPIOx_IDR and GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write accessible. The data input through the I/O are stored into the input data register (GPIOx_IDR), a read-only register.
Page 142: I/O Alternate Function Input/Output
General-purpose I/Os (GPIO) RM0401 6.3.7 I/O alternate function input/output Two registers are provided to select one out of the sixteen alternate function inputs/outputs available for each I/O. With these registers, you can connect an alternate function to some other pin as required by your application. This means that a number of possible peripheral functions are multiplexed on each GPIO using the GPIOx_AFRL and GPIOx_AFRH alternate function registers.
Page 143: Output Configuration
RM0401 General-purpose I/Os (GPIO) 6.3.10 Output configuration When the I/O port is programmed as output: • The output buffer is enabled: – Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register leaves the port in Hi-Z (the P-MOS is never activated) –...
Page 144: Analog Configuration
General-purpose I/Os (GPIO) RM0401 Figure 20. Alternate function configuration 6.3.12 Analog configuration When the I/O port is programmed as analog configuration: • The output buffer is disabled • The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin.
Page 145: Using The Osc32_In/Osc32_Out Pins As Gpio Pc14/Pc15
RM0401 General-purpose I/Os (GPIO) 6.3.13 Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general-purpose PC14 and PC15 I/Os, respectively, when the LSE oscillator is off. The PC14 and PC15 I/Os are only configured as LSE oscillator pins OSC32_IN and OSC32_OUT when the LSE oscillator is ON.
Page 146 General-purpose I/Os (GPIO) RM0401 Table 26. RTC additional functions (continued) TSINSEL Time TAMP1INSEL ALARMOUTTYPE RTC_ALARM RTC_CALIB Tamper TIMESTAMP configuration stamp TAMPER1 RTC_ALARM enabled enabled enabled and function enabled pin selection configuration selection Calibration Don’t Don’t Don’t care Don’t care Don’t care out output PP care care...
Page 147: Gpio Registers
RM0401 General-purpose I/Os (GPIO) GPIO registers This section gives a detailed description of the GPIO registers. For a summary of register bits, register address offsets and reset values, refer to Table The GPIO registers can be accessed by byte (8 bits), half-words (16 bits) or words (32 bits). 6.4.1 GPIO port mode register (GPIOx_MODER) (x = A..C and H) Address offset: 0x00...
Page 148: Gpio Port Output Speed Register (Gpiox_Ospeedr)
General-purpose I/Os (GPIO) RM0401 6.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..C and H) Address offset: 0x08 Reset values: • 0x0C00 0000 for port A • 0x0000 00C0 for port B • 0x0000 0000 for other ports OSPEEDR15 OSPEEDR14 OSPEEDR13 OSPEEDR12...
Page 149: Gpio Port Input Data Register (Gpiox_Idr) (X = A..c And H
RM0401 General-purpose I/Os (GPIO) 6.4.5 GPIO port input data register (GPIOx_IDR) (x = A..C and H) Address offset: 0x10 Reset value: 0x0000 XXXX (where X means undefined) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 150: Gpio Port Configuration Lock Register (Gpiox_Lckr)
General-purpose I/Os (GPIO) RM0401 Bits 31:16 BRy: Port x reset bit y (y = 0..15) These bits are write-only and can be accessed in word, half-word or byte mode. A read to these bits returns the value 0x0000. 0: No action on the corresponding ODRx bit 1: Resets the corresponding ODRx bit Note: If both BSx and BRx are set, BSx has priority.
Page 151: Gpio Alternate Function Low Register (Gpiox_Afrl) (X = A..c And H)
RM0401 General-purpose I/Os (GPIO) Bits 31:17 Reserved, must be kept at reset value. Bit 16 LCKK[16]: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. 0: Port configuration lock key not active 1: Port configuration lock key active.
Page 152: (X = A
General-purpose I/Os (GPIO) RM0401 6.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A..C and H) Address offset: 0x24 Reset value: 0x0000 0000 AFRH15[3:0] AFRH14[3:0] AFRH13[3:0] AFRH12[3:0] AFRH11[3:0] AFRH10[3:0] AFRH9[3:0] AFRH8[3:0] Bits 31:0 AFRHy: Alternate function selection for port x bit y (y = 8..15) These bits are written by software to configure alternate function I/Os AFRHy selection: 0000: AF0...
Page 153 RM0401 General-purpose I/Os (GPIO) Table 27. GPIO register map and reset values (continued) Offset Register GPIOx_ OTYPER (where x = A..C 0x04 and H) Reset value GPIOx_ OSPEEDER (where x = A..C 0x08 and H) Reset value GPIOA_ OSPEEDER 0x08 Reset value GPIOB_ OSPEEDER...
Page 154 General-purpose I/Os (GPIO) RM0401 Table 27. GPIO register map and reset values (continued) Offset Register GPIOx_LCKR (where x =A..C 0x1C and H) Reset value GPIOx_AFRL (where x =A..C AFRL7[3:0] AFRL6[3:0] AFRL5[3:0] AFRL4[3:0] AFRL3[3:0] AFRL2[3:0] AFRL1[3:0] AFRL0[3:0] 0x20 and H) Reset value GPIOx_AFRH (where x =A..C AFRH15[3:0] AFRH14[3:0] AFRH13[3:0] AFRH12[3:0] AFRH11[3:0] AFRH10[3:0]...
Page 155: System Configuration Controller (Syscfg)
RM0401 System configuration controller (SYSCFG) System configuration controller (SYSCFG) The system configuration controller is mainly used to remap the memory accessible in the code area and manage the external interrupt line connection to the GPIOs. I/O compensation cell By default the I/O compensation cell is not used. However when the I/O output buffer speed is configured in 50 MHz or 100 MHz mode, it is recommended to use the compensation cell for slew rate control on I/O t commutation to reduce the I/O noise on power...
Page 156: Syscfg Peripheral Mode Configuration Register (Syscfg_Pmc)
System configuration controller (SYSCFG) RM0401 Bits 31:2 Reserved, must be kept at reset value. Bits 1:0 MEM_MODE: Memory mapping selection Set and cleared by software. This bit controls the memory internal mapping at address 0x0000 0000. After reset these bits take the value selected by the Boot pins.
Page 157: Syscfg External Interrupt Configuration Register 1
RM0401 System configuration controller (SYSCFG) 7.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0] Bits 31:16 Reserved, must be kept at reset value.
Page 158: Syscfg External Interrupt Configuration Register 3
System configuration controller (SYSCFG) RM0401 7.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) Address offset: 0x10 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0] Bits 31:16 Reserved, must be kept at reset value.
Page 159: Syscfg Configuration Register 2 (Syscfg_Cfgr2)
RM0401 System configuration controller (SYSCFG) 7.2.7 SYSCFG configuration register 2 (SYSCFG_CFGR2) Address offset: 0x1C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 160: Compensation Cell Control Register (Syscfg_Cfgr)
System configuration controller (SYSCFG) RM0401 Bits 31:9 Reserved, must be kept at reset value. Bit 8 READY: Compensation cell ready flag 0: I/O compensation cell not ready 1: O compensation cell ready Bits 7:2 Reserved, must be kept at reset value. Bit 0 CMP_PD: Compensation cell power-down 0: I/O compensation cell power-down mode 1: I/O compensation cell enabled...
Page 161: Syscfg Register Map
RM0401 System configuration controller (SYSCFG) 7.2.10 SYSCFG register map The following table gives the SYSCFG register map and the reset values. Table 28. SYSCFG register map and reset values Offset Register SYSCFG_ MEMRMP 0x00 Reset value SYSCFG_PMC 0x04 Reset value SYSCFG_EXTICR1 EXTI3[3:0] EXTI2[3:0]...
Page 162: Direct Memory Access Controller (Dma)
Direct memory access controller (DMA) RM0401 Direct memory access controller (DMA) DMA introduction Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory and between memory and memory. Data can be quickly moved by DMA without any CPU action.
Page 163 RM0401 Direct memory access controller (DMA) – DMA flow controller: the number of data items to be transferred is software- programmable from 1 to 65535 – Peripheral flow controller: the number of data items to be transferred is unknown and controlled by the source or the destination peripheral that signals the end of the transfer by hardware •...
Page 164: Dma Functional Description
Direct memory access controller (DMA) RM0401 DMA functional description 8.3.1 DMA block diagram Figure 22 shows the block diagram of a DMA. Figure 22. DMA block diagram 8.3.2 DMA overview The DMA controller performs direct memory transfer: as an AHB master, it can take the control of the AHB bus matrix to initiate AHB transactions.
Page 165: Dma Transactions
RM0401 Direct memory access controller (DMA) Figure 23. System implementation of the two DMA controllers 1. The DMA1 controller AHB peripheral port is not connected to the bus matrix like in the case of the DMA2 controller, thus only DMA2 streams are able to perform memory-to-memory transfers. 8.3.3 DMA transactions A DMA transaction consists of a sequence of a given number of data transfers.
Page 166: Channel Selection
Direct memory access controller (DMA) RM0401 controller accesses the peripheral, an Acknowledge signal is sent to the peripheral by the DMA controller. The peripheral releases its request as soon as it gets the Acknowledge signal from the DMA controller. Once the request has been deasserted by the peripheral, the DMA controller releases the Acknowledge signal.
Page 167: Arbiter
RM0401 Direct memory access controller (DMA) Table 30. DMA2 request mapping Peripheral Stream 0 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7 requests TIM1_CH1 Channel 0 ADC1 ADC1 TIM1_CH2 TIM1_CH3 Channel 1 Channel 2 SPI1_TX SPI5_RX SPI5_TX...
Page 168: Source, Destination And Transfer Modes
Direct memory access controller (DMA) RM0401 8.3.7 Source, destination and transfer modes Both source and destination transfers can address peripherals and memories in the entire 4 Gbytes area, at addresses comprised between 0x0000 0000 and 0xFFFF FFFF. The direction is configured using the DIR[1:0] bits in the DMA_SxCR register and offers three possibilities: memory-to-peripheral, peripheral-to-memory or memory-to-memory transfers.
Page 169: Figure 25. Peripheral-To-Memory Mode
RM0401 Direct memory access controller (DMA) Figure 25. Peripheral-to-memory mode 1. For double-buffer mode. Memory-to-peripheral mode Figure 26 describes this mode. When this mode is enabled (by setting the EN bit in the DMA_SxCR register), the stream immediately initiates transfers from the source to entirely fill the FIFO. Each time a peripheral request occurs, the contents of the FIFO are drained and stored into the destination.
Page 170: Figure 26. Memory-To-Peripheral Mode
Direct memory access controller (DMA) RM0401 Figure 26. Memory-to-peripheral mode 1. For double-buffer mode. Memory-to-memory mode The DMA channels can also work without being triggered by a request from a peripheral. This is the memory-to-memory mode, described in Figure When the stream is enabled by setting the Enable bit (EN) in the DMA_SxCR register, the stream immediately starts to fill the FIFO up to the threshold level.
Page 171: Pointer Incrementation
RM0401 Direct memory access controller (DMA) Figure 27. Memory-to-memory mode 1. For double-buffer mode. 8.3.8 Pointer incrementation Peripheral and memory pointers can optionally be automatically post-incremented or kept constant after each transfer depending on the PINC and MINC bits in the DMA_SxCR register.
Page 172: Circular Mode
Direct memory access controller (DMA) RM0401 8.3.9 Circular mode The circular mode is available to handle circular buffers and continuous data flows (e.g. ADC scan mode). This feature can be enabled using the CIRC bit in the DMA_SxCR register. When the circular mode is activated, the number of data items to be transferred is automatically reloaded with the initial value programmed during the stream configuration phase, and the DMA requests continue to be served.
Page 173: Programmable Data Width, Packing/Unpacking, Endianness
RM0401 Direct memory access controller (DMA) memory 0 to 1 (or from 1 to 0) depending on the value of CT in the DMA_SxCR register in accordance with one of the two above conditions. For all the other modes (except the double-buffer mode), the memory address registers are write-protected as soon as the stream is enabled.
Page 174: Table 33. Packing/Unpacking And Endian Behavior (Bit Pinc = Minc = 1)
Direct memory access controller (DMA) RM0401 Table 33. Packing/unpacking and endian behavior (bit PINC = MINC = 1) Number Peripheral port address / byte lane of data Memory Memory port Peripheral memory peripheral items to transfer address / byte transfer port port PINCOS = 1...
Page 175: Single And Burst Transfers
RM0401 Direct memory access controller (DMA) 8.3.12 Single and burst transfers The DMA controller can generate single transfers or incremental burst transfers of 4, 8 or 16 beats. The size of the burst is configured by software independently for the two AHB ports by using the MBURST[1:0] and PBURST[1:0] bits in the DMA_SxCR register.
Page 176: Table 35. Fifo Threshold Configurations
Direct memory access controller (DMA) RM0401 Figure 28. FIFO structure FIFO threshold and burst configuration Caution is required when choosing the FIFO threshold (bits FTH[1:0] of the DMA_SxFCR register) and the size of the memory burst (MBURST[1:0] of the DMA_SxCR register): The content pointed by the FIFO threshold must exactly match an integer number of memory burst transfers.
Page 177 RM0401 Direct memory access controller (DMA) Table 35. FIFO threshold configurations (continued) MSIZE FIFO level MBURST = INCR4 MBURST = INCR8 MBURST = INCR16 Forbidden 1 burst of 4 beats Forbidden Half-word Forbidden Full 2 bursts of 4 beats 1 burst of 8 beats Forbidden Forbidden Word...
Page 178: Dma Transfer Completion
Direct memory access controller (DMA) RM0401 value. The software may read the DMA_SxNDTR register to determine the memory area that contains the good data (start address and last address). If the number of remaining data items in the FIFO is lower than a burst size (if the MBURST bits in DMA_SxCR register are set to configure the stream to manage burst on the AHB memory port), single transactions are generated to complete the FIFO flush.
Page 179: Dma Transfer Suspension
RM0401 Direct memory access controller (DMA) 8.3.15 DMA transfer suspension At any time, a DMA transfer can be suspended to be restarted later on or to be definitively disabled before the end of the DMA transfer. There are two cases: •...
Page 180: Summary Of The Possible Dma Configurations
Direct memory access controller (DMA) RM0401 triggered in the case of a peripheral-to-memory DMA transfer. The TCIFx flag of the corresponding stream is set in the status register to indicate the DMA completion. To know the number of data items transferred during the DMA transfer, read the DMA_SxNDTR register and apply the following formula: –...
Page 181: Stream Configuration Procedure
RM0401 Direct memory access controller (DMA) 8.3.18 Stream configuration procedure The following sequence must be followed to configure a DMA stream x (where x is the stream number): If the stream is enabled, disable it by resetting the EN bit in the DMA_SxCR register, then read this bit in order to confirm that there is no ongoing stream operation.
Page 182: Error Management
Direct memory access controller (DMA) RM0401 8.3.19 Error management The DMA controller can detect the following errors: • Transfer error: the transfer error interrupt flag (TEIFx) is set when: – a bus error occurs during a DMA read or a write access –...
Page 183: Dma Interrupts
RM0401 Direct memory access controller (DMA) DMA interrupts For each DMA stream, an interrupt can be produced on the following events: • Half-transfer reached • Transfer complete • Transfer error • FIFO error (overrun, underrun or FIFO level error) • Direct mode error Separate interrupt enable control bits are available for flexibility as shown in Table...
Page 184: Dma Registers
Direct memory access controller (DMA) RM0401 DMA registers The DMA registers have to be accessed by words (32 bits). 8.5.1 DMA low interrupt status register (DMA_LISR) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. TCIF3 HTIF3 TEIF3 DMEIF3 Res.
Page 185: Dma High Interrupt Status Register (Dma_Hisr)
RM0401 Direct memory access controller (DMA) 8.5.2 DMA high interrupt status register (DMA_HISR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. TCIF7 HTIF7 TEIF7 DMEIF7 Res. FEIF7 TCIF6 HTIF6 TEIF6 DMEIF6 Res. FEIF6 Res. Res. Res. Res. TCIF5 HTIF5 TEIF5...
Page 186: Dma Low Interrupt Flag Clear Register (Dma_Lifcr)
Direct memory access controller (DMA) RM0401 8.5.3 DMA low interrupt flag clear register (DMA_LIFCR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. CTCIF3 CHTIF3 CTEIF3 CDMEIF3 Res. CFEIF3 CTCIF2 CHTIF2 CTEIF2 CDMEIF2 Res. CFEIF2 Res. Res. Res. Res.
Page 187: Dma Stream X Configuration Register (Dma_Sxcr)
RM0401 Direct memory access controller (DMA) Bits 24, 18, 8, 2 CDMEIFx: stream x clear direct mode error interrupt flag (x = 7..4) Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_HISR register. Bits 23, 17, 7, 1 Reserved, must be kept at reset value. Bits 22, 16, 6, 0 CFEIFx: stream x clear FIFO error interrupt flag (x = 7..4) Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_HISR register.
Page 188 Direct memory access controller (DMA) RM0401 Bit 19 CT: current target (only in double-buffer mode) This bit is set and cleared by hardware. It can also be written by software. 0: current target memory is Memory 0 (addressed by the DMA_SxM0AR pointer) 1: current target memory is Memory 1 (addressed by the DMA_SxM1AR pointer) This bit can be written only if EN is ‘0’...
Page 189 RM0401 Direct memory access controller (DMA) Bit 9 PINC: peripheral increment mode This bit is set and cleared by software. 0: peripheral address pointer is fixed 1: peripheral address pointer is incremented after each data transfer (increment is done according to PSIZE) This bit is protected and can be written only if EN is ‘0’.
Page 190: Dma Stream X Number Of Data Register (Dma_Sxndtr)
Direct memory access controller (DMA) RM0401 Bit 0 EN: stream enable / flag stream ready when read low This bit is set and cleared by software. 0: stream disabled 1: stream enabled This bit may be cleared by hardware: – on a DMA end of transfer (stream ready to be configured) –...
Page 191: Dma Stream X Peripheral Address Register (Dma_Sxpar)
RM0401 Direct memory access controller (DMA) 8.5.7 DMA stream x peripheral address register (DMA_SxPAR) Address offset: 0x18 + 0x18 * x, (x = 0 to 7) Reset value: 0x0000 0000 PAR[31:16] PAR[15:0] Bits 31:0 PAR[31:0]: peripheral address Base address of the peripheral data register from/to which the data is read/written. These bits are write-protected and can be written only when bit EN = '0' in the DMA_SxCR register.
Page 192: Dma Stream X Fifo Control Register (Dma_Sxfcr)
Direct memory access controller (DMA) RM0401 Bits 31:0 M1A[31:0]: memory 1 address (used in case of double-buffer mode) Base address of memory area 1 from/to which the data is read/written. This register is used only for the double-buffer mode. These bits are write-protected. They can be written only if: –...
Page 193 RM0401 Direct memory access controller (DMA) Bits 1:0 FTH[1:0]: FIFO threshold selection These bits are set and cleared by software. 00: 1/4 full FIFO 01: 1/2 full FIFO 10: 3/4 full FIFO 11: full FIFO These bits are not used in the direct mode when the DMIS value is zero. These bits are protected and can be written only if EN is ‘0’.
Page 194: Dma Register Map
Direct memory access controller (DMA) RM0401 8.5.11 DMA register map Table 38 summarizes the DMA registers. Table 38. DMA register map and reset values Offset Register name DMA_LISR 0x0000 Reset value DMA_HISR 0x0004 Reset value DMA_LIFCR 0x0008 Reset value DMA_HIFCR 0x000C Reset value DMA_S0CR...
Page 195 RM0401 Direct memory access controller (DMA) Table 38. DMA register map and reset values (continued) Offset Register name DMA_S1M0AR M0A[31:0] 0x0034 Reset value DMA_S1M1AR M1A[31:0] 0x0038 Reset value DMA_S1FCR FS[2:0] 0x003C Reset value DMA_S2CR 0x0040 Reset value DMA_S2NDTR NDT[15:0] 0x0044 Reset value DMA_S2PAR PA[31:0]...
Page 196 Direct memory access controller (DMA) RM0401 Table 38. DMA register map and reset values (continued) Offset Register name DMA_S3FCR FS[2:0] 0x006C Reset value DMA_S4CR 0x0070 Reset value DMA_S4NDTR NDT[15:0] 0x0074 Reset value DMA_S4PAR PA[31:0] 0x0078 Reset value DMA_S4M0AR M0A[31:0] 0x007C Reset value DMA_S4M1AR M1A[31:0]...
Page 197 RM0401 Direct memory access controller (DMA) Table 38. DMA register map and reset values (continued) Offset Register name DMA_S6CR 0x00A0 Reset value DMA_S6NDTR NDT[15:0] 0x00A4 Reset value DMA_S6PAR PA[31:0] 0x00A8 Reset value DMA_S6M0AR M0A[31:0] 0x00AC Reset value DMA_S6M1AR M1A[31:0] 0x00B0 Reset value DMA_S6FCR FS[2:0]...
Page 198: Interrupts And Events
Interrupts and events RM0401 Interrupts and events Nested vectored interrupt controller (NVIC) 9.1.1 NVIC features The nested vector interrupt controller NVIC includes the following features: ® • 52 maskable interrupt channels (not including the 16 interrupt lines of Cortex -M4 with FPU) •...
Page 199 RM0401 Interrupts and events Table 39. Vector table (continued) Type of Acronym Description Address priority Non maskable interrupt, Clock Security fixed 0x0000 0008 System fixed HardFault All class of fault 0x0000 000C settable MemManage Memory management 0x0000 0010 settable BusFault Prefetch fault, memory access fault 0x0000 0014 settable...
Page 200 Interrupts and events RM0401 Table 39. Vector table (continued) Type of Acronym Description Address priority settable DMA1_Stream4 DMA1 Stream4 global interrupt 0x0000 007C settable DMA1_Stream5 DMA1 Stream5 global interrupt 0x0000 0080 settable DMA1_Stream6 DMA1 Stream6 global interrupt 0x0000 0084 settable ADC1 global interrupts 0x0000 0088 19 to...
Page 201 RM0401 Interrupts and events Table 39. Vector table (continued) Type of Acronym Description Address priority 51 to 0x0000 010C to Reserved 0x0000 0114 TIM6 global interrupt, settable TIM6_DAC 0x0000 0118 DAC1 underrun error interrupt Reserved 0x0000 011C settable DMA2_Stream0 DMA2 Stream0 global interrupt 0x0000 0120 settable DMA2_Stream1...
Page 202: Exti Main Features
Interrupts and events RM0401 Table 39. Vector table (continued) Type of Acronym Description Address priority settable I2C4_ER I2C4 error interrupt 0x0000 01C4 LPTIM1 global interrupt or EXTI Line 23 settable LPTIM1/EXTI23 0x0000 01C8 interrupt 9.2.1 EXTI main features The main features of the EXTI controller are the following: •...
Page 203: Exti Block Diagram
RM0401 Interrupts and events 9.2.2 EXTI block diagram Figure 29 shows the block diagram. Figure 29. External interrupt/event controller block diagram 9.2.3 Wakeup event management The STM32F4xx are able to handle external or internal events in order to wake up the core (WFE).
Page 204 Interrupts and events RM0401 generated. The pending bit corresponding to the interrupt line is also set. This request is reset by writing a ‘1’ in the pending register. To generate the event, the event line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the event request by writing a ‘1’...
Page 205: External Interrupt/Event Line Mapping
RM0401 Interrupts and events 9.2.5 External interrupt/event line mapping Up to 50 GPIOs are connected to the 16 external interrupt/event lines in the following manner: Figure 30. External interrupt/event GPIO mapping The five other EXTI lines are connected as follows: •...
Page 206: Exti Registers
Interrupts and events RM0401 registers EXTI Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in register descriptions. 9.3.1 Interrupt mask register (EXTI_IMR) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. Res.
Page 207: Rising Trigger Selection Register (Exti_Rtsr)
RM0401 Interrupts and events 9.3.3 Rising trigger selection register (EXTI_RTSR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. TR22 TR21 Res. Res. TR18 TR17 TR16 TR15 TR14 TR13 TR12 TR11 TR10 Bits 31:23 Reserved, must be kept at reset value. Bits 22:21 TRx: Rising trigger event configuration bit of line x 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line...
Page 208: Software Interrupt Event Register (Exti_Swier)
Interrupts and events RM0401 Bits 22:21 TRx: Falling trigger event configuration bit of line x 0: Falling trigger disabled (for Event and Interrupt) for input line 1: Falling trigger enabled (for Event and Interrupt) for input line. Bits 20:19 Reserved, must be kept at reset value. Bits 18:0 TRx: Falling trigger event configuration bit of line x 0: Falling trigger disabled (for Event and Interrupt) for input line 1: Falling trigger enabled (for Event and Interrupt) for input line.
Page 209 RM0401 Interrupts and events PR15 PR14 PR13 PR12 PR11 PR10 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits 31:23 Reserved, must be kept at reset value. Bits 22:21 PRx: Pending bit 0: No trigger request occurred 1: selected trigger request occurred This bit is set when the selected edge event arrives on the external interrupt line.
Page 210: Exti Register Map
Interrupts and events RM0401 9.3.7 EXTI register map Table 40 gives the EXTI register map and the reset values. Table 40. External interrupt/event controller register map and reset values Offset Register EXTI_IMR MR[18:0] [22:21] 0x00 Reset value EXTI_EMR MR[18:0] [22:21] 0x04 Reset value EXTI_RTSR...
Page 211: Crc Calculation Unit
RM0401 CRC calculation unit CRC calculation unit 10.1 CRC introduction The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity.
Page 212: Crc Registers
CRC calculation unit RM0401 Each write operation into the data register creates a combination of the previous CRC value and the new one (CRC computation is done on the whole 32-bit data word, and not byte per byte). The write operation is stalled until the end of the CRC computation, thus allowing back-to- back write accesses or consecutive write and read accesses.
Page 213: Independent Data Register (Crc_Idr)
RM0401 CRC calculation unit 10.4.2 Independent data register (CRC_IDR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. IDR[7:0] Bits 31:8 Reserved, must be kept at reset value.
Page 214: Crc Register Map
CRC calculation unit RM0401 10.4.4 CRC register map Table 41. CRC calculation unit register map and reset values Offset Register CRC_DR Data register 0x00 Reset value 0xFFFF FFFF CRC_IDR Independent data register 0x04 Reset value 0x0000 CRC_CR 0x08 Reset value Refer to Section 2.2 on page 41 for the register boundary addresses.
Page 215: Analog-To-Digital Converter (Adc)
RM0401 Analog-to-digital converter (ADC) Analog-to-digital converter (ADC) 11.1 ADC introduction The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 19 multiplexed channels allowing it to measure signals from 16 external sources, two internal sources, and the V channel.
Page 216: Figure 32. Single Adc Block Diagram
Analog-to-digital converter (ADC) RM0401 Figure 32. Single ADC block diagram 216/771 RM0401 Rev 3...
Page 217: Adc On-Off Control
RM0401 Analog-to-digital converter (ADC) Table 42. ADC pins Name Signal type Remarks Input, analog reference The higher/positive reference voltage for the ADC, REF+ positive 1.8 V ≤ V ≤ V REF+ Analog power supply equal to V Input, analog supply 2.4 V ≤V ≤V (3.6 V) for full speed...
Page 218: Single Conversion Mode
Analog-to-digital converter (ADC) RM0401 The total number of conversions in the injected group must be written in the L[1:0] bits in the ADC_JSQR register. If the ADC_SQRx or ADC_JSQR registers are modified during a conversion, the current conversion is reset and a new start pulse is sent to the ADC to convert the newly chosen group.
Page 219: Timing Diagram
RM0401 Analog-to-digital converter (ADC) mode (using JAUTO bit), refer to Auto-injection section) 11.3.6 Timing diagram As shown in Figure 33, the ADC needs a stabilization time of t before it starts STAB converting accurately. After the start of the ADC conversion and after 15 clock cycles, the EOC flag is set and the 16-bit ADC data register contains the result of the conversion.
Page 220: Scan Mode
Analog-to-digital converter (ADC) RM0401 Table 43. Analog watchdog channel selection ADC_CR1 register control bits (x = don’t care) Channels guarded by the analog watchdog AWDSGL bit AWDEN bit JAWDEN bit None All injected channels All regular channels All regular and injected channels Single injected channel Single...
Page 221: Discontinuous Mode
Note: It is not possible to use both the auto-injected and discontinuous modes simultaneously. Figure 35. Injected conversion latency 1. The maximum latency value can be found in the electrical characteristics of the STM32F410 datasheets. 11.3.10 Discontinuous mode Regular group This mode is enabled by setting the DISCEN bit in the ADC_CR1 register.
Page 222: Data Alignment
Analog-to-digital converter (ADC) RM0401 Example: • n = 3, channels to be converted = 0, 1, 2, 3, 6, 7, 9, 10 • 1st trigger: sequence converted 0, 1, 2. An EOC event is generated at each conversion. • 2nd trigger: sequence converted 3, 6, 7. An EOC event is generated at each conversion •...
Page 223: Channel-Wise Programmable Sampling Time
RM0401 Analog-to-digital converter (ADC) Figure 36. Right alignment of 12-bit data Figure 37. Left alignment of 12-bit data Special case: when left-aligned, the data are aligned on a half-word basis except when the resolution is set to 6-bit. in that case, the data are aligned on a byte basis as shown in Figure Figure 38.
Page 224: Conversion On External Trigger And Trigger Polarity
Analog-to-digital converter (ADC) RM0401 11.6 Conversion on external trigger and trigger polarity Conversion can be triggered by an external event (e.g. timer capture, EXTI line). If the EXTEN[1:0] control bits (for a regular conversion) or JEXTEN[1:0] bits (for an injected conversion) are different from “0b00”, then external events are able to trigger a conversion with the selected polarity.
Page 225: Fast Conversion Mode
RM0401 Analog-to-digital converter (ADC) Table 46 gives the possible external trigger for injected conversion. Table 46. External trigger for injected channels Source Connection type JEXTSEL[3:0] TIM1_CH4 event 0000 TIM1_TRGO event 0001 TIM5_CH4 event 1010 Internal signal from on-chip TIM5_TRGO event 1011 timers Not used...
Page 226: Managing A Sequence Of Conversions Without Using The Dma
Analog-to-digital converter (ADC) RM0401 DMA requests are no longer accepted. In this case, if a DMA request is made, the regular conversion in progress is aborted and further regular triggers are ignored. It is then necessary to clear the OVR flag and the DMAEN bit in the used DMA stream, and to re- initialize both the DMA and the ADC to have the wanted converted channel data transferred to the right memory location.
Page 227: Figure 39. Temperature Sensor And Vrefint Channel Block Diagram
RM0401 Analog-to-digital converter (ADC) Note: The TSVREFE bit must be set to enable the conversion of both internal channels: the ADC1_IN18 or ADC1_IN16 (temperature sensor) and the ADC1_IN17 (VREFINT). Main features • Supported temperature range: –40 to 125 °C • Precision: ±1.5 °C Figure 39.
Page 228: Battery Charge Monitoring
Analog-to-digital converter (ADC) RM0401 Note: The sensor has a startup time after waking from power down mode before it can output at the correct level. The ADC also has a startup time after power-on, so to minimize SENSE the delay, the ADON and TSVREFE bits should be set at the same time. The temperature sensor output voltage changes linearly with temperature.
Page 229: Adc Registers
RM0401 Analog-to-digital converter (ADC) 11.12 ADC registers Refer to for a list of abbreviations used in register descriptions. Section 1.2 on page 34 The peripheral registers must be written at word level (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 11.12.1 ADC status register (ADC_SR) Address offset: 0x00...
Page 230: Adc Control Register 1 (Adc_Cr1)
Analog-to-digital converter (ADC) RM0401 11.12.2 ADC control register 1 (ADC_CR1) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. OVRIE AWDEN JAWDEN Res. Res. Res. Res. Res. Res. DISCNUM[2:0] JDISCEN DISCEN JAUTO AWDSGL SCAN JEOCIE AWDIE EOCIE AWDCH[4:0] Bits 31:27 Reserved, must be kept at reset value.
Page 231 RM0401 Analog-to-digital converter (ADC) Bit 11 DISCEN: Discontinuous mode on regular channels This bit is set and cleared by software to enable/disable Discontinuous mode on regular channels. 0: Discontinuous mode on regular channels disabled 1: Discontinuous mode on regular channels enabled Bit 10 JAUTO: Automatic injected group conversion This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion.
Page 232: Adc Control Register 2 (Adc_Cr2)
Analog-to-digital converter (ADC) RM0401 11.12.3 ADC control register 2 (ADC_CR2) Address offset: 0x08 Reset value: 0x0000 0000 Res. SWSTART EXTEN EXTSEL[3:0] Res. JSWSTART JEXTEN JEXTSEL[3:0] Res. Res. Res. Res. ALIGN EOCS Res. Res. Res. Res. Res. Res. CONT ADON Bit 31 Reserved, must be kept at reset value. Bit 30 SWSTART: Start conversion of regular channels This bit is set by software to start conversion and cleared by hardware as soon as the conversion starts.
Page 233 RM0401 Analog-to-digital converter (ADC) Bits 21:20 JEXTEN: External trigger enable for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. 00: Trigger detection disabled 01: Trigger detection on the rising edge 10: Trigger detection on the falling edge 11: Trigger detection on both the rising and falling edges Bits 19:16 JEXTSEL[3:0]: External event select for injected group...
Page 234: Adc Sample Time Register 1 (Adc_Smpr1)
Analog-to-digital converter (ADC) RM0401 11.12.4 ADC sample time register 1 (ADC_SMPR1) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. SMP18[2:0] SMP17[2:0] SMP16[2:0] SMP15[2:1] SMP15_0 SMP14[2:0] SMP13[2:0] SMP12[2:0] SMP11[2:0] SMP10[2:0] Bits 31: 27 Reserved, must be kept at reset value. Bits 26:0 SMPx[2:0]: Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel.
Page 235: Adc Injected Channel Data Offset Register X (Adc_Jofrx) (X=1
RM0401 Analog-to-digital converter (ADC) 11.12.6 ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) Address offset: 0x14-0x20 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 236: Adc Regular Sequence Register 1 (Adc_Sqr1)
Analog-to-digital converter (ADC) RM0401 Res. Res. Res. Res. LT[11:0] Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 LT[11:0]: Analog watchdog lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Note: The software can write to these registers when an ADC conversion is ongoing.
Page 237: Adc Regular Sequence Register 2 (Adc_Sqr2)
RM0401 Analog-to-digital converter (ADC) 11.12.10 ADC regular sequence register 2 (ADC_SQR2) Address offset: 0x30 Reset value: 0x0000 0000 Res. Res. SQ12[4:0] SQ11[4:0] SQ10[4:1] SQ10_0 SQ9[4:0] SQ8[4:0] SQ7[4:0] Bits 31:30 Reserved, must be kept at reset value. Bits 29:26 SQ12[4:0]: 12th conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 12th in...
Page 238: Adc Injected Sequence Register (Adc_Jsqr)
Analog-to-digital converter (ADC) RM0401 11.12.12 ADC injected sequence register (ADC_JSQR) Address offset: 0x38 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. JL[1:0] JSQ4[4:1] JSQ4[0] JSQ3[4:0] JSQ2[4:0] JSQ1[4:0] Bits 31:22 Reserved, must be kept at reset value. Bits 21:20 JL[1:0]: Injected sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence.
Page 239: Adc Regular Data Register (Adc_Dr)
RM0401 Analog-to-digital converter (ADC) Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 JDATA[15:0]: Injected data These bits are read-only. They contain the conversion result from injected channel x. The data are left -or right-aligned as shown in Figure 36 Figure 11.12.14 ADC regular data register (ADC_DR)
Page 240: Adc Common Control Register (Adc_Ccr)
Analog-to-digital converter (ADC) RM0401 Bit 2 JEOC1: Injected channel end of conversion of ADC1 This bit is a copy of the JEOC bit in the ADC1_SR register. Bit 1 EOC1: End of conversion of ADC1 This bit is a copy of the EOC bit in the ADC1_SR register. Bit 0 AWD1: Analog watchdog flag of ADC1 This bit is a copy of the AWD bit in the ADC1_SR register.
Page 241: 11.12.17 Adc Register Map
RM0401 Analog-to-digital converter (ADC) 11.12.17 ADC register map The following table summarizes the ADC registers. Table 48. ADC global register map Offset Register 0x000 - 0x04C ADC1 0x050 - 0x2FC Reserved 0x300 - 0x308 Common registers Table 49. ADC register map and reset values Offset Register ADC_SR...
Page 242: Table 50. Adc Register Map And Reset Values (Common Adc Registers)
Analog-to-digital converter (ADC) RM0401 Table 49. ADC register map and reset values (continued) Offset Register ADC_SQR3 Regular channel sequence SQx_x bits 0x34 Reset value ADC_JSQR JL[1:0] Injected channel sequence JSQx_x bits 0x38 Reset value ADC_JDR1 JDATA[15:0] 0x3C Reset value ADC_JDR2 JDATA[15:0] 0x40 Reset value...
Page 243: Digital-To-Analog Converter (Dac)
RM0401 Digital-to-analog converter (DAC) Digital-to-analog converter (DAC) 12.1 Introduction The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned.
Page 244: Dac Output Buffer Enable
Digital-to-analog converter (DAC) RM0401 Figure 40. DAC channel block diagram Table 51. DAC pins Name Signal type Remarks The higher/positive reference voltage for the DAC. Input, analog positive and V are connected together on the REF+ REF+ reference package. Input, analog supply Analog power supply Input, analog supply ground Ground for analog power supply...
Page 245: Dac Channel Enable
RM0401 Digital-to-analog converter (DAC) The DAC channel output buffer can be enabled and disabled through the BOFF1 bit in the DAC_CR register. 12.4 DAC channel enable The DAC channel can be powered on by setting the EN1 bit in the DAC_CR register. The DAC channel is then enabled after a startup time t WAKEUP Note:...
Page 246: Figure 42. Timing Diagram For Conversion With Trigger Disabled Ten = 0
Digital-to-analog converter (DAC) RM0401 When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage becomes available after a time t that depends on the power supply voltage and the SETTLING analog output load. Figure 42. Timing diagram for conversion with trigger disabled TEN = 0 Independent trigger with single LFSR generation To configure the DAC in this conversion mode (see Section 12.6: Noise...
Page 247: Dac Output Voltage
RM0401 Digital-to-analog converter (DAC) 12.5.3 DAC output voltage Digital inputs are converted to output voltages on a linear conversion between 0 and V REF+ The analog output voltages on each DAC channel pin are determined by the following equation: DACoutput ×...
Page 248: Noise Generation
Digital-to-analog converter (DAC) RM0401 12.6 Noise generation In order to generate a variable-amplitude pseudonoise, an LFSR (linear feedback shift register) is available. DAC noise generation is selected by setting WAVEx[1:0] to “01”. The preloaded value in LFSR is 0xAAA. This register is updated three APB clock cycles after each trigger event, following a specific calculation algorithm.
Page 249: Triangle-Wave Generation
RM0401 Digital-to-analog converter (DAC) 12.7 Triangle-wave generation It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal. DAC triangle-wave generation is selected by setting WAVEx[1:0] to “10”. The amplitude is configured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter is incremented three APB clock cycles after each trigger event.
Page 250: Dma Request
Digital-to-analog converter (DAC) RM0401 12.8 DMA request The DAC channel has a DMA capability. One DMA channel is used to service DAC channel DMA requests. A DAC DMA request is generated when an external trigger (but not a software trigger) occurs while the DMAENx bit is set.
Page 251: Dac Registers
RM0401 Digital-to-analog converter (DAC) 12.9 DAC registers Refer to Section 1.2 on page 34 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 12.9.1 DAC control register (DAC_CR) Address offset: 0x00 Reset value: 0x0000 0000 Res.
Page 252 Digital-to-analog converter (DAC) RM0401 Bits 5:3 TSEL1[2:0]: DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. 011: TIM5 TRGO event 110: EXTI line9 111: Software trigger Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). Bit 2 TEN1: DAC channel1 trigger enable This bit is set and cleared by software to enable/disable DAC channel1 trigger.
Page 253: Dac Software Trigger Register (Dac_Swtrigr)
RM0401 Digital-to-analog converter (DAC) 12.9.2 DAC software trigger register (DAC_SWTRIGR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 254: Dac Channel1 12-Bit Left-Aligned Data Holding Register
Digital-to-analog converter (DAC) RM0401 12.9.4 DAC channel1 12-bit left-aligned data holding register (DAC_DHR12L1) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DACC1DHR[11:0] Res. Res. Res. Bits 31:16 Reserved, must be kept at reset value.
Page 255: Dac Status Register (Dac_Sr)
RM0401 Digital-to-analog converter (DAC) Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 DACC1DOR[11:0]: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1. 12.9.7 DAC status register (DAC_SR) Address offset: 0x34 Reset value: 0x0000 0000 Res.
Page 256: Dac Register Map
Digital-to-analog converter (DAC) RM0401 12.9.8 DAC register map Table 53 summarizes the DAC registers. Table 53. DAC register map and reset values Register Offset name DAC_CR 0x00 Reset value DAC_ SWTRIGR 0x04 Reset value DAC_ DACC1DHR[11:0] DHR12R1 0x08 Reset value DAC_ DACC1DHR[11:0] DHR12L1...
Page 257: True Random Number Generator (Rng)
RM0401 True random number generator (RNG) True random number generator (RNG) 13.1 Introduction The RNG is a true random number generator that continuously provides 32-bit entropy samples, based on an analog noise source. It can be used by the application as a live entropy source to build a NIST compliant Deterministic Random Bit Generator (DRBG).
Page 258: Rng Functional Description
True random number generator (RNG) RM0401 13.3 RNG functional description 13.3.1 RNG block diagram Figure 47 shows the RNG block diagram. Figure 47. RNG block diagram 13.3.2 RNG internal signals Table 54 describes a list of useful-to-know internal signals available at the RNG level, not at the STM32 product level (on pads).
Page 259: Random Number Generation
RM0401 True random number generator (RNG) 13.3.3 Random number generation The true random number generator (RNG) delivers truly random data through its AHB interface at deterministic intervals. The RNG implements the entropy source model pictured Figure 48, and provides three main functions to the application: •...
Page 260 True random number generator (RNG) RM0401 Section 13.4: RNG low-power usage. • A sampling stage of these outputs clocked by a dedicated clock input (rng_clk), delivering a 2-bit raw data output. This noise source sampling is independent to the AHB interface clock frequency (rng_hclk). Note: Section 13.7: Entropy source validation recommended RNG clock frequencies are given.
Page 261: Rng Initialization
RM0401 True random number generator (RNG) Health checks This component ensures that the entire entropy source (with its noise source) starts then operates as expected, obtaining assurance that failures are caught quickly and with a high probability and reliability. The RNG implements the following health check features: Continuous health tests, running indefinitely on the outputs of the noise source –...
Page 262: Rng Clocking
True random number generator (RNG) RM0401 To run the RNG in polling mode following steps are recommended: Enable the random number generation by setting the RNGEN bit to “1” in the RNG_CR register. Read the RNG_SR register and check that: –...
Page 263: Rng Low-Power Usage
RM0401 True random number generator (RNG) Noise source error detection When a noise source (or seed) error occurs, the RNG stops generating random numbers and sets to “1” both SEIS and SECS bits to indicate that a seed error occurred. If a value is available in the RNG_DR register, it must not be used as it may not have enough entropy.
Page 264: Entropy Source Validation
True random number generator (RNG) RM0401 13.7 Entropy source validation 13.7.1 Introduction In order to assess the amount of entropy available from the RNG, STMicroelectronics has tested the peripheral using NIST SP800-22 rev1a statistical tests. For more information on running this NIST statistical test suite, refer to STM32 microcontrollers random number generation validation using NIST statistical test suite application note (AN4230), available on STMicroelectronics website.
Page 265: Rng Registers
RM0401 True random number generator (RNG) 13.8 RNG registers The RNG is associated with a control register, a data register and a status register. 13.8.1 RNG control register (RNG_CR) Address offset: 0x000 Reset value: 0x0000 0000 Res. Res. Res. Res. Res.
Page 266: Rng Status Register (Rng_Sr)
True random number generator (RNG) RM0401 13.8.2 RNG status register (RNG_SR) Address offset: 0x004 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 267: Rng Data Register (Rng_Dr)
RM0401 True random number generator (RNG) 13.8.3 RNG data register (RNG_DR) Address offset: 0x008 Reset value: 0x0000 0000 The RNG_DR register is a read-only register that delivers a 32-bit random value when read. After being read this register delivers a new random value after 42 periods of RNG clock if the output FIFO is empty.
Page 268: Rng Register Map
True random number generator (RNG) RM0401 13.8.4 RNG register map Table 56 gives the RNG register map and reset values. Table 56. RNG register map and reset map Offset Register name RNG_CR 0x000 Reset value RNG_SR 0x004 Reset value 0 0 0 RNG_DR RNDATA[31:0] 0x008...
Page 269: Advanced-Control Timers (Tim1)
RM0401 Advanced-control timers (TIM1) Advanced-control timers (TIM1) 14.1 TIM1 introduction The advanced-control timer (TIM1) consists of a 16-bit auto-reload counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse length of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion).
Page 270: Figure 49. Advanced-Control Timer Block Diagram
Advanced-control timers (TIM1) RM0401 Figure 49. Advanced-control timer block diagram 270/771 RM0401 Rev 3...
Page 271: Tim1 Functional Description
RM0401 Advanced-control timers (TIM1) 14.3 TIM1 functional description 14.3.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.
Page 272: Figure 50. Counter Timing Diagram With Prescaler Division Change From 1 To 2
Advanced-control timers (TIM1) RM0401 Figure 50. Counter timing diagram with prescaler division change from 1 to 2 Figure 51. Counter timing diagram with prescaler division change from 1 to 4 272/771 RM0401 Rev 3...
Page 273: Counter Modes
RM0401 Advanced-control timers (TIM1) 14.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register plus one (TIMx_RCR+1).
Page 274: Figure 53. Counter Timing Diagram, Internal Clock Divided By 2
Advanced-control timers (TIM1) RM0401 Figure 53. Counter timing diagram, internal clock divided by 2 Figure 54. Counter timing diagram, internal clock divided by 4 Figure 55. Counter timing diagram, internal clock divided by N 274/771 RM0401 Rev 3...
Page 275: Figure 56. Counter Timing Diagram, Update Event When Arpe=0
RM0401 Advanced-control timers (TIM1) Figure 56. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) Figure 57. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) RM0401 Rev 3 275/771...
Page 276 Advanced-control timers (TIM1) RM0401 Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event. If the repetition counter is used, the update event (UEV) is generated after downcounting is repeated for the number of times programmed in the repetition counter register plus one (TIMx_RCR+1).
Page 277: Figure 58. Counter Timing Diagram, Internal Clock Divided By 1
RM0401 Advanced-control timers (TIM1) Figure 58. Counter timing diagram, internal clock divided by 1 Figure 59. Counter timing diagram, internal clock divided by 2 RM0401 Rev 3 277/771...
Page 278: Figure 60. Counter Timing Diagram, Internal Clock Divided By 4
Advanced-control timers (TIM1) RM0401 Figure 60. Counter timing diagram, internal clock divided by 4 Figure 61. Counter timing diagram, internal clock divided by N 278/771 RM0401 Rev 3...
Page 279: Figure 62. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
RM0401 Advanced-control timers (TIM1) Figure 62. Counter timing diagram, update event when repetition counter is not used Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto- reload value down to 1 and generates a counter underflow event.
Page 280: Figure 63. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr = 0X6
Advanced-control timers (TIM1) RM0401 DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): •...
Page 281: Figure 65. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36
RM0401 Advanced-control timers (TIM1) Figure 65. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 Center-aligned mode 2 or 3 is used with an UIF on overflow. Figure 66. Counter timing diagram, internal clock divided by N RM0401 Rev 3 281/771...
Page 282: Repetition Counter
Advanced-control timers (TIM1) RM0401 Figure 67. Counter timing diagram, update event with ARPE=1 (counter underflow) Figure 68. Counter timing diagram, update event with ARPE=1 (counter overflow) 14.3.3 Repetition counter Section 14.3.1: Time-base unit describes how the update event (UEV) is generated with respect to the counter overflows/underflows.
Page 283: Figure 69. Update Rate Examples Depending On Mode And Timx_Rcr Register Settings
RM0401 Advanced-control timers (TIM1) The repetition counter is decremented: • At each counter overflow in upcounting mode, • At each counter underflow in downcounting mode, • At each counter overflow and at each counter underflow in center-aligned mode. Although this limits the maximum number of repetition to 128 PWM cycles, it makes it possible to update the duty cycle twice per PWM period.
Page 284: Clock Selection
Advanced-control timers (TIM1) RM0401 14.3.4 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin • External clock mode2: external trigger input ETR • Internal trigger inputs (ITRx): using one timer as prescaler for another timer Internal clock source (CK_INT) If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed...
Page 285: Figure 71. Ti2 External Clock Connection Example
RM0401 Advanced-control timers (TIM1) Figure 71. TI2 external clock connection example For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register.
Page 286: Figure 72. Control Circuit In External Clock Mode 1
Advanced-control timers (TIM1) RM0401 Figure 72. Control circuit in external clock mode 1 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. Figure 73 gives an overview of the external trigger input block.
Page 287: Capture/Compare Channels
RM0401 Advanced-control timers (TIM1) As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
Page 288: Figure 75. Capture/Compare Channel (Example: Channel 1 Input Stage)
Advanced-control timers (TIM1) RM0401 Figure 75. Capture/compare channel (example: channel 1 input stage) The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. Figure 76. Capture/compare channel 1 main circuit 288/771 RM0401 Rev 3...
Page 289: Figure 77. Output Stage Of Capture/Compare Channel (Channels 1 To 3)
RM0401 Advanced-control timers (TIM1) Figure 77. Output stage of capture/compare channel (channels 1 to 3) Figure 78. Output stage of capture/compare channel (channel 4) The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
Page 290: Input Capture Mode
Advanced-control timers (TIM1) RM0401 14.3.6 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled.
Page 291: Pwm Input Mode
RM0401 Advanced-control timers (TIM1) 14.3.7 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. •...
Page 292: Output Compare Mode
Advanced-control timers (TIM1) RM0401 To force an output compare signal (OCXREF/OCx) to its active level, one just needs to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. For example: CCxP=0 (OCx active high) =>...
Page 293: Pwm Mode
RM0401 Advanced-control timers (TIM1) Figure 80. Output compare mode, toggle on OC1. 14.3.10 PWM mode Pulse Width Modulation mode allows to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 294: Figure 81. Edge-Aligned Pwm Waveforms (Arr=8)
Advanced-control timers (TIM1) RM0401 PWM edge-aligned mode • Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Upcounting mode. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <...
Page 295: Figure 82. Center-Aligned Pwm Waveforms (Arr=8)
RM0401 Advanced-control timers (TIM1) Figure 82 shows some center-aligned PWM waveforms in an example where: • TIMx_ARR=8, • PWM mode is the PWM mode 1, • The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register. Figure 82.
Page 296: Complementary Outputs And Dead-Time Insertion
Advanced-control timers (TIM1) RM0401 Hints on using center-aligned mode: • When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software.
Page 297: Figure 83. Complementary Output With Dead-Time Insertion
RM0401 Advanced-control timers (TIM1) Figure 83. Complementary output with dead-time insertion. Figure 84. Dead-time waveforms with delay greater than the negative pulse. Figure 85. Dead-time waveforms with delay greater than the positive pulse. The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register.
Page 298: Using The Break Function
Advanced-control timers (TIM1) RM0401 have both outputs at inactive level or both outputs active and complementary with dead- time. Note: When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes active when OCxREF is high whereas OCxN is complemented and becomes active when OCxREF is low.
Page 299 RM0401 Advanced-control timers (TIM1) active level together. Note that because of the resynchronization on MOE, the dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles). – If OSSI=0 then the timer releases the enable outputs else the enable outputs remain or become high as soon as one of the CCxE or CCxNE bits is high.
Page 300: Figure 86. Output Behavior In Response To A Break
Advanced-control timers (TIM1) RM0401 Figure 86. Output behavior in response to a break. 300/771 RM0401 Rev 3...
Page 301: Clearing The Ocxref Signal On An External Event
RM0401 Advanced-control timers (TIM1) 14.3.13 Clearing the OCxREF signal on an external event The OCxREF signal for a given channel can be driven Low by applying a High level to the ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The OCxREF signal remains Low until the next update event, UEV, occurs.
Page 302: 6-Step Pwm Generation
Advanced-control timers (TIM1) RM0401 14.3.14 6-step PWM generation When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Thus one can program in advance the configuration for the next step and change the configuration of all the channels at the same time.
Page 303: One-Pulse Mode
RM0401 Advanced-control timers (TIM1) 14.3.15 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 304: Encoder Interface Mode
Advanced-control timers (TIM1) RM0401 The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY • The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
Page 305: Table 57. Counting Direction Versus Encoder Signals
RM0401 Advanced-control timers (TIM1) TIMx_ARR must be configured before starting. In the same way, the capture, compare, prescaler, repetition counter, trigger output features continue to work as normal. Encoder mode and External clock mode 2 are not compatible and must not be selected together. In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s position.
Page 306: Figure 90. Example Of Counter Operation In Encoder Interface Mode
Advanced-control timers (TIM1) RM0401 Figure 90. Example of counter operation in encoder interface mode. Figure 91 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’). Figure 91. Example of encoder interface mode with TI1FP1 polarity inverted. The timer, when configured in Encoder Interface mode provides information on the sensor’s current position.
Page 307: Timer Input Xor Function
RM0401 Advanced-control timers (TIM1) 14.3.17 Timer input XOR function The TI1S bit in the TIMx_CR2 register allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and TIMx_CH3.
Page 308: Figure 92. Example Of Hall Sensor Interface
Advanced-control timers (TIM1) RM0401 Figure 92 describes this example. Figure 92. Example of Hall sensor interface 308/771 RM0401 Rev 3...
Page 309: Timx And External Trigger Synchronization
RM0401 Advanced-control timers (TIM1) 14.3.19 TIMx and external trigger synchronization The TIMx timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated.
Page 310: Figure 94. Control Circuit In Gated Mode
Advanced-control timers (TIM1) RM0401 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we do not need any filter, so we keep IC1F=0000).
Page 311: Figure 95. Control Circuit In Trigger Mode
RM0401 Advanced-control timers (TIM1) Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: • Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we do not need any filter, so we keep IC2F=0000).
Page 312: Debug Mode
Advanced-control timers (TIM1) RM0401 Configure the channel 1 as follows, to detect rising edges on TI: – IC1F=0000: no filter. – The capture prescaler is not used for triggering and does not need to be configured. – CC1S=01 in TIMx_CCMR1 register to select only the input capture source –...
Page 313: Tim1 Registers
RM0401 Advanced-control timers (TIM1) 14.4 TIM1 registers Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in register descriptions. The peripheral registers must be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-word (16 bits) or words (32 bits).
Page 314: Tim1 Control Register 2 (Timx_Cr2)
Advanced-control timers (TIM1) RM0401 Bit 3 OPM: One pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled.
Page 315 RM0401 Advanced-control timers (TIM1) Bit 11 OIS2N: Output Idle state 2 (OC2N output) refer to OIS1N bit Bit 10 OIS2: Output Idle state 2 (OC2 output) refer to OIS1 bit Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
Page 316: Tim1 Slave Mode Control Register (Timx_Smcr)
Advanced-control timers (TIM1) RM0401 Bit 1 Reserved, must be kept at reset value. Bit 0 CCPC: Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit).
Page 317 RM0401 Advanced-control timers (TIM1) Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 318: Tim1 Dma/Interrupt Enable Register (Timx_Dier)
Advanced-control timers (TIM1) RM0401 Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
Page 319 RM0401 Advanced-control timers (TIM1) Bit 11 CC3DE: Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled 1: CC3 DMA request enabled Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled 1: CC2 DMA request enabled Bit 9 CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled 1: CC1 DMA request enabled...
Page 320: Tim1 Status Register (Timx_Sr)
Advanced-control timers (TIM1) RM0401 14.4.5 TIM1 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. CC4OF CC3OF CC2OF CC1OF Res. COMIF CC4IF CC3IF CC2IF CC1IF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:13 Reserved, must be kept at reset value.
Page 321: Tim1 Event Generation Register (Timx_Egr)
RM0401 Advanced-control timers (TIM1) Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
Page 322 Advanced-control timers (TIM1) RM0401 Bit 5 COMG: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware 0: No action 1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits Note: This bit acts only on channels having a complementary output.
Page 323: Tim1 Capture/Compare Mode Register 1 (Timx_Ccmr1)
RM0401 Advanced-control timers (TIM1) 14.4.7 TIM1 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 324 Advanced-control timers (TIM1) RM0401 Bits 6:4 OC1M: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 325 RM0401 Advanced-control timers (TIM1) Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC.
Page 326: Tim1 Capture/Compare Mode Register 2 (Timx_Ccmr2)
Advanced-control timers (TIM1) RM0401 Bits 3:2 IC1PSC: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events...
Page 327: Tim1 Capture/Compare Enable Register (Timx_Ccer)
RM0401 Advanced-control timers (TIM1) Bit 3 OC3PE: Output compare 3 preload enable Bit 2 OC3FE: Output compare 3 fast enable Bits 1:0 CC3S: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4...
Page 328 Advanced-control timers (TIM1) RM0401 Bit 12 CC4E: Capture/Compare 4 output enable refer to CC1E description Bit 11 CC3NP: Capture/Compare 3 complementary output polarity refer to CC1NP description Bit 10 CC3NE: Capture/Compare 3 complementary output enable refer to CC1NE description Bit 9 CC3P: Capture/Compare 3 output polarity refer to CC1P description Bit 8 CC3E: Capture/Compare 3 output enable refer to CC1E description...
Page 329 RM0401 Advanced-control timers (TIM1) Bit 1 CC1P: Capture/Compare 1 output polarity CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations.
Page 330: Table 59. Output Control Bits For Complementary Ocx And Ocxn Channels
Advanced-control timers (TIM1) RM0401 Table 59. Output control bits for complementary OCx and OCxN channels with break feature Control bits Output states OSSI OSSR CCxE CCxNE OCx output state OCxN output state Output Disabled (not driven by Output Disabled (not driven by the timer) the timer) OCxN=0, OCxN_EN=0 OCx=0, OCx_EN=0...
Page 331: Tim1 Counter (Timx_Cnt)
RM0401 Advanced-control timers (TIM1) Note: The state of the external I/O pins connected to the complementary OCx and OCxN channels depends on the OCx and OCxN channel state and the GPIO registers. 14.4.10 TIM1 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 14.4.11...
Page 332: Tim1 Repetition Counter Register (Timx_Rcr)
Advanced-control timers (TIM1) RM0401 14.4.13 TIM1 repetition counter register (TIMx_RCR) Address offset: 0x30 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. REP[7:0] Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e.
Page 333: Tim1 Capture/Compare Register 2 (Timx_Ccr2)
RM0401 Advanced-control timers (TIM1) 14.4.15 TIM1 capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE).
Page 334: Tim1 Capture/Compare Register 4 (Timx_Ccr4)
Advanced-control timers (TIM1) RM0401 14.4.17 TIM1 capture/compare register 4 (TIMx_CCR4) Address offset: 0x40 Reset value: 0x0000 CCR4[15:0] Bits 15:0 CCR4[15:0]: Capture/Compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE).
Page 335 RM0401 Advanced-control timers (TIM1) Bit 13 BKP: Break polarity 0: Break input BRK is active low 1: Break input BRK is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 336: Tim1 Dma Control Register (Timx_Dcr)
Advanced-control timers (TIM1) RM0401 Bits 7:0 DTG[7:0]: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x t with t DTG[7:5]=10x => DT=(64+DTG[5:0])xt with T =2xt DTG[7:5]=110 =>...
Page 337: Tim1 Dma Address For Full Transfer (Timx_Dmar)
RM0401 Advanced-control timers (TIM1) 14.4.20 TIM1 DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 DMAB[15:0] Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the...
Page 338: Tim1 Register Map
Advanced-control timers (TIM1) RM0401 14.4.21 TIM1 register map TIM1 registers are mapped as 16-bit addressable registers as described in the table below: Table 60. TIM1 register map and reset values Offset Register TIMx_CR1 [1:0] [1:0] 0x00 Reset value TIMx_CR2 MMS[2:0] 0x04 Reset value ETPS...
Page 339 RM0401 Advanced-control timers (TIM1) Table 60. TIM1 register map and reset values (continued) Offset Register TIMx_CCR1 CCR1[15:0] 0x34 Reset value TIMx_CCR2 CCR2[15:0] 0x38 Reset value TIMx_CCR3 CCR3[15:0] 0x3C Reset value TIMx_CCR4 CCR4[15:0] 0x40 Reset value LOCK TIMx_BDTR DT[7:0] [1:0] 0x44 Reset value TIMx_DCR DBL[4:0]...
Page 340: General-Purpose Timers (Tim5)
General-purpose timers (TIM5) RM0401 General-purpose timers (TIM5) 15.1 TIM5 introduction The general-purpose timer consists of a 32-bit auto-reload counter driven by a programmable prescaler. It can be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM).
Page 341: Tim5 Functional Description
RM0401 General-purpose timers (TIM5) Figure 97. General-purpose timer block diagram 15.3 TIM5 functional description 15.3.1 Time-base unit The main block of the programmable timer is a 32-bit counter with its related auto-reload register. The counter can count up. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
Page 342: Figure 98. Counter Timing Diagram With Prescaler Division Change From 1 To 2
General-purpose timers (TIM5) RM0401 The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling). Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.
Page 343: Counter Modes
RM0401 General-purpose timers (TIM5) Figure 99. Counter timing diagram with prescaler division change from 1 to 4 15.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An Update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
Page 344: Figure 100. Counter Timing Diagram, Internal Clock Divided By 1
General-purpose timers (TIM5) RM0401 Figure 100. Counter timing diagram, internal clock divided by 1 Figure 101. Counter timing diagram, internal clock divided by 2 Figure 102. Counter timing diagram, internal clock divided by 4 344/771 RM0401 Rev 3...
Page 345: Figure 103. Counter Timing Diagram, Internal Clock Divided By N
RM0401 General-purpose timers (TIM5) Figure 103. Counter timing diagram, internal clock divided by N Figure 104. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) RM0401 Rev 3 345/771...
Page 346: Figure 105. Counter Timing Diagram, Update Event When Arpe=1 (Timx_Arr Preloaded)
General-purpose timers (TIM5) RM0401 Figure 105. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event.
Page 347: Figure 106. Counter Timing Diagram, Internal Clock Divided By 1
RM0401 General-purpose timers (TIM5) Figure 106. Counter timing diagram, internal clock divided by 1 Figure 107. Counter timing diagram, internal clock divided by 2 Figure 108. Counter timing diagram, internal clock divided by 4 RM0401 Rev 3 347/771...
Page 348: Figure 109. Counter Timing Diagram, Internal Clock Divided By N
General-purpose timers (TIM5) RM0401 Figure 109. Counter timing diagram, internal clock divided by N Figure 110. Counter timing diagram, Update event Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) –...
Page 349: Figure 111. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr=0X6
RM0401 General-purpose timers (TIM5) In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated by hardware and gives the current direction of the counter. The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event.
Page 350: Figure 112. Counter Timing Diagram, Internal Clock Divided By 2
General-purpose timers (TIM5) RM0401 Figure 112. Counter timing diagram, internal clock divided by 2 Figure 113. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 1. Center-aligned mode 2 or 3 is used with an UIF on overflow. Figure 114. Counter timing diagram, internal clock divided by N 350/771 RM0401 Rev 3...
Page 351: Clock Selection
RM0401 General-purpose timers (TIM5) Figure 115. Counter timing diagram, Update event with ARPE=1 (counter underflow) Figure 116. Counter timing diagram, Update event with ARPE=1 (counter overflow) 15.3.3 Clock selection The counter clock can be provided by the following clock sources: •...
Page 352: Figure 117. Control Circuit In Normal Mode, Internal Clock Divided By 1
General-purpose timers (TIM5) RM0401 Internal clock source (CK_INT) If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG which remains cleared automatically).
Page 353: Capture/Compare Channels
RM0401 General-purpose timers (TIM5) For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01 in the TIMx_CCMR1 register.
Page 354: Figure 120. Capture/Compare Channel (Example: Channel 1 Input Stage)
General-purpose timers (TIM5) RM0401 Figure 120. Capture/compare channel (example: channel 1 input stage) The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. Figure 121. Capture/compare channel 1 main circuit 354/771 RM0401 Rev 3...
Page 355: Input Capture Mode
RM0401 General-purpose timers (TIM5) Figure 122. Output stage of capture/compare channel (channel 1) The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
Page 356: Pwm Input Mode
General-purpose timers (TIM5) RM0401 new level have been detected (sampled at f frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. • Select the edge of the active transition on the TI1 channel by writing the CC1P and CC1NP bits to 00 in the TIMx_CCER register (rising edge in this case).
Page 357: Forced Output Mode
RM0401 General-purpose timers (TIM5) For example, one can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): • Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected).
Page 358: Output Compare Mode
General-purpose timers (TIM5) RM0401 Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the Output Compare Mode section. 15.3.8 Output compare mode This function is used to control an output waveform or indicating when a period of time has...
Page 359: Pwm Mode
RM0401 General-purpose timers (TIM5) Figure 124. Output compare mode, toggle on OC1 15.3.9 PWM mode Pulse width modulation mode allows to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 360: Figure 125. Edge-Aligned Pwm Waveforms (Arr=8)
General-purpose timers (TIM5) RM0401 PWM edge-aligned mode Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Section : Upcounting mode on page 343. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <TIMx_CCRx else it becomes low.
Page 361: Figure 126. Center-Aligned Pwm Waveforms (Arr=8)
RM0401 General-purpose timers (TIM5) Section : Center-aligned mode (up/down counting) on page 348. Figure 126 shows some center-aligned PWM waveforms in an example where: • TIMx_ARR=8, • PWM mode is the PWM mode 1, • The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register.
Page 362: One-Pulse Mode
General-purpose timers (TIM5) RM0401 in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. • Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results.
Page 363: Encoder Interface Mode
RM0401 General-purpose timers (TIM5) Let’s use TI2FP2 as trigger 1: • Map TI2FP2 on TI2 by writing CC2S=01 in the TIMx_CCMR1 register. • TI2FP2 must detect a rising edge, write CC2P=0 and CC2NP=’0’ in the TIMx_CCER register. • Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=110 in the TIMx_SMCR register.
Page 364: Table 61. Counting Direction Versus Encoder Signals
General-purpose timers (TIM5) RM0401 TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in TIMx_CR1 register written to ‘1). The sequence of transitions of the two inputs is evaluated and generates count pulses as well as the direction signal. Depending on the sequence the counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware accordingly.
Page 365: Figure 128. Example Of Counter Operation In Encoder Interface Mode
RM0401 General-purpose timers (TIM5) Figure 128. Example of counter operation in encoder interface mode Figure 129 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=1). Figure 129. Example of encoder interface mode with TI1FP1 polarity inverted The timer, when configured in Encoder Interface mode provides information on the sensor’s current position.
Page 366: Timer Input Xor Function
General-purpose timers (TIM5) RM0401 15.3.12 Timer input XOR function The TI1S bit in the TIM_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3. The XOR output can be used with all the timer input functions such as trigger or input capture.
Page 367: Figure 131. Control Circuit In Gated Mode
RM0401 General-purpose timers (TIM5) Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we do not need any filter, so we keep IC1F=0000).
Page 368: Debug Mode
General-purpose timers (TIM5) RM0401 The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input. Figure 132. Control circuit in trigger mode 15.3.14 Debug mode ® When the microcontroller enters debug mode (Cortex -M4 with FPU core - halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBGMCU module.
Page 369: Tim5 Registers
RM0401 General-purpose timers (TIM5) 15.4 TIM5 registers Refer to Section 1.2 on page 34 for a list of abbreviations used in register descriptions. The 32-bit peripheral registers have to be written by words (32 bits). All other peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
Page 370 General-purpose timers (TIM5) RM0401 Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: –...
Page 371: Timx Control Register 2 (Timx_Cr2)
RM0401 General-purpose timers (TIM5) 15.4.2 TIMx control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. TI1S MMS[2:0] CCDS Res. Res. Res. Bits 15:8 Reserved, must be kept at reset value. Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) Bits 6:4 MMS[2:0]: Master mode selection...
Page 372: Timx Slave Mode Control Register (Timx_Smcr)
General-purpose timers (TIM5) RM0401 15.4.3 TIMx slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. TS[2:0] Res. SMS[2:0] Bits 15:8 Reserved, must be kept at reset value. Bit 7 MSM: Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO).
Page 373: Timx Dma/Interrupt Enable Register (Timx_Dier)
RM0401 General-purpose timers (TIM5) Table 62. TIMx internal trigger connection Slave TIM ITR0 (TS = 000) ITR1 (TS = 001) ITR2 (TS = 010) ITR3 (TS = 011) TIM5 Reserved LPTIM Reserved Reserved 15.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 Res.
Page 374: Timx Status Register (Timx_Sr)
General-purpose timers (TIM5) RM0401 Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled 1: CC2 interrupt enabled Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled 15.4.5...
Page 375 RM0401 General-purpose timers (TIM5) Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
Page 376: Timx Event Generation Register (Timx_Egr)
General-purpose timers (TIM5) RM0401 15.4.6 TIMx event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC4G CC3G CC2G CC1G Bits 15:7 Reserved, must be kept at reset value. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
Page 377: Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)
RM0401 General-purpose timers (TIM5) 15.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 378 General-purpose timers (TIM5) RM0401 Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 379 RM0401 General-purpose timers (TIM5) Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output.
Page 380: Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)
General-purpose timers (TIM5) RM0401 15.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. Res. OC4M[2:0] OC4PE OC4FE Res. OC3M[2:0] OC3PE OC3FE CC4S[1:0] CC3S[1:0] IC4F[3:0] IC4PSC[1:0] IC3F[3:0] IC3PSC[1:0] Output compare mode Bit 15 Reserved, must be kept at reset value.
Page 381: Timx Capture/Compare Enable Register (Timx_Ccer)
RM0401 General-purpose timers (TIM5) Input capture mode Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3...
Page 382: Table 63. Output Control Bit For Standard Ocx Channels
General-purpose timers (TIM5) RM0401 Bit 7 CC2NP: Capture/Compare 2 output Polarity. refer to CC1NP description Bit 6 Reserved, must be kept at reset value. Bit 5 CC2P: Capture/Compare 2 output Polarity. refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable. refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 output Polarity.
Page 383: Timx Counter (Timx_Cnt)
RM0401 General-purpose timers (TIM5) 15.4.10 TIMx counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 15.4.11 TIMx prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1).
Page 384: Timx Capture/Compare Register 1 (Timx_Ccr1)
General-purpose timers (TIM5) RM0401 15.4.13 TIMx capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 0000 CCR1[31:16] (depending on timers) CCR1[15:0] Bits 31:16 CCR1[31:16]: High Capture/Compare 1 value Bits 15:0 CCR1[15:0]: Low Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
Page 385: Timx Capture/Compare Register 4 (Timx_Ccr4)
RM0401 General-purpose timers (TIM5) Reset value: 0x0000 0000 CCR3[31:16] (depending on timers) CCR3[15:0] Bits 31:16 CCR3[31:16]: High Capture/Compare 3 value. Bits 15:0 CCR3[15:0]: Low Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR register (bit OC3PE).
Page 386: Timx Dma Address For Full Transfer (Timx_Dmar)
General-purpose timers (TIM5) RM0401 Reset value: 0x0000 Res. Res. Res. DBL[4:0] Res. Res. Res. DBA[4:0] Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address).
Page 387: Tim5 Option Register (Tim5_Or)
RM0401 General-purpose timers (TIM5) Configure the corresponding DMA channel as follows: – DMA channel peripheral address is the DMAR register address – DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers. –...
Page 388: Timx Register Map
General-purpose timers (TIM5) RM0401 15.4.20 TIMx register map TIMx registers are mapped as described in the table below: Table 64. TIM5 register map and reset values Offset Register TIMx_CR1 [1:0] [1:0] 0x00 Reset value TIMx_CR2 MMS[2:0] 0x04 Reset value ETPS TIMx_SMCR ETF[3:0] TS[2:0]...
Page 389 RM0401 General-purpose timers (TIM5) Table 64. TIM5 register map and reset values (continued) Offset Register TIMx_PSC PSC[15:0] 0x28 Reset value TIMx_ARR ARR[31:16] ARR[15:0] 0x2C Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x30 Reserved TIMx_CCR1...
Page 390: General-Purpose Timers (Tim9 And Tim11)
General-purpose timers (TIM9 and TIM11) RM0401 General-purpose timers (TIM9 and TIM11) 16.1 TIM9 and TIM11 introduction The TIM9 and TIM11 general-purpose timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM).
Page 391: Tim11 Main Features
RM0401 General-purpose timers (TIM9 and TIM11) Figure 133. General-purpose timer block diagram (TIM9) Internal clock (CK_INT) ITR0 Trigger controller ITR1 ITR2 TRGI Slave ITR3 Reset, Enable, Count mode TI1F_ED controller TI1FP1 TI2FP2 Auto-reload register Stop, Clear CK_PSC CK_CNT Prescaler COUNTER CC1I CC1I TI1FP1...
Page 392: Figure 134. General-Purpose Timer Block Diagram (Tim11)
General-purpose timers (TIM9 and TIM11) RM0401 Figure 134. General-purpose timer block diagram (TIM11) 392/771 RM0401 Rev 3...
Page 393: Tim9 And Tim11 Functional Description
RM0401 General-purpose timers (TIM9 and TIM11) 16.3 TIM9 and TIM11 functional description 16.3.1 Time-base unit The main block of the timer is a 16-bit counter with its related auto-reload register. The counters counts up. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
Page 394: Figure 135. Counter Timing Diagram With Prescaler Division Change From 1 To 2
General-purpose timers (TIM9 and TIM11) RM0401 Figure 135. Counter timing diagram with prescaler division change from 1 to 2 Figure 136. Counter timing diagram with prescaler division change from 1 to 4 394/771 RM0401 Rev 3...
Page 395: Counter Modes
RM0401 General-purpose timers (TIM9 and TIM11) 16.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller on TIM9) also generates an update event.
Page 396: Figure 138. Counter Timing Diagram, Internal Clock Divided By 2
General-purpose timers (TIM9 and TIM11) RM0401 Figure 138. Counter timing diagram, internal clock divided by 2 Figure 139. Counter timing diagram, internal clock divided by 4 Figure 140. Counter timing diagram, internal clock divided by N 396/771 RM0401 Rev 3...
Page 397: Figure 141. Counter Timing Diagram, Update Event When Arpe=0
RM0401 General-purpose timers (TIM9 and TIM11) Figure 141. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) Figure 142. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) RM0401 Rev 3 397/771...
Page 398: Clock Selection
General-purpose timers (TIM9 and TIM11) RM0401 16.3.3 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1 (for TIM9): external input pin (TIx) • Internal trigger inputs (ITRx) (for TIM9): connecting the trigger output from another timer.
Page 399: Figure 144. Ti2 External Clock Connection Example
RM0401 General-purpose timers (TIM9 and TIM11) Figure 144. TI2 external clock connection example For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register.
Page 400: Capture/Compare Channels
General-purpose timers (TIM9 and TIM11) RM0401 16.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). Figure 146 Figure 148 give an overview of one capture/compare channel.
Page 401: Input Capture Mode
RM0401 General-purpose timers (TIM9 and TIM11) Figure 147. Capture/compare channel 1 main circuit Figure 148. Output stage of capture/compare channel (channel 1) The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
Page 402: Pwm Input Mode (Only For Tim9)
General-purpose timers (TIM9 and TIM11) RM0401 cleared by software by writing it to ‘0’ or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when it is written with 0. The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises.
Page 403: Forced Output Mode
RM0401 General-purpose timers (TIM9 and TIM11) Select the active input for TIMx_CCR1: write the CC1S bits to ‘01’ in the TIMx_CCMR1 register (TI1 selected). Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): program the CC1P and CC1NP bits to ‘00’ (active on rising edge). Select the active input for TIMx_CCR2: write the CC2S bits to ‘10’...
Page 404: Output Compare Mode
General-purpose timers (TIM9 and TIM11) RM0401 16.3.8 Output compare mode This function is used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare function: Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP...
Page 405: Pwm Mode
RM0401 General-purpose timers (TIM9 and TIM11) Figure 150. Output compare mode, toggle on OC1. 16.3.9 PWM mode Pulse Width Modulation mode allows to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 406: One-Pulse Mode
General-purpose timers (TIM9 and TIM11) RM0401 Figure 151. Edge-aligned PWM waveforms (ARR=8) 16.3.10 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.
Page 407: Figure 152. Example Of One Pulse Mode
RM0401 General-purpose timers (TIM9 and TIM11) Figure 152. Example of one pulse mode. For example one may want to generate a positive pulse on OC1 with a length of t PULSE after a delay of t as soon as a positive edge is detected on the TI2 input pin. DELAY Use TI2FP2 as trigger 1: Map TI2FP2 to TI2 by writing CC2S=’01’...
Page 408: Tim9 External Trigger Synchronization
General-purpose timers (TIM9 and TIM11) RM0401 Particular case: OCx fast enable In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle.
Page 409: Figure 153. Control Circuit In Reset Mode
RM0401 General-purpose timers (TIM9 and TIM11) Figure 153. Control circuit in reset mode Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: Configure the channel 1 to detect low levels on TI1.
Page 410: Figure 154. Control Circuit In Gated Mode
General-purpose timers (TIM9 and TIM11) RM0401 Figure 154. Control circuit in gated mode Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: Configure the channel 2 to detect rising edges on TI2.
Page 411: Debug Mode
RM0401 General-purpose timers (TIM9 and TIM11) 16.3.12 Debug mode ® When the microcontroller enters debug mode (Cortex -M4 with FPU core halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBGMCU module. For more details, refer to Section 26.16.2: Debug support for timers, watchdog, and I2C.
Page 412 General-purpose timers (TIM9 and TIM11) RM0401 Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generates an update interrupt if enabled: – Counter overflow –...
Page 413: Tim9 Slave Mode Control Register (Timx_Smcr)
RM0401 General-purpose timers (TIM9 and TIM11) 16.4.2 TIM9 slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. TS[2:0] Res. SMS[2:0] Bits 15:8 Reserved, must be kept at reset value. Bit 7 MSM: Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO).
Page 414: Tim9 Interrupt Enable Register (Timx_Dier)
General-purpose timers (TIM9 and TIM11) RM0401 Table 65. TIMx internal trigger connections Slave TIM ITR0 (TS = ‘000’) ITR1 (TS = ‘001’) ITR2 (TS = ‘010’) ITR3 (TS = ‘011’) TIM5 Reserved LPTIM Reserved Reserved TIM9 Reserved LPTIM Reserved TIM11 16.4.3 TIM9 Interrupt enable register (TIMx_DIER) Address offset: 0x0C...
Page 415: Tim9 Status Register (Timx_Sr)
RM0401 General-purpose timers (TIM9 and TIM11) 16.4.4 TIM9 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. Res. Res. CC2OF CC1OF Res. Res. Res. Res. Res. CC2IF CC1IF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:11 Reserved, must be kept at reset value. Bit 10 CC2OF: Capture/compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag...
Page 416 General-purpose timers (TIM9 and TIM11) RM0401 Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value. It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
Page 417: Tim9 Event Generation Register (Timx_Egr)
RM0401 General-purpose timers (TIM9 and TIM11) 16.4.5 TIM9 event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC2G CC1G Bits 15:7 Reserved, must be kept at reset value. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
Page 418 General-purpose timers (TIM9 and TIM11) RM0401 Output compare mode Bit 15 Reserved, must be kept at reset value. Bits 14:12 OC2M[2:0]: Output compare 2 mode Bit 11 OC2PE: Output compare 2 preload enable Bit 10 OC2FE: Output compare 2 fast enable Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bitfield defines the direction of the channel (input/output) as well as the used input.
Page 419 RM0401 General-purpose timers (TIM9 and TIM11) Bit 3 OC1PE: Output compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken into account immediately 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register.
Page 420 General-purpose timers (TIM9 and TIM11) RM0401 Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1...
Page 421: Tim9 Capture/Compare Enable Register (Timx_Ccer)
RM0401 General-purpose timers (TIM9 and TIM11) 16.4.7 TIM9 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. CC2NP Res. CC2P CC2E CC1NP Res. CC1P CC1E Bits 15:8 Reserved, must be kept at reset value. Bit 7 CC2NP: Capture/Compare 2 output Polarity refer to CC1NP description Bit 6 Reserved, must be kept at reset value.
Page 422: Tim9 Counter (Timx_Cnt)
General-purpose timers (TIM9 and TIM11) RM0401 Table 66. Output control bit for standard OCx channels CCxE bit OCx output state Output disabled (OCx=’0’, OCx_EN=’0’) OCx=OCxREF + Polarity, OCx_EN=’1’ Note: The states of the external I/O pins connected to the standard OCx channels depend on the state of the OCx channel and on the GPIO registers.
Page 423: Tim9 Capture/Compare Register 1 (Timx_Ccr1)
RM0401 General-purpose timers (TIM9 and TIM11) 16.4.11 TIM9 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 CCR1[15:0] Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded into the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (OC1PE bit).
Page 424: Tim9 Register Map
General-purpose timers (TIM9 and TIM11) RM0401 16.4.13 TIM9 register map TIM9 registers are mapped as 16-bit addressable registers as described below: Table 67. TIM9 register map and reset values Offset Register TIMx_CR1 [1:0] 0x00 Reset value TIMx_SMCR TS[2:0] SMS[2:0] 0x08 Reset value TIMx_DIER 0x0C...
Page 425 RM0401 General-purpose timers (TIM9 and TIM11) Table 67. TIM9 register map and reset values (continued) Offset Register TIMx_CCR1 CCR1[15:0] 0x34 Reset value TIMx_CCR2 CCR2[15:0] 0x38 Reset value 0x3C to Reserved 0x4C Refer to Section 2.2 on page 41 for the register boundary addresses. RM0401 Rev 3 425/771...
Page 426: Tim11 Registers
General-purpose timers (TIM9 and TIM11) RM0401 16.5 TIM11 registers The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 16.5.1 TIM11 control register 1 (TIMx_CR1) Address offset: 0x00...
Page 427: Tim11 Interrupt Enable Register (Timx_Dier)
RM0401 General-purpose timers (TIM9 and TIM11) 16.5.2 TIM11 Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC1IE Bits 15:2 Reserved, must be kept at reset value. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled...
Page 428: Tim11 Event Generation Register (Timx_Egr)
General-purpose timers (TIM9 and TIM11) RM0401 Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value. It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
Page 429: Tim11 Capture/Compare Mode Register 1
RM0401 General-purpose timers (TIM9 and TIM11) 16.5.5 TIM11 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 430 General-purpose timers (TIM9 and TIM11) RM0401 Output compare mode Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 is derived.
Page 431 RM0401 General-purpose timers (TIM9 and TIM11) Input capture mode Bits 15:8 Reserved, must be kept at reset value. Bits 7:4 IC1F: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1.
Page 432: Tim11 Capture/Compare Enable Register
General-purpose timers (TIM9 and TIM11) RM0401 16.5.6 TIM11 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC1NP Res. CC1P CC1E Bits 15:4 Reserved, must be kept at reset value. Bit 3 CC1NP: Capture/Compare 1 complementary output Polarity.
Page 433: Tim11 Counter (Timx_Cnt)
RM0401 General-purpose timers (TIM9 and TIM11) 16.5.7 TIM11 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 16.5.8 TIM11 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1).
Page 434: Tim11 Capture/Compare Register 1 (Timx_Ccr1)
General-purpose timers (TIM9 and TIM11) RM0401 16.5.10 TIM11 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 CCR1[15:0] Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE).
Page 435: Tim11 Register Map
RM0401 General-purpose timers (TIM9 and TIM11) 16.5.12 TIM11 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Table 69. TIM11 register map and reset values Offset Register TIMx_CR1 [1:0] 0x00 Reset value TIMx_SMCR 0x08 Reset value TIMx_DIER...
Page 436 General-purpose timers (TIM9 and TIM11) RM0401 Table 69. TIM11 register map and reset values (continued) Offset Register TIMx_CCR1 CCR1[15:0] 0x34 Reset value 0x38 to Reserved 0x4C TIMx_OR 0x50 Reset value Refer to Section 2.2.2 on page 38 for the register boundary addresses. 436/771 RM0401 Rev 3...
Page 437: Basic Timers (Tim6)
RM0401 Basic timers (TIM6) Basic timers (TIM6) 17.1 Introduction The basic timer TIM6 consists of a 16-bit auto-reload counter driven by a programmable prescaler. IT can be used as generic timer for timebase generation but it is also specifically used to drive the digital-to-analog converter (DAC).
Page 438: Tim6 Functional Description
Basic timers (TIM6) RM0401 17.3 TIM6 functional description 17.3.1 Time-base unit The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
Page 439: Figure 157. Counter Timing Diagram With Prescaler Division Change From 1 To 2
RM0401 Basic timers (TIM6) Figure 157. Counter timing diagram with prescaler division change from 1 to 2 Figure 158. Counter timing diagram with prescaler division change from 1 to 4 RM0401 Rev 3 439/771...
Page 440: Counting Mode
Basic timers (TIM6) RM0401 17.3.2 Counting mode The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An update event can be generate at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
Page 441: Figure 160. Counter Timing Diagram, Internal Clock Divided By 2
RM0401 Basic timers (TIM6) Figure 160. Counter timing diagram, internal clock divided by 2 Figure 161. Counter timing diagram, internal clock divided by 4 RM0401 Rev 3 441/771...
Page 442: Figure 162. Counter Timing Diagram, Internal Clock Divided By N
Basic timers (TIM6) RM0401 Figure 162. Counter timing diagram, internal clock divided by N Figure 163. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded) 442/771 RM0401 Rev 3...
Page 443: Clock Source
RM0401 Basic timers (TIM6) Figure 164. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) 17.3.3 Clock source The counter clock is provided by the Internal clock (CK_INT) source. The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except for UG that remains cleared automatically).
Page 444: Debug Mode
Basic timers (TIM6) RM0401 Figure 165. Control circuit in normal mode, internal clock divided by 1 17.3.4 Debug mode ® When the microcontroller enters the debug mode (Cortex -M4 with FPU core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP configuration bit in the DBGMCU module.
Page 445: Tim6 Registers
RM0401 Basic timers (TIM6) 17.4 TIM6 registers Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in register descriptions. The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
Page 446: Tim6 Control Register 2 (Timx_Cr2)
Basic timers (TIM6) RM0401 17.4.2 TIM6 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. MMS[2:0] Res. Res. Res. Res. Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 MMS: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO).
Page 447: Tim6 Status Register (Timx_Sr)
RM0401 Basic timers (TIM6) 17.4.4 TIM6 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rc_w0 Bits 15:1 Reserved, must be kept at reset value. Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event.
Page 448: Tim6 Prescaler (Timx_Psc)
Basic timers (TIM6) RM0401 17.4.7 TIM6 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to f / (PSC[15:0] + 1). CK_PSC PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).
Page 449: Tim6 Register Map
RM0401 Basic timers (TIM6) 17.4.9 TIM6 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Table 70. TIM6 register map and reset values Offset Register TIMx_CR1 0x00 Reset value TIMx_CR2 MMS[2:0] 0x04 Reset value 0x08 Res.
Page 450: Low-Power Timer (Lptim)
Configurable output: Pulse, PWM • Configurable I/O polarity • Encoder mode 18.3 LPTIM implementation Table 71 describes LPTIM implementation on STM32F410 devices. Table 71. STM32F410 LPTIM features LPTIM modes/features LPTIM1 Encoder mode 1. X = supported. 450/771 RM0401 Rev 3...
Page 451: Lptim Functional Description
RM0401 Low-power timer (LPTIM) 18.4 LPTIM functional description 18.4.1 LPTIM block diagram Figure 166. Low-power timer block diagram 18.4.2 LPTIM trigger mapping The LPTIM external trigger connections are detailed hereafter: Table 72. LPTIM1 external trigger connection TRIGSEL External trigger lptim_ext_trig0 PB6 or PC3 input on AF1 lptim_ext_trig1 RTC alarm A output signal...
Page 452: Lptim Input1 Multiplexing
Low-power timer (LPTIM) RM0401 Table 72. LPTIM1 external trigger connection (continued) TRIGSEL External trigger lptim_ext_trig6 Reserved lptim_ext_trig7 Reserved 18.4.3 LPTIM input1 multiplexing Various inputs can be selected for LPTIM1 input 1 through the LPTMI option register (LPTIM1_OR). This input can either be connected to the pads selected by the LPTIM alternate function (AF1) or directly connected internally to PA4, PB9 pad or to TIM6/DAC trigger.
Page 453: Prescaler
RM0401 Low-power timer (LPTIM) The digital filters are divided into two groups: • The first group of digital filters protects the LPTIM external inputs. The digital filters sensitivity is controlled by the CKFLT bits • The second group of digital filters protects the LPTIM internal trigger inputs. The digital filters sensitivity is controlled by the TRGFLT bits.
Page 454: Trigger Multiplexer
Low-power timer (LPTIM) RM0401 18.4.7 Trigger multiplexer The LPTIM counter may be started either by software or after the detection of an active edge on one of the 8 trigger inputs. TRIGEN[1:0] is used to determine the LPTIM trigger source: •...
Page 455: Figure 168. Lptim Output Waveform, Single Counting Mode Configuration
RM0401 Low-power timer (LPTIM) Figure 168. LPTIM output waveform, single counting mode configuration - Set-once mode activated: It should be noted that when the WAVE bit-field in the LPTIM_CFGR register is set, the Set- once mode is activated. In this case, the counter is only started once following the first trigger, and any subsequent trigger event is discarded as shown in Figure 169.
Page 456: Timeout Function
Low-power timer (LPTIM) RM0401 Figure 170. LPTIM output waveform, Continuous counting mode configuration SNGSTRT and CNTSTRT bits can only be set when the timer is enabled (The ENABLE bit is set to ‘1’). It is possible to change “on the fly” from One-shot mode to Continuous mode. If the Continuous mode was previously selected, setting SNGSTRT will switch the LPTIM to the One-shot mode.
Page 457: Register Update
RM0401 Low-power timer (LPTIM) The LPTIM output waveform can be configured through the WAVE bit as follow: • Resetting the WAVE bit to ‘0’ forces the LPTIM to generate either a PWM waveform or a One pulse waveform depending on which bit is set: CNTSTRT or SNGSTRT. •...
Page 458: Counter Mode
Low-power timer (LPTIM) RM0401 counter comparator. Within this latency period, any additional write into these registers must be avoided. The ARROK flag and the CMPOK flag in the LPTIM_ISR register indicate when the write operation is completed to respectively the LPTIM_ARR register and the LPTIM_CMP register.
Page 459: Encoder Mode
RM0401 Low-power timer (LPTIM) The LPTIM_CFGR and LPTIM_IER registers must be modified only when the LPTIM is disabled. 18.4.14 Encoder mode This mode allows handling signals from quadrature encoders used to detect angular position of rotary elements. Encoder interface mode acts simply as an external clock with direction selection.
Page 460: Debug Mode
Low-power timer (LPTIM) RM0401 Figure 172. Encoder mode counting sequence 18.4.15 Debug mode When the microcontroller enters debug mode (core halted), the LPTIM counter either continues to work normally or stops, depending on the DBG_LPTIM_STOP configuration bit in the DBGMCU module. 18.5 LPTIM low-power modes Table 75.
Page 461: Lptim Interrupts
RM0401 Low-power timer (LPTIM) 18.6 LPTIM interrupts The following events generate an interrupt/wake-up event, if they are enabled through the LPTIM_IER register: • Compare match • Auto-reload match (whatever the direction if encoder mode) • External trigger event • Autoreload register write completed •...
Page 462 Low-power timer (LPTIM) RM0401 Bits 31:22 Reserved, must be kept at reset value. Bit 21 Reserved, must be kept at reset value. Bit 20 Reserved, must be kept at reset value. Bit 19 Reserved, must be kept at reset value. Bits 18:16 Reserved, must be kept at reset value.
Page 463: Lptim Interrupt Clear Register (Lptim_Icr)
RM0401 Low-power timer (LPTIM) 18.7.2 LPTIM interrupt clear register (LPTIM_ICR) Address offset: 0x004 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DOWN ARRO CMPO EXTTR ARRM CMPM Res. Res.
Page 464: Lptim Interrupt Enable Register (Lptim_Ier)
Low-power timer (LPTIM) RM0401 Bit 2 EXTTRIGCF: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register Bit 1 ARRMCF: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register Bit 0 CMPMCF: Compare match clear flag Writing 1 to this bit clears the CMP flag in the LPTIM_ISR register 18.7.3...
Page 465: Lptim Configuration Register (Lptim_Cfgr)
RM0401 Low-power timer (LPTIM) Bit 6 DOWNIE: Direction change to down Interrupt Enable DOWN interrupt disabled DOWN interrupt enabled Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to Section 18.3: LPTIM implementation. Bit 5 UPIE: Direction change to UP Interrupt Enable UP interrupt disabled UP interrupt enabled...
Page 466 Low-power timer (LPTIM) RM0401 Bit 24 ENC: Encoder mode enable The ENC bit controls the Encoder mode 0: Encoder mode disabled 1: Encoder mode enabled Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to Section 18.3: LPTIM implementation.
Page 467 RM0401 Low-power timer (LPTIM) Bits 15:13 TRIGSEL[2:0]: Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: 000: lptim_ext_trig0 001: lptim_ext_trig1 010: lptim_ext_trig2 011: lptim_ext_trig3 100: lptim_ext_trig4 101: lptim_ext_trig5 110: lptim_ext_trig6...
Page 468: Lptim Control Register (Lptim_Cr)
Low-power timer (LPTIM) RM0401 Bits 4:3 CKFLT[1:0]: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any external clock signal level change is considered as a valid transition 01: external clock signal level change must be stable for at least 2 clock periods before it is...
Page 469: Lptim Compare Register (Lptim_Cmp)
RM0401 Low-power timer (LPTIM) Bits 31:3 Reserved, must be kept at reset value. Bit 2 CNTSTRT: Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected.
Page 470: Lptim Autoreload Register (Lptim_Arr)
Low-power timer (LPTIM) RM0401 18.7.7 LPTIM autoreload register (LPTIM_ARR) Address offset: 0x018 Reset value: 0x0000 0001 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ARR[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 ARR[15:0]: Auto reload value ARR is the autoreload value for the LPTIM.
Page 471: Lptim1 Option Register (Lptim1_Or)
RM0401 Low-power timer (LPTIM) 18.7.9 LPTIM1 option register (LPTIM1_OR) Address offset: 0x020 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 472: Lptim Register Map
Low-power timer (LPTIM) RM0401 18.7.10 LPTIM register map The following table summarizes the LPTIM registers. Table 77. LPTIM register map and reset values Offset Register name LPTIM_ISR 0x000 0 0 0 0 0 0 0 Reset value LPTIM_ICR 0x004 0 0 0 0 0 0 0 Reset value LPTIM_IER 0x008...
Page 473: Window Watchdog (Wwdg)
RM0401 Window watchdog (WWDG) Window watchdog (WWDG) 19.1 WWDG introduction The window watchdog is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the contents of the downcounter before the T6 bit becomes cleared.
Page 474: Figure 173. Watchdog Block Diagram
Window watchdog (WWDG) RM0401 Figure 173. Watchdog block diagram The application program must write in the WWDG_CR register at regular intervals during normal operation to prevent an MCU reset. This operation must occur only when the counter value is lower than the window register value. The value to be stored in the WWDG_CR register must be between 0xFF and 0xC0.
Page 475: How To Program The Watchdog Timeout
RM0401 Window watchdog (WWDG) In some applications, the EWI interrupt can be used to manage a software system check and/or system recovery/graceful degradation, without generating a WWDG reset. In this case, the corresponding interrupt service routine (ISR) should reload the WWDG counter to avoid the WWDG reset, then trigger the required actions.
Page 476: Debug Mode
Window watchdog (WWDG) RM0401 As an example, let us assume APB1 frequency is equal to 24 MHz, WDGTB[1:0] is set to 3 and T[5:0] is set to 63: ⁄ × × × t WWDG 24000 4096 21.85 ms Refer to the datasheets for the minimum and maximum values of the t WWDG.
Page 477: Wwdg Registers
RM0401 Window watchdog (WWDG) 19.6 WWDG registers Refer to for a list of abbreviations used in register descriptions. Section 1.2 on page 34 The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). 19.6.1 Control register (WWDG_CR) Address offset: 0x00 Reset value: 0x0000 007F Res.
Page 478: Configuration Register (Wwdg_Cfr)
Window watchdog (WWDG) RM0401 19.6.2 Configuration register (WWDG_CFR) Address offset: 0x04 Reset value: 0x0000 007F Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WDGTB[1:0] W[6:0] Bits 31:10 Reserved, must be kept at reset value. Bit 9 EWI: Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40.
Page 479: Wwdg Register Map
RM0401 Window watchdog (WWDG) 19.6.4 WWDG register map The following table gives the WWDG register map and reset values. Table 78. WWDG register map and reset values Offset Register WWDG_CR T[6:0] 0x00 Reset value WWDG_CFR W[6:0] 0x04 Reset value WWDG_SR 0x08 Reset value Refer to...
Page 480: Independent Watchdog (Iwdg)
Independent watchdog (IWDG) RM0401 Independent watchdog (IWDG) 20.1 IWDG introduction The devices feature two embedded watchdog peripherals that offer a combination of high safety level, timing accuracy and flexibility of use. Both watchdog peripherals (Independent and Window) serve to detect and resolve malfunctions due to software failure, and to trigger system reset or an interrupt (window watchdog only) when the counter reaches a given timeout value.
Page 481: Debug Mode
RM0401 Independent watchdog (IWDG) A status register is available to indicate that an update of the prescaler or the down-counter reload value is on going. 20.3.3 Debug mode ® When the microcontroller enters debug mode (Cortex -M4 with FPU core halted), the IWDG counter either continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in DBGMCU module.
Page 482: Iwdg Registers
Independent watchdog (IWDG) RM0401 20.4 IWDG registers Refer to Section 1.2 on page 34 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). 20.4.1 Key register (IWDG_KR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by Standby mode) Res.
Page 483: Prescaler Register (Iwdg_Pr)
RM0401 Independent watchdog (IWDG) 20.4.2 Prescaler register (IWDG_PR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 484: Reload Register (Iwdg_Rlr)
Independent watchdog (IWDG) RM0401 20.4.3 Reload register (IWDG_RLR) Address offset: 0x08 Reset value: 0x0000 0FFF (reset by Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RL[11:0] Bits 31:12 Reserved, must be kept at reset value.
Page 485: Iwdg Register Map
RM0401 Independent watchdog (IWDG) Note: If several reload values or prescaler values are used by application, it is mandatory to wait until RVU bit is reset before changing the reload value and to wait until PVU bit is reset before changing the prescaler value. However, after updating the prescaler and/or the reload value it is not necessary to wait until RVU or PVU is reset before continuing code execution (even in case of low-power mode entry, the write operation is taken into account and will complete)
Page 486: Real-Time Clock (Rtc)
Real-time clock (RTC) RM0401 Real-time clock (RTC) 21.1 Introduction The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-of-day clock/calendar, two programmable alarm interrupts, and a periodic programmable wakeup flag with interrupt capability. The RTC also includes an automatic wakeup unit to manage low power modes.
Page 487: Figure 176. Rtc Block Diagram
RM0401 Real-time clock (RTC) – 0.95 ppm accuracy, obtained in a calibration window of several seconds • Timestamp function for event saving (1 event) • Tamper detection: – 2 tamper events with configurable filter and internal pull-up. • 20 backup registers (80 bytes). The backup registers are reset when a tamper detection event occurs.
Page 488: Rtc Functional Description
Real-time clock (RTC) RM0401 21.3 RTC functional description 21.3.1 Clock and prescalers The RTC clock source (RTCCLK) is selected through the clock controller among the LSE clock, the LSI oscillator clock, and the HSE clock. For more information on the RTC clock source configuration, refer to Section 6: Reset and clock control (RCC).
Page 489: Programmable Alarms
RM0401 Real-time clock (RTC) Every two RTCCLK periods, the current calendar value is copied into the shadow registers, and the RSF bit of RTC_ISR register is set (see Section 21.6.4). The copy is not performed in Stop and Standby mode. When exiting these modes, the shadow registers are updated after up to two RTCCLK periods.
Page 490: Rtc Initialization And Configuration
Real-time clock (RTC) RM0401 complete (see Programming the wakeup timer), the timer starts counting down.When the wakeup function is enabled, the down-counting remains active in low power modes. In addition, when it reaches 0, the WUTF flag is set in the RTC_ISR register, and the wakeup counter is automatically reloaded with its reload value (RTC_WUTR register value).
Page 491 RM0401 Real-time clock (RTC) factor. Even if only one of the two fields needs to be changed, 2 separate write accesses must be performed to the RTC_PRER register. Load the initial time and date values in the shadow registers (RTC_TR and RTC_DR), and configure the time format (12 or 24 hours) through the FMT bit in the RTC_CR register.
Page 492: Reading The Calendar
Real-time clock (RTC) RM0401 21.3.6 Reading the calendar BYPSHAD control bit is cleared in the RTC_CR register When To read the RTC calendar registers (RTC_SSR, RTC_TR and RTC_DR) properly, the APB1 clock frequency (f ) must be equal to or greater than seven times the f PCLK1 RTCCLK clock frequency.
Page 493: Resetting The Rtc
RM0401 Real-time clock (RTC) 21.3.7 Resetting the RTC The calendar shadow registers (RTC_SSR, RTC_TR and RTC_DR) and some bits of the RTC status register (RTC_ISR) are reset to their default values by all available system reset sources. On the contrary, the following registers are resetted to their default values by a backup domain reset and are not affected by a system reset: the RTC current calendar registers, the RTC control register (RTC_CR), the prescaler register (RTC_PRER), the RTC calibration registers (RTC_CALIBR or RTC_CALR), the RTC shift register (RTC_SHIFTR),...
Page 494: Rtc Reference Clock Detection
Real-time clock (RTC) RM0401 21.3.9 RTC reference clock detection The RTC calendar update can be synchronized to a reference clock RTC_REFIN, usually the mains (50 or 60 Hz). The RTC_REFIN reference clock should have a higher precision than the 32.768 kHz LSE clock. When the RTC_REFIN detection is enabled (REFCKON bit of RTC_CR set to 1), the calendar is still clocked by the LSE, and RTC_REFIN is used to compensate for the imprecision of the calendar update frequency (1 Hz).
Page 495: Rtc Smooth Digital Calibration
RM0401 Real-time clock (RTC) When positive calibration is enabled (DCS = ‘0’), 2 ck_apre cycles are added every minute (around 15360 ck_apre cycles) for 2xDC minutes. This causes the calendar to be updated sooner, thereby adjusting the effective RTC frequency to be a bit higher. When negative calibration is enabled (DCS = ‘1’), 1 ck_apre cycle is removed every minute (around 15360 ck_apre cycles) for 2xDC minutes.
Page 496 Real-time clock (RTC) RM0401 The smooth calibration register (RTC_CALR) specifies the number of RTCCLK clock cycles to be masked during the 32-second cycle: • Setting the bit CALM[0] to 1 causes exactly one pulse to be masked during the 32- second cycle.
Page 497: Timestamp Function
RM0401 Real-time clock (RTC) Verifying the RTC calibration RTC precision is performed by measuring the precise frequency of RTCCLK and calculating the correct CALM value and CALP values. An optional 1 Hz output is provided to allow applications to measure and verify the RTC precision. Measuring the precise frequency of the RTC over a limited interval can result in a measurement error of up to 2 RTCCLK clock cycles over the measurement period, depending on how the digital calibration cycle is aligned with the measurement period.
Page 498: Tamper Detection
Real-time clock (RTC) RM0401 If a new timestamp event is detected while the timestamp flag (TSF) is already set, the timestamp overflow flag (TSOVF) flag is set and the timestamp registers (RTC_TSTR and RTC_TSDR) maintain the results of the previous event. Note: TSF is set 2 ck_apre cycles after the timestamp event occurs due to synchronization process.
Page 499: Calibration Clock Output
RM0401 Real-time clock (RTC) Edge detection on tamper inputs If the TAMPFLT bits are “00”, the TAMPER pins generate tamper detection events (RTC_TAMP[2:1]) when either a rising edge is observed or an falling edge is observed depending on the corresponding TAMPxTRG bit. The internal pull-up resistors on the TAMPER inputs are deactivated when edge detection is selected.
Page 500: Alarm Output
Real-time clock (RTC) RM0401 The RTC_CALIB output is not impacted by the calibration value programmed in RTC_CALIBR register. The RTC_CALIB duty cycle is irregular: there is a light jitter on falling edges. It is therefore recommended to use rising edges. If COSEL is set and “PREDIV_S+1”...
Page 501: Rtc Interrupts
RM0401 Real-time clock (RTC) 21.5 RTC interrupts All RTC interrupts are connected to the EXTI controller. To enable the RTC Alarm interrupt, the following sequence is required: Configure and enable the EXTI Line 17 in interrupt mode and select the rising edge sensitivity.
Page 502: Rtc Registers
Bits 14:12 MNT[2:0]: Minute tens in BCD format Bits 11:8 MNU[3:0]: Minute units in BCD format Bit 7 Reserved, must be kept at reset value. Bits 6:4 ST[2:0]: Second tens in BCD format Bits 3:0 SU[3:0]: Second units in BCD format Note: This register is write protected.
Page 503: Rtc Date Register (Rtc_Dr)
RM0401 Real-time clock (RTC) 21.6.2 RTC date register (RTC_DR) The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration Reading the calendar. Address offset: 0x04 Backup domain reset value: 0x0000_2101 System reset: 0x0000 2101 when BYPSHAD = 0.
Page 504: Rtc Control Register (Rtc_Cr)
Real-time clock (RTC) RM0401 21.6.3 RTC control register (RTC_CR) Address offset: 0x08 Backup domain reset value: 0x0000 0000 System reset: not affected Res. Res. Res. Res. Res. Res. Res. Res. OSEL[1:0] COSEL BKP SUB1H ADD1H TSIE WUTIE ALRBIE ALRAIE WUTE ALRBE ALRAE DCE FMT BYPSHAD REFCKON TSEDGE WUCKSEL[2:0] Bits 31:24 Reserved, must be kept at reset value.
Page 505 RM0401 Real-time clock (RTC) Bit 16 ADD1H: Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. 0: No effect 1: Adds 1 hour to the current time. This can be used for summer time change Bit 15 TSIE: Timestamp interrupt enable 0: Timestamp Interrupt disable 1: Timestamp Interrupt enable...
Page 506: Rtc Initialization And Status Register (Rtc_Isr)
Real-time clock (RTC) RM0401 Bit 4 REFCKON: Reference clock detection enable (50 or 60 Hz) 0: Reference clock detection disabled 1: Reference clock detection enabled Note: PREDIV_S must be 0x00FF. Bit 3 TSEDGE: Timestamp event active edge 0: TIMESTAMP rising edge generates a timestamp event 1: TIMESTAMP falling edge generates a timestamp event TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting Bits 2:0 WUCKSEL[2:0]: Wakeup clock selection...
Page 507 RM0401 Real-time clock (RTC) Bit 14 TAMP2F: TAMPER2 detection flag This flag is set by hardware when a tamper detection event is detected on tamper input 2. It is cleared by software writing 0. Bit 13 TAMP1F: Tamper detection flag This flag is set by hardware when a tamper detection event is detected.
Page 508: Rtc Prescaler Register (Rtc_Prer)
Real-time clock (RTC) RM0401 Bit 4 INITS: Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (backup domain reset value state). 0: Calendar has not been initialized 1: Calendar has been initialized Bit 3 SHPF: Shift operation pending 0: No shift operation is pending 1: A shift operation is pending...
Page 509: Rtc Wakeup Timer Register (Rtc_Wutr)
RM0401 Real-time clock (RTC) Bits 31:23 Reserved, must be kept at reset value Bits 22:16 PREDIV_A[6:0]: Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) Bit 15 Reserved, must be kept at reset value. Bits 14:0 PREDIV_S[14:0]: Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1) Note:...
Page 510 Real-time clock (RTC) RM0401 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DC[4:0] Bits 31:8 Reserved, must be kept at reset value Bit 7 DCS: Digital calibration sign 0: Positive calibration: calendar update frequency is increased 1: Negative calibration: calendar update frequency is decreased...
Page 511: Rtc Alarm A Register (Rtc_Alrmar)
Bit 7 MSK1: Alarm A seconds mask 0: Alarm A set if the seconds match 1: Seconds don’t care in Alarm A comparison Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. Note: This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization mode.
Page 512: Rtc Alarm B Register (Rtc_Alrmbr)
Bit 7 MSK1: Alarm B seconds mask 0: Alarm B set if the seconds match 1: Seconds don’t care in Alarm B comparison Bits 6:4 ST[2:0]: Second tens in BCD format Bits 3:0 SU[3:0]: Second units in BCD format Note: This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization mode.
Page 513: Rtc Write Protection Register (Rtc_Wpr)
RM0401 Real-time clock (RTC) 21.6.10 RTC write protection register (RTC_WPR) Address offset: 0x24 Backup domain reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 514: Rtc Shift Control Register (Rtc_Shiftr)
Real-time clock (RTC) RM0401 21.6.12 RTC shift control register (RTC_SHIFTR) Address offset: 0x2C Backup domain reset value: 0x0000 0000 System reset: not affected ADD1S Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SUBFS[14:0] Bit 31 ADD1S: Add one second 0: No effect...
Page 515: Rtc Time Stamp Time Register (Rtc_Tstr)
Bits 14:12 MNT[2:0]: Minute tens in BCD format. Bits 11:8 MNU[3:0]: Minute units in BCD format. Bit 7 Reserved, must be kept at reset value. Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. Note: The content of this register is valid only when TSF is set to 1 in RTC_ISR.
Page 516: Rtc Timestamp Sub Second Register (Rtc_Tsssr)
Real-time clock (RTC) RM0401 Bits 31:16 Reserved, must be kept at reset value. Bits 15:13 WDU[1:0]: Week day units Bit 12 MT: Month tens in BCD format Bits 11:8 MU[3:0]: Month units in BCD format Bits 7:6 Reserved, must be kept at reset value. Bits 5:4 DT[1:0]: Date tens in BCD format Bits 3:0 DU[3:0]: Date units in BCD format Note:...
Page 517: Rtc Tamper And Alternate Function Configuration Register
RM0401 Real-time clock (RTC) Bits 31:16 Reserved, must be kept at reset value Bit 15 CALP: Increase frequency of RTC by 488.5 ppm 0: No RTCCLK pulses are added. 1: One RTCCLK pulse is effectively inserted every 2 pulses (frequency increased by 488.5 ppm).
Page 518 Real-time clock (RTC) RM0401 Bits 31:19 Reserved, must be kept at reset value. Always read as 0. Bit 18 ALARMOUTTYPE: RTC_ALARM output type 0: RTC_ALARM is an open-drain output 1: RTC_ALARM is a push-pull output Bit 17 TSINSEL: TIMESTAMP mapping 0: RTC_AF1 used as TIMESTAMP 1: Reserved Bit 16 TAMP1INSEL: TAMPER1 mapping...
Page 519: Rtc Alarm A Sub Second Register (Rtc_Alrmassr)
RM0401 Real-time clock (RTC) Bits 6:5 Reserved. Always read as 0. Bit 4 TAMP2TRG: Active level for tamper 2 if TAMPFLT != 00 0: TAMPER2 staying low triggers a tamper detection event. 1: TAMPER2 staying high triggers a tamper detection event. if TAMPFLT = 00: 0: TAMPER2 rising edge triggers a tamper detection event.
Page 520: Rtc Alarm B Sub Second Register (Rtc_Alrmbssr)
Real-time clock (RTC) RM0401 Bits 31:28 Reserved, must be kept at reset value Bits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit 0: No comparison on sub seconds for Alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match).
Page 521: Rtc Backup Registers (Rtc_Bkpxr)
RM0401 Real-time clock (RTC) Bits 31:28 Reserved, must be kept at reset value Bits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit 0x0: No comparison on sub seconds for Alarm B. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match).
Page 522: Rtc Register Map
Real-time clock (RTC) RM0401 21.6.21 RTC register map Table 83. RTC register map and reset values Offset Register RTC_TR HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0] [1:0] 0x00 Reset value RTC_DR YT[3:0] YU[3:0] WDU[2:0] MU[3:0] DU[3:0] [1:0] 0x04 Reset value WCKSEL OSEL...
Page 523 RM0401 Real-time clock (RTC) Table 83. RTC register map and reset values (continued) Offset Register RTC_TSTR HU[3:0] MNU[3:0] ST[2:0] SU[3:0] 0x30 Reset value RTC_TSSSR SS[15:0] 0x38 Reset value RTC_ CALR CALM[8:0] 0x3C Reset value RTC_TAFCR 0x40 Reset value RTC_ MASKSS[3:0]...
Page 524: Fast-Mode Plus Inter-Integrated Circuit (Fmpi2C) Interface
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 22.1 Introduction The I C (inter-integrated circuit) bus interface handles communications between the microcontroller and the serial I C bus. It provides multimaster capability, and controls all I bus-specific sequencing, protocol, arbitration and timing.
Page 525: Fmpi2C Implementation
Independent clock: a choice of independent clock sources allowing the FMPI2C communication speed to be independent from the PCLK reprogramming 22.3 FMPI2C implementation This manual describes the full set of features implemented in FMPI2C1 Table 84. STM32F410 FMPI2C implementation I2C features I2C4 7-bit addressing mode 10-bit addressing mode...
Page 526: Fmpi2C Block Diagram
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 22.4.1 FMPI2C block diagram The block diagram of the FMPI2C interface is shown in Figure 177. Figure 177. FMPI2C block diagram The FMPI2C is clocked by an independent clock source which allows to the FMPI2C to operate independently from the PCLK frequency.
Page 527: Fmpi2C Pins And Internal Signals
RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 22.4.2 FMPI2C pins and internal signals Table 85. FMPI2C input/output pins Pin name Signal type Description I2C_SDA Bidirectional I2C data I2C_SCL Bidirectional I2C clock I2C_SMBA Bidirectional SMBus Alert Table 86. FMPI2C internal input/output signals Internal signal name Signal type Description...
Page 528: Mode Selection
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 22.4.4 Mode selection The interface can operate in one of the four following modes: • Slave transmitter • Slave receiver • Master transmitter • Master receiver By default, it operates in slave mode. The interface automatically switches from slave to master when it generates a START condition, and from master to slave if an arbitration loss or a STOP generation occurs, allowing multimaster capability.
Page 529: Table 87. Comparison Of Analog Vs. Digital Filters
RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface When the FMPI2C is disabled (PE=0), the I C performs a software reset. Refer to Section 22.4.6: Software reset for more details. Noise filters Before enabling the FMPI2C peripheral by setting the PE bit in FMPI2C_CR1 register, the user must configure the noise filters, if needed.
Page 530: Figure 179. Setup And Hold Timings
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 FMPI2C timings The timings must be configured in order to guarantee a correct data hold and setup time, used in master and slave modes. This is done by programming the PRESC[3:0], SCLDEL[3:0] and SDADEL[3:0] bits in the FMPI2C_TIMINGR register. The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C configuration window Figure 179.
Page 531: Table 88. I2C-Smbus Specification Data Setup And Hold Times
RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface • When the SCL falling edge is internally detected, a delay is inserted before sending SDA output. This delay is where = SDADEL x t = (PRESC+1) SDADEL PRESC I2CCLK PRESC I2CCLK impacts the hold time SDADEL HD;DAT.
Page 532 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 The SDA and SCL transition time values to be used are the ones in the application. Using the maximum values from the standard increases the constraints for the SDADEL and SCLDEL calculation, but ensures the feature whatever the application. Note: At every clock pulse, after SCL falling edge detection, the I2C master or slave stretches SCL low during at least [(SDADEL+SCLDEL+1) x (PRESC+1) + 1] x t...
Page 533: Software Reset
RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 180. FMPI2C initialization flowchart 22.4.6 Software reset A software reset can be performed by clearing the PE bit in the FMPI2C_CR1 register. In that case FMPI2C lines SCL and SDA are released. Internal states machines are reset and communication control bits, as well as status bits come back to their reset value.
Page 534: Data Transfer
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 22.4.7 Data transfer The data transfer is managed through transmit and receive data registers and a shift register. Reception The SDA input fills the shift register. After the 8th SCL pulse (when the complete data byte is received), the shift register is copied into FMPI2C_RXDR register if it is empty (RXNE=0).
Page 535: Figure 182. Data Transmission
RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Transmission If the FMPI2C_TXDR register is not empty (TXE=0), its content is copied into the shift register after the 9th SCL pulse (the Acknowledge pulse). Then the shift register content is shifted out on SDA line. If TXE=1, meaning that no data is written yet in FMPI2C_TXDR, SCL line is stretched low until FMPI2C_TXDR is written.
Page 536: Fmpi2C Slave Mode
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 When RELOAD=0 in master mode, the counter can be used in 2 modes: • Automatic end mode (AUTOEND = ‘1’ in the FMPI2C_CR2 register). In this mode, the master automatically sends a STOP condition once the number of bytes programmed in the NBYTES[7:0] bit field has been transferred.
Page 537 RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface By default, the slave uses its clock stretching capability, which means that it stretches the SCL signal at low level when needed, in order to perform software actions. If the master does not support clock stretching, the FMPI2C must be configured with NOSTRETCH=1 in the FMPI2C_CR1 register.
Page 538: Figure 183. Slave Initialization Flowchart
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 Slave Byte Control mode In order to allow byte ACK control in slave reception mode, Slave Byte Control mode must be enabled by setting the SBC bit in the FMPI2C_CR1 register. This is required to be compliant with SMBus standards.
Page 539 RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Slave transmitter A transmit interrupt status (TXIS) is generated when the FMPI2C_TXDR register becomes empty. An interrupt is generated if the TXIE bit is set in the FMPI2C_CR1 register. The TXIS bit is cleared when the FMPI2C_TXDR register is written with the next data byte to be transmitted.
Page 540: Figure 184. Transfer Sequence Flowchart For Fmpi2C Slave Transmitter
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 Figure 184. Transfer sequence flowchart for FMPI2C slave transmitter, NOSTRETCH= 0 540/771 RM0401 Rev 3...
Page 541: Figure 185. Transfer Sequence Flowchart For Fmpi2C Slave Transmitter
RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 185. Transfer sequence flowchart for FMPI2C slave transmitter, NOSTRETCH= 1 RM0401 Rev 3 541/771...
Page 542: Figure 186. Transfer Bus Diagrams For Fmpi2C Slave Transmitter
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 Figure 186. Transfer bus diagrams for FMPI2C slave transmitter 542/771 RM0401 Rev 3...
Page 543: Figure 187. Transfer Sequence Flowchart For Slave Receiver With Nostretch=0
RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Slave receiver RXNE is set in FMPI2C_ISR when the FMPI2C_RXDR is full, and generates an interrupt if RXIE is set in FMPI2C_CR1. RXNE is cleared when FMPI2C_RXDR is read. When a STOP is received and STOPIE is set in FMPI2C_CR1, STOPF is set in FMPI2C_ISR and an interrupt is generated.
Page 544: Figure 188. Transfer Sequence Flowchart For Slave Receiver With Nostretch=1
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 Figure 188. Transfer sequence flowchart for slave receiver with NOSTRETCH=1 Figure 189. Transfer bus diagrams for FMPI2C slave receiver 544/771 RM0401 Rev 3...
Page 545: Fmpi2C Master Mode
RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 22.4.9 FMPI2C master mode FMPI2C master initialization Before enabling the peripheral, the FMPI2C master clock must be configured by setting the SCLH and SCLL bits in the FMPI2C_TIMINGR register. The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C Configuration window.
Page 546: Figure 190. Master Clock Generation
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 Figure 190. Master clock generation Caution: In order to be I C or SMBus compliant, the master clock must respect the timings given below: 546/771 RM0401 Rev 3...
Page 547: Table 90. I2C-Smbus Specification Clock Timings
RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Table 90. I C-SMBUS specification clock timings Standard- Fast-mode Fast-mode SMBUS mode (Sm) (Fm) Plus (Fm+) Symbol Parameter Unit SCL clock frequency 1000 Hold time (repeated) START condition 0.26 µs HD:STA Set-up time for a repeated START 0.26 µs SU:STA...
Page 548: Figure 191. Master Initialization Flowchart
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 master re-launches automatically the slave address transmission until ACK is received. In this case ADDRCF must be set if a NACK is received from the slave, in order to stop sending the slave address. If the FMPI2C is addressed as a slave (ADDR=1) while the START bit is set, the FMPI2C switches to slave mode and the START bit is cleared, when the ADDRCF bit is set.
Page 549: Figure 193. 10-Bit Address Read Access With Head10R=1
RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface • If the master addresses a 10-bit address slave, transmits data to this slave and then reads data from the same slave, a master transmission flow must be done first. Then a repeated start is set with the 10 bit slave address configured with HEAD10R=1. In this case the master sends this sequence: ReStart + Slave address 10-bit header Read.
Page 550: Figure 194. Transfer Sequence Flowchart For Fmpi2C Master Transmitter For N≤255 Bytes
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 Figure 194. Transfer sequence flowchart for FMPI2C master transmitter for N≤255 bytes 550/771 RM0401 Rev 3...
Page 551: Figure 195. Transfer Sequence Flowchart For Fmpi2C Master Transmitter For N>255 Bytes
RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 195. Transfer sequence flowchart for FMPI2C master transmitter for N>255 bytes RM0401 Rev 3 551/771...
Page 552: Figure 196. Transfer Bus Diagrams For Fmpi2C Master Transmitter
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 Figure 196. Transfer bus diagrams for FMPI2C master transmitter 552/771 RM0401 Rev 3...
Page 553 RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Master receiver In the case of a read transfer, the RXNE flag is set after each byte reception, after the 8th SCL pulse. An RXNE event generates an interrupt if the RXIE bit is set in the FMPI2C_CR1 register.
Page 554: Figure 197. Transfer Sequence Flowchart For Fmpi2C Master Receiver For N≤255 Bytes
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 Figure 197. Transfer sequence flowchart for FMPI2C master receiver for N≤255 bytes 554/771 RM0401 Rev 3...
Page 555: Figure 198. Transfer Sequence Flowchart For Fmpi2C Master Receiver For N >255 Bytes
RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 198. Transfer sequence flowchart for FMPI2C master receiver for N >255 bytes RM0401 Rev 3 555/771...
Page 556: Figure 199. Transfer Bus Diagrams For Fmpi2C Master Receiver
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 Figure 199. Transfer bus diagrams for FMPI2C master receiver 556/771 RM0401 Rev 3...
Page 557: Fmpi2C_Timingr Register Configuration Examples
RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 22.4.10 FMPI2C_TIMINGR register configuration examples The tables below provide examples of how to program the FMPI2C_TIMINGR to obtain timings compliant with the I C specification. In order to get more accurate configuration values, the STM32CubeMX tool (I2C Configuration window) must be used. Table 91.
Page 558: Smbus Specific Features
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 2. t minimum value is 4 x t = 250 ns. Example with t = 1000 ns. SYNC1 + SYNC2 I2CCLK SYNC1 + SYNC2 minimum value is 4 x t = 250 ns. Example with t = 750 ns.
Page 559 RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Received Command and Data acknowledge control A SMBus receiver must be able to NACK each received command or data. In order to allow the ACK control in slave mode, the Slave Byte Control mode must be enabled by setting SBC bit in FMPI2C_CR1 register.
Page 560: Table 93. Smbus Timeout Specifications
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 Timeouts This peripheral embeds hardware timers in order to be compliant with the 3 timeouts defined in SMBus specification. Table 93. SMBus timeout specifications Limits Symbol Parameter Unit Detect clock low timeout TIMEOUT Cumulative clock low extend time (slave device) LOW:SEXT Cumulative clock low extend time (master device)
Page 561: Smbus Initialization
RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Bus idle detection A master can assume that the bus is free if it detects that the clock and data signals have been high for t greater than t . (refer to Table 88: I2C-SMBUS specification data IDLE HIGH setup and hold...
Page 562: Table 94. Smbus With Pec Configuration
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 Table 94. SMBUS with PEC configuration Mode SBC bit RELOAD bit AUTOEND bit PECBYTE bit Master Tx/Rx NBYTES + PEC+ STOP Master Tx/Rx NBYTES + PEC + ReSTART Slave Tx/Rx with PEC Timeout detection The timeout detection is enabled by setting the TIMOUTEN and TEXTEN bits in the FMPI2C_TIMEOUTR register.
Page 563: Smbus: Fmpi2C_Timeoutr Register Configuration Examples
RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Refer to Table 97: Examples of TIMEOUTA settings for various FMPI2CCLK frequencies (max tIDLE = 50 µs) Caution: Changing the TIMEOUTA and TIDLE configuration is not allowed when the TIMEOUTEN is set. SMBus: 22.4.13 FMPI2C_TIMEOUTR register configuration examples This section is relevant only when SMBus feature is supported.
Page 564: Figure 201. Transfer Sequence Flowchart For Smbus Slave Transmitter N Bytes + Pec
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 FMPI2C_PECR register is automatically transmitted if the master requests an extra byte after the NBYTES-1 data transfer. Caution: The PECBYTE bit has no effect when the RELOAD bit is set. Figure 201. Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC 564/771 RM0401 Rev 3...
Page 565: Figure 202. Transfer Bus Diagrams For Smbus Slave Transmitter (Sbc=1)
RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 202. Transfer bus diagrams for SMBus slave transmitter (SBC=1) SMBus Slave receiver When the FMPI2C is used in SMBus mode, SBC must be programmed to ‘1’ in order to allow the PEC checking at the end of the programmed number of data bytes. In order to allow the ACK control of each byte, the reload mode must be selected (RELOAD=1).
Page 566: Figure 203. Transfer Sequence Flowchart For Smbus Slave Receiver N Bytes + Pec
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 Figure 203. Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC 566/771 RM0401 Rev 3...
Page 567: Figure 204. Bus Transfer Diagrams For Smbus Slave Receiver (Sbc=1)
RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 204. Bus transfer diagrams for SMBus slave receiver (SBC=1) This section is relevant only when SMBus feature is supported. Refer to Section 22.3: FMPI2C implementation. In addition to FMPI2C master transfer management (refer to Section 22.4.9: FMPI2C master mode) some additional software flowcharts are provided to support SMBus.
Page 568: Figure 205. Bus Transfer Diagrams For Smbus Master Transmitter
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 When the SMBus master wants to send a RESTART condition after the PEC, software mode must be selected (AUTOEND=0). In this case, once NBYTES-1 have been transmitted, the FMPI2C_PECR register content is transmitted and the TC flag is set after the PEC transmission, stretching the SCL line low.
Page 569 RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface SMBus Master receiver When the SMBus master wants to receive the PEC followed by a STOP at the end of the transfer, automatic end mode can be selected (AUTOEND=1). The PECBYTE bit must be set and the slave address must be programmed, before setting the START bit.
Page 570: Error Conditions
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 Figure 206. Bus transfer diagrams for SMBus master receiver 22.4.15 Error conditions The following are the error conditions which may cause communication to fail. Bus error (BERR) A bus error is detected when a START or a STOP condition is detected and is not located after a multiple of 9 SCL clock pulses.
Page 571 RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface In case of a misplaced START or RESTART detection in slave mode, the FMPI2C enters address recognition state like for a correct START condition. When a bus error is detected, the BERR flag is set in the FMPI2C_ISR register, and an interrupt is generated if the ERRIE bit is set in the FMPI2C_CR1 register.
Page 572: Dma Requests
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 Timeout Error (TIMEOUT) This section is relevant only when the SMBus feature is supported. Refer to Section 22.3: FMPI2C implementation. A timeout error occurs for any of these conditions: • TIDLE=0 and SCL remained low for the time defined in the TIMEOUTA[11:0] bits: this is used to detect a SMBus timeout.
Page 573: Debug Mode
RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface NBYTES counter. Refer to Master transmitter on page 549. • In slave mode: – With NOSTRETCH=0, when all data are transferred using DMA, the DMA must be initialized before the address match event, or in ADDR interrupt subroutine, before clearing ADDR.
Page 574: Fmpi2C Interrupts
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 22.6 FMPI2C interrupts The table below gives the list of FMPI2C interrupt requests. Table 99. FMPI2C Interrupt requests Exit the Exit the Exit the Interrupt Interrupt Event Enable Interrupt clear Sleep Stop Standby acronym event flag...
Page 575: Fmpi2C Registers
RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 22.7 FMPI2C registers Refer to Section 1.2 on page 34 for a list of abbreviations used in register descriptions. The peripheral registers are accessed by words (32-bit). 22.7.1 FMPI2C control register 1 (FMPI2C_CR1) Address offset: 0x00 Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is...
Page 576 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 Bit 20 SMBHEN: SMBus Host address enable 0: Host address disabled. Address 0b0001000x is NACKed. 1: Host address enabled. Address 0b0001000x is ACKed. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to Section 22.3: FMPI2C implementation.
Page 577 RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Bit 7 ERRIE: Error interrupts enable 0: Error detection interrupts disabled 1: Error detection interrupts enabled Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT)
Page 578: Fmpi2C Control Register 2 (Fmpi2C_Cr2)
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 22.7.2 FMPI2C control register 2 (FMPI2C_CR2) Address offset: 0x04 Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed.
Page 579 RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Bit 15 NACK: NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. 0: an ACK is sent after current received byte.
Page 580 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 Bits 9:8 SADD[9:8]: Slave address bit 9:8 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits are don’t care In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 9:8 of the slave address to be sent Note: Changing these bits when the START bit is set is not allowed.
Page 581: Fmpi2C Own Address 1 Register (Fmpi2C_Oar1)
RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 22.7.3 FMPI2C own address 1 register (FMPI2C_OAR1) Address offset: 0x08 Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed.
Page 582: Fmpi2C Own Address 2 Register (Fmpi2C_Oar2)
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 22.7.4 FMPI2C own address 2 register (FMPI2C_OAR2) Address offset: 0x0C Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed.
Page 583: Fmpi2C Timing Register (Fmpi2C_Timingr)
RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 22.7.5 FMPI2C timing register (FMPI2C_TIMINGR) Address offset: 0x10 Reset value: 0x0000 0000 Access: No wait states PRESC[3:0] Res. Res. Res. Res. SCLDEL[3:0] SDADEL[3:0] SCLH[7:0] SCLL[7:0] Bits 31:28 PRESC[3:0]: Timing prescaler This field is used to prescale FMPI2CCLK in order to generate the clock period t used PRESC for data setup and hold counters (refer to...
Page 584: Fmpi2C Timeout Register (Fmpi2C_Timeoutr)
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 22.7.6 FMPI2C timeout register (FMPI2C_TIMEOUTR) Address offset: 0x14 Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed.
Page 585: Fmpi2C Interrupt And Status Register (Fmpi2C_Isr)
RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 22.7.7 FMPI2C interrupt and status register (FMPI2C_ISR) Address offset: 0x18 Reset value: 0x0000 0001 Access: No wait states Res. Res. Res. Res. Res. Res. Res. Res. ADDCODE[6:0] TIME BUSY Res. ALERT ARLO BERR STOPF NACKF ADDR RXNE TXIS...
Page 586 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 Bit 11 PECERR: PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit.
Page 587: Fmpi2C Interrupt Clear Register (Fmpi2C_Icr)
RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Bit 2 RXNE: Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the FMPI2C_RXDR register, and is ready to be read. It is cleared when FMPI2C_RXDR is read. Note: This bit is cleared by hardware when PE=0.
Page 588: Fmpi2C Pec Register (Fmpi2C_Pecr)
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 Bit 10 OVRCF: Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the FMPI2C_ISR register. Bit 9 ARLOCF: Arbitration lost flag clear Writing 1 to this bit clears the ARLO flag in the FMPI2C_ISR register. Bit 8 BERRCF: Bus error flag clear Writing 1 to this bit clears the BERRF flag in the FMPI2C_ISR register.
Page 589: Fmpi2C Receive Data Register (Fmpi2C_Rxdr)
RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 22.7.10 FMPI2C receive data register (FMPI2C_RXDR) Address offset: 0x24 Reset value: 0x0000 0000 Access: No wait states Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 590: Fmpi2C Register Map
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0401 22.7.12 FMPI2C register map The table below provides the FMPI2C register map and reset values. Table 100. FMPI2C register map and reset values Register Offset name FMPI2C_CR1 DNF[3:0] Reset value FMPI2C_CR2 NBYTES[7:0] SADD[9:0] Reset value FMPI2C_OAR1 OA1[9:0]...
Page 591 RM0401 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Table 100. FMPI2C register map and reset values (continued) Register Offset name FMPI2C_TXDR TXDATA[7:0] 0x28 Reset value Refer to Section 2.2.2 on page 38 for the register boundary addresses. RM0401 Rev 3 591/771...
Page 592: Inter-Integrated Circuit (I 2 C) Interface
Inter-integrated circuit (I C) interface RM0401 Inter-integrated circuit (I C) interface 23.1 C introduction C (inter-integrated circuit) bus Interface serves as an interface between the microcontroller and the serial I C bus. It provides multimaster capability, and controls all I C bus-specific sequencing, protocol, arbitration and timing.
Page 593: I 2 C Main Features
RM0401 Inter-integrated circuit (I C) interface 23.2 C main features • Parallel-bus/I C protocol converter • Multimaster capability: the same interface can act as Master or Slave • C Master features: – Clock generation – Start and Stop generation • C Slave features: –...
Page 594: C Functional Description
Inter-integrated circuit (I C) interface RM0401 Note: Some of the above features may not be available in certain products. The user should refer to the product data sheet, to identify the specific features supported by the I C interface implementation. 23.3 C functional description In addition to receiving and transmitting data, this interface converts it from serial to parallel...
Page 595: I2C Slave Mode
RM0401 Inter-integrated circuit (I C) interface The block diagram of the I C interface is shown in Figure 208. Figure 208. I C block diagram 1. SMBA is an optional signal in SMBus mode. This signal is not applicable if SMBus is disabled. 23.3.2 C slave mode By default the I...
Page 596 Inter-integrated circuit (I C) interface RM0401 Note: In 10-bit addressing mode, the comparison includes the header sequence (11110xx0), where xx denotes the two most significant bits of the address. Header or address not matched: the interface ignores it and waits for another Start condition.
Page 597: Figure 209. Transfer Sequence Diagram For Slave Transmitter
RM0401 Inter-integrated circuit (I C) interface Figure 209. Transfer sequence diagram for slave transmitter 1. The EV1 and EV3_1 events stretch SCL low until the end of the corresponding software sequence. 2. The EV3 event stretches SCL low if the software sequence is not completed before the end of the next byte transmission Slave receiver Following the address reception and after clearing ADDR, the slave receives bytes from the...
Page 598: I2C Master Mode
Inter-integrated circuit (I C) interface RM0401 Figure 210. Transfer sequence diagram for slave receiver 1. The EV1 event stretches SCL low until the end of the corresponding software sequence. 2. The EV2 event stretches SCL low if the software sequence is not completed before the end of the next byte reception.
Page 599 RM0401 Inter-integrated circuit (I C) interface SCL master clock generation The CCR bits are used to generate the high and low level of the SCL clock, starting from the generation of the rising and falling edge (respectively). As a slave may stretch the SCL line, the peripheral checks the SCL input from the bus at the end of the time programmed in TRISE bits after rising edge generation.
Page 600 Inter-integrated circuit (I C) interface RM0401 The master can decide to enter Transmitter or Receiver mode depending on the LSB of the slave address sent. • In 7-bit addressing mode, – To enter Transmitter mode, a master sends the slave address with LSB reset. –...
Page 601: Figure 211. Transfer Sequence Diagram For Master Transmitter
RM0401 Inter-integrated circuit (I C) interface Figure 211. Transfer sequence diagram for master transmitter 1. The EV5, EV6, EV9, EV8_1 and EV8_2 events stretch SCL low until the end of the corresponding software sequence. 2. The EV8 event stretches SCL low if the software sequence is not complete before the end of the next byte transmission. RM0401 Rev 3 601/771...
Page 602 Inter-integrated circuit (I C) interface RM0401 Master receiver Following the address transmission and after clearing ADDR, the I C interface enters Master Receiver mode. In this mode the interface receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: An acknowledge pulse if the ACK bit is set The RxNE bit is set and an interrupt is generated if the ITEVFEN and ITBUFEN bits are...
Page 603: Figure 212. Transfer Sequence Diagram For Master Receiver
RM0401 Inter-integrated circuit (I C) interface Figure 212. Transfer sequence diagram for master receiver 1. If a single byte is received, it is NA. 2. The EV5, EV6 and EV9 events stretch SCL low until the end of the corresponding software sequence. 3.
Page 604: Error Conditions
Inter-integrated circuit (I C) interface RM0401 For N >2 -byte reception, from N-2 data reception • Wait until BTF = 1 (data N-2 in DR, data N-1 in shift register, SCL stretched low until data N-2 is read) • Set ACK low •...
Page 605: Programmable Noise Filter
RM0401 Inter-integrated circuit (I C) interface Overrun/underrun error (OVR) An overrun error can occur in slave mode when clock stretching is disabled and the I interface is receiving data. The interface has received a byte (RxNE=1) and the data in DR has not been read, before the next byte is received by the interface.
Page 606: Sda/Scl Line Control
Inter-integrated circuit (I C) interface RM0401 Note: For each frequency range, the constraint is given based on the worst case which is the minimum frequency of the range. Greater DNF values can be used if the system can support maximum hold time violation. 23.3.6 SDA/SCL line control •...
Page 607: Table 102. Smbus Vs. I2C
RM0401 Inter-integrated circuit (I C) interface Table 102. SMBus vs. I SMBus Max. speed 100 kHz Max. speed 400 kHz Min. clock speed 10 kHz No minimum clock speed 35 ms clock low timeout No timeout Logic levels are fixed Logic levels are V dependent Different address types (reserved, dynamic etc.)
Page 608 Inter-integrated circuit (I C) interface RM0401 SMBus alert mode SMBus Alert is an optional signal with an interrupt line for devices that want to trade their ability to master for a pin. SMBA is a wired-AND signal just as the SCL and SDA signals are. SMBA is used in conjunction with the SMBus General Call Address.
Page 609: Dma Requests
RM0401 Inter-integrated circuit (I C) interface 23.3.8 DMA requests DMA requests (when enabled) are generated only for data transfer. DMA requests are generated by Data Register becoming empty in transmission and Data Register becoming full in reception. The DMA must be initialized and enabled before the I2C data transfer. The DMAEN bit must be set in the I2C_CR2 register before the ADDR event.
Page 610: Packet Error Checking
Inter-integrated circuit (I C) interface RM0401 Reception using DMA DMA mode can be enabled for reception by setting the DMAEN bit in the I2C_CR2 register. Data will be loaded from the I2C_DR register to a Memory area configured using the DMA peripheral (refer to the DMA specification) whenever a data byte is received.
Page 611: I 2 C Interrupts
RM0401 Inter-integrated circuit (I C) interface be set before the ACK of the CRC reception in slave mode. It must be set when the ACK is set low in master mode. • A PECERR error flag/interrupt is also available in the I2C_SR1 register. •...
Page 612: Figure 213. I2C Interrupt Mapping Diagram
Inter-integrated circuit (I C) interface RM0401 Figure 213. I C interrupt mapping diagram ITEVFEN ADDR ADD10 STOPF it_event ITBUFEN RxNE ITERREN BERR ARLO it_error PECERR TIMEOUT SMBALERT 612/771 RM0401 Rev 3...
Page 613: I 2 C Debug Mode
RM0401 Inter-integrated circuit (I C) interface 23.5 C debug mode ® When the microcontroller enters the debug mode (Cortex -M4 with FPU core halted), the SMBUS timeout either continues to work normally or stops, depending on the DBG_I2Cx_SMBUS_TIMEOUT configuration bits in the DBGMCU module. For more details, refer to Section 26.16.2: Debug support for timers, watchdog, and I2C.
Page 614 Inter-integrated circuit (I C) interface RM0401 Bit 11 POS: Acknowledge/PEC Position (for data reception) This bit is set and cleared by software and cleared by hardware when PE=0. 0: ACK bit controls the (N)ACK of the current byte being received in the shift register. The PEC bit indicates that current byte in shift register is a PEC.
Page 615: I 2 C Control Register 2 (I2C_Cr2)
RM0401 Inter-integrated circuit (I C) interface Bit 2 Reserved, must be kept at reset value Bit 1 SMBUS: SMBus mode 0: I C mode 1: SMBus mode Bit 0 PE: Peripheral enable 0: Peripheral disable 1: Peripheral enable Note: If this bit is reset while a communication is on going, the peripheral is disabled at the end of the current communication, when back to IDLE state.
Page 616 Inter-integrated circuit (I C) interface RM0401 ITERREN: Error interrupt enable 0: Error interrupt disabled 1: Error interrupt enabled This interrupt is generated when: – BERR = 1 – ARLO = 1 – AF = 1 – OVR = 1 – PECERR = 1 –...
Page 617: I 2 C Own Address Register 1 (I2C_Oar1)
RM0401 Inter-integrated circuit (I C) interface 23.6.3 C Own address register 1 (I2C_OAR1) Address offset: 0x08 Reset value: 0x0000 Res. Res. Res. Res. Res. ADD[9:8] ADD[7:1] ADD0 MODE Bit 15 ADDMODE Addressing mode (slave mode) 0: 7-bit slave address (10-bit address not acknowledged) 1: 10-bit slave address (7-bit address not acknowledged) Bit 14 Should always be kept at 1 by software.
Page 618: C Data Register (I2C_Dr)
Inter-integrated circuit (I C) interface RM0401 23.6.5 C Data register (I2C_DR) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. DR[7:0] Bits 15:8 Reserved, must be kept at reset value Bits 7:0 DR[7:0] 8-bit data register Byte received or to be transmitted to the bus.
Page 619 RM0401 Inter-integrated circuit (I C) interface Bit 15 SMBALERT: SMBus alert In SMBus host mode: 0: no SMBALERT 1: SMBALERT event occurred on pin In SMBus slave mode: 0: no SMBALERT response address header 1: SMBALERT response address header to SMBALERT LOW received –...
Page 620 Inter-integrated circuit (I C) interface RM0401 Bit 9 ARLO: Arbitration lost (master mode) 0: No Arbitration Lost detected 1: Arbitration Lost detected Set by hardware when the interface loses the arbitration of the bus to another master – Cleared by software writing 0, or by hardware when PE=0. After an ARLO event the interface switches back automatically to Slave mode (MSL=0).
Page 621 RM0401 Inter-integrated circuit (I C) interface Bit 3 ADD10: 10-bit header sent (Master mode) 0: No ADD10 event occurred. 1: Master has sent first address byte (header). – Set by hardware when the master has sent the first byte in 10-bit address mode. –...
Page 622: I 2 C Status Register 2 (I2C_Sr2)
Inter-integrated circuit (I C) interface RM0401 23.6.7 C Status register 2 (I2C_SR2) Address offset: 0x18 Reset value: 0x0000 Note: Reading I2C_SR2 after reading I2C_SR1 clears the ADDR flag, even if the ADDR flag was set after reading I2C_SR1. Consequently, I2C_SR2 must be read only when ADDR is found set in I2C_SR1 or when the STOPF bit is cleared.
Page 623: I 2 C Clock Control Register (I2C_Ccr)
RM0401 Inter-integrated circuit (I C) interface Bit 2 TRA: Transmitter/receiver 0: Data bytes received 1: Data bytes transmitted This bit is set depending on the R/W bit of the address byte, at the end of total address phase. It is also cleared by hardware after detection of Stop condition (STOPF=1), repeated Start condition, loss of bus arbitration (ARLO=1), or when PE=0.
Page 624: C Trise Register (I2C_Trise)
Inter-integrated circuit (I C) interface RM0401 Bit 14 DUTY: Fm mode duty cycle 0: Fm mode t high 1: Fm mode t = 16/9 (see CCR) high Bits 13:12 Reserved, must be kept at reset value Bits 11:0 CCR[11:0]: Clock control register in Fm/Sm mode (Master mode) Controls the SCL clock in master mode.
Page 625: I 2 C Fltr Register (I2C_Fltr)
RM0401 Inter-integrated circuit (I C) interface 23.6.10 C FLTR register (I2C_FLTR) Address offset: 0x24 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ANOFF DNF[3:0] Bits 15:5 Reserved, must be kept at reset value Bit 4 ANOFF: Analog noise filter OFF 0: Analog noise filter enable 1: Analog noise filter disable Note: ANOFF must be configured only when the I2C is disabled (PE = 0).
Page 626: I2C Register Map
Inter-integrated circuit (I C) interface RM0401 23.6.11 C register map The table below provides the I C register map and reset values. Table 104. I C register map and reset values Offset Register I2C_CR1 0x00 Reset value I2C_CR2 FREQ[5:0] 0x04 Reset value ADD[ I2C_OAR1...
Page 627: Universal Synchronous Receiver Transmitter (Usart) /Universal Asynchronous Receiver Transmitter (Uart)
RM0401 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmitter (UART) 24.1 USART introduction The universal synchronous asynchronous receiver transmitter (USART) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format.
Page 628: Usart Main Features
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- 24.2 USART main features • Full duplex, asynchronous communications • NRZ standard format (Mark/Space) • Configurable oversampling method by 16 or by 8 to give flexibility between speed and clock tolerance •...
Page 629: Usart Implementation
RM0401 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver – Receive data register full – Idle line received – Overrun error – Framing error – Noise error – Parity error • Multiprocessor communication - enter into mute mode if address match does not occur •...
Page 630 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Through these pins, serial data is transmitted and received in normal USART mode as frames comprising: • An Idle Line prior to transmission or reception • A start bit • A data word (8 or 9 bits) least significant bit first •...
Page 631: Figure 214. Usart Block Diagram
RM0401 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Figure 214. USART block diagram PWDATA PRDATA Write Read (Data register) DR (CPU or DMA) (CPU or DMA) Receive data register (RDR) Transmit data register (TDR) IrDA SW_RX Receive Shift Register Transmit Shift Register ENDEC block...
Page 632: Usart Character Description
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- 24.4.1 USART character description Word length may be selected as being either 8 or 9 bits by programming the M bit in the USART_CR1 register (see Figure 215). The TX pin is in low state during the start bit. It is in high state during the stop bit. An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next frame that contains data (The number of “1”...
Page 633: Transmitter
RM0401 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver 24.4.2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the transmit enable bit (TE) is set, the data in the transmit shift register is output on the TX pin and the corresponding clock pulses are output on the SCLK pin.
Page 634: Figure 216. Configurable Stop Bits
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Figure 216. Configurable stop bits 8-bit Word length (M bit is reset) Possible Next data frame parity Data frame Next Start start Stop Bit2 Bit0 Bit1 Bit3 Bit4 Bit5 Bit6 Bit7 CLOCK **** ** LBCL bit controls last data clock pulse...
Page 635: Figure 217. Tc/Txe Behavior When Transmitting
RM0401 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver When a transmission is taking place, a write instruction to the USART_DR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission.
Page 636: Receiver
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- 24.4.3 Receiver The USART can receive data words of either 8 or 9 bits depending on the M bit in the USART_CR1 register. Start bit detection The start bit detection sequence is the same when oversampling by 16 or by 8. In the USART, the start bit is detected when a specific sequence of samples is recognized.
Page 637 RM0401 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Procedure: Enable the USART by writing the UE bit in USART_CR1 register to 1. Program the M bit in USART_CR1 to define the word length. Program the number of stop bits in USART_CR2. Select DMA enable (DMAR) in USART_CR3 if multibuffer communication is to take place.
Page 638 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- The RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set when the next data is received or the previous DMA request has not been serviced. When an overrun error occurs: •...
Page 639: Table 106. Noise Detection From Sampled Data
RM0401 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver receiver tolerance to clock deviation). In this case the NF bit will never be set. When noise is detected in a frame: • The NF bit is set at the rising edge of the RXNE bit. •...
Page 640 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Table 106. Noise detection from sampled data (continued) Sampled value NE status Received bit value Framing error A framing error is detected when: The stop bit is not recognized on reception at the expected time, following either a de- synchronization or excessive noise.
Page 641: Fractional Baud Rate Generation
RM0401 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver be set. The second stop bit is not checked for framing error. The RXNE flag will be set at the end of the first stop bit. 24.4.4 Fractional baud rate generation The baud rate for the receiver and transmitter (Rx and Tx) are both set to the same value as programmed in the Mantissa and Fraction values of USARTDIV.
Page 642 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- This leads to: DIV_Fraction = 16*0d0.99 = 0d15.84 The nearest real number is 0d16 = 0x10 => overflow of DIV_frac[3:0] => carry must be added up to the mantissa DIV_Mantissa = mantissa (0d50.990 + carry) = 0d51 = 0x33 Then, USART_BRR = 0x330 hence USARTDIV = 0d51.000 How to derive USARTDIV from USART_BRR register values when OVER8=1 Example 1:...
Page 643: Table 107. Error Calculation For Programmed Baud Rates At F
RM0401 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Table 107. Error calculation for programmed baud rates at f = 8 MHz or f = 12 MHz, PCLK PCLK oversampling by 16 Oversampling by 16 (OVER8=0) Baud rate = 8 MHz = 12 MHz PCLK PCLK...
Page 644 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Table 108. Error calculation for programmed baud rates at f = 8 MHz or f = 12 MHz, PCLK PCLK oversampling by 8 (continued) Oversampling by 8 (OVER8 = 1) Baud rate = 8 MHz = 12 MHz PCLK...
Page 645: Oversampling By 8
RM0401 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Table 110. Error calculation for programmed baud rates at f = 16 MHz or f = 24 MHz, PCLK PCLK oversampling by 8 Oversampling by 8 (OVER8=1) Baud rate = 16 MHz = 24 MHz PCLK PCLK...
Page 646: Oversampling By 8
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Table 111. Error calculation for programmed baud rates at f = 8 MHz or f = 16 MHz, PCLK PCLK oversampling by 16 (continued) Oversampling by 16 (OVER8=0) Baud rate = 8 MHz = 16 MHz PCLK PCLK...
Page 647: Table 114. Error Calculation For Programmed Baud Rates At F
RM0401 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Table 113. Error calculation for programmed baud rates at f = 30 MHz or f = 60 MHz, PCLK PCLK (1)(2) oversampling by 16 Oversampling by 16 (OVER8=0) Baud rate = 30 MHz = 60 MHz PCLK PCLK...
Page 648 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Table 114. Error calculation for programmed baud rates at f = 30 MHz or f = 60 MHz, PCLK PCLK (1) (2) oversampling by 8 (continued) Oversampling by 8 (OVER8=1) Baud rate = 30 MHz =60 MHz PCLK...
Page 649 RM0401 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Table 115. Error calculation for programmed baud rates at f = 42 MHz or f = 84 Hz, PCLK PCLK (1)(2) oversampling by 16 (continued) Oversampling by 16 (OVER8=0) Baud rate = 42 MHz = 84 MHz PCLK...
Page 650 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Table 116. Error calculation for programmed baud rates at f = 42 MHz or f = 84 MHz, PCLK PCLK (1)(2) oversampling by 8 (continued) Oversampling by 8 (OVER8=1) Baud rate = 42 MHz = 84 MHz PCLK...
Page 651: Usart Receiver Tolerance To Clock Deviation
RM0401 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Table 118. Error calculation for programmed baud rates at f = 100 MHz or f = 50 MHz, PCLK PCLK (1)(2) oversampling by 8 Oversampling by 8 (OVER8=1) Baud rate = 100 MHz = 50 MHz PCLK PCLK...
Page 652: Multiprocessor Communication
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- The USART receiver tolerance to properly receive data is equal to the maximum tolerated deviation and depends on the following choices: • 10- or 11-bit character length defined by the M bit in the USART_CR1 register •...
Page 653: Figure 221. Mute Mode Using Idle Line Detection
RM0401 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Idle line detection (WAKE=0) The USART enters mute mode when the RWU bit is written to 1. It wakes up when an Idle frame is detected. Then the RWU bit is cleared by hardware but the IDLE bit is not set in the USART_SR register.
Page 654: Parity Control
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Figure 222. Mute mode using address mark detection 24.4.7 Parity control Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the USART_CR1 register. Depending on the frame length defined by the M bit, the possible USART frame formats are as listed in Table 121.
Page 655: Lin (Local Interconnection Network) Mode
RM0401 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver sequence (a read from the status register followed by a read or write access to the USART_DR data register). Note: In case of wakeup by an address mark: the MSB bit of the data is taken into account to identify an address but not the parity bit.
Page 656: Figure 223. Break Detection In Lin Mode (11-Bit Break Length - Lbdl Bit Is Set)
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- detection circuit receives either a ‘1, if the break word was not complete, or a delimiter character if a break has been detected. The behavior of the break detector state machine and the break flag is shown in Figure 223.
Page 657: Usart Synchronous Mode
RM0401 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Figure 224. Break detection in LIN mode vs. Framing error detection 24.4.9 USART synchronous mode The synchronous mode is selected by writing the CLKEN bit in the USART_CR2 register to 1. In synchronous mode, the following bits must be kept cleared: •...
Page 658: Figure 225. Usart Example Of Synchronous Transmission
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- has been written). This means that it is not possible to receive a synchronous data without transmitting data. The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly.
Page 659: Single-Wire Half-Duplex Communication
RM0401 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Figure 227. USART data clock timing diagram (M=1) Figure 228. RX data setup/hold time Note: The function of SCLK is different in Smartcard mode. Refer to the Smartcard mode chapter for more details. 24.4.10 Single-wire half-duplex communication The single-wire half-duplex mode is selected by setting the HDSEL bit in the USART_CR3...
Page 660: Smartcard
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- As soon as HDSEL is written to 1: • the TX and RX lines are internally connected • the RX pin is no longer used • the TX pin is always released when no data is transmitted. Thus, it acts as a standard I/O in idle or in reception.
Page 661: Figure 230. Parity Error Detection Using The 1.5 Stop Bits
RM0401 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver shifting on the next baud clock edge. In Smartcard mode this transmission is further delayed by a guaranteed 1/2 baud clock. • If a parity error is detected during reception of a frame programmed with a 0.5 or 1.5 stop bit period, the transmit line is pulled low for a baud clock period after the completion of the receive frame.
Page 662: Irda Sir Endec Block
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- prescaler register USART_GTPR. SCLK frequency can be programmed from f /2 to /62, where f is the peripheral input clock. 24.4.12 IrDA SIR ENDEC block The IrDA mode is selected by setting the IREN bit in the USART_CR3 register. In IrDA mode, the following bits must be kept cleared: •...
Page 663: Figure 231. Irda Sir Endec- Block Diagram
RM0401 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver IrDA low-power mode Transmitter: In low-power mode the pulse width is not maintained at 3/16 of the bit period. Instead, the width of the pulse is 3 times the low-power baud rate that can be a minimum of 1.42 MHz. Generally this value is 1.8432 MHz (1.42 MHz <...
Page 664: Continuous Communication Using Dma
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- 24.4.13 Continuous communication using DMA The USART is capable of continuous communication using the DMA. The DMA requests for Rx buffer and Tx buffer are generated independently. Transmission using DMA DMA mode can be enabled for transmission by setting DMAT bit in the USART_CR3 register.
Page 665: Figure 233. Transmission Using Dma
RM0401 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Figure 233. Transmission using DMA Reception using DMA DMA mode can be enabled for reception by setting the DMAR bit in USART_CR3 register. Data is loaded from the USART_DR register to a SRAM area configured using the DMA peripheral (refer to the DMA specification) whenever a data byte is received.
Page 666: Hardware Flow Control
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Figure 234. Reception using DMA Error flagging and interrupt generation in multibuffer communication In case of multibuffer communication if any error occurs during the transaction the error flag will be asserted after the current byte. An interrupt will be generated if the interrupt enable flag is set.
Page 667: Figure 236. Rts Flow Control
RM0401 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver RTS flow control If the RTS flow control is enabled (RTSE=1), then nRTS is asserted (tied low) as long as the USART receiver is ready to receive a new data. When the receive register is full, nRTS is deasserted, indicating that the transmission is expected to stop at the end of the current frame.
Page 668: Usart Interrupts
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Note: Special behavior of break frames: when the CTS flow is enabled, the transmitter does not check the nCTS input state to send a break. 24.5 USART interrupts Table 122. USART interrupt requests Interrupt event Event flag Enable control bit...
Page 669: Usart Registers
RM0401 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Figure 238. USART interrupt mapping diagram 24.6 USART registers Refer to for a list of abbreviations used in register descriptions. Section 1.2 on page 34 The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). 24.6.1 Status register (USART_SR) Address offset: 0x00...
Page 670 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Bits 31:10 Reserved, must be kept at reset value Bit 9 CTS: CTS flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software (by writing it to 0).
Page 671 RM0401 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Bit 3 ORE: Overrun error This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RXNE=1. An interrupt is generated if RXNEIE=1 in the USART_CR1 register.
Page 672: Data Register (Usart_Dr)
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- 24.6.2 Data register (USART_DR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 673: Control Register 1 (Usart_Cr1)
RM0401 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver 24.6.4 Control register 1 (USART_CR1) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OVER8 Res. WAKE PEIE TXEIE TCIE...
Page 674 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Bit 8 PEIE: PE interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An USART interrupt is generated whenever PE=1 in the USART_SR register Bit 7 TXEIE: TXE interrupt enable This bit is set and cleared by software.
Page 675: Control Register 2 (Usart_Cr2)
RM0401 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver 24.6.5 Control register 2 (USART_CR2) Address offset: 0x10 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LINEN STOP[1:0] CLKEN CPOL CPHA...
Page 676: Control Register 3 (Usart_Cr3)
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Bit 8 LBCL: Last bit clock pulse This bit allows the user to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. 0: The clock pulse of the last data bit is not output to the SCLK pin 1: The clock pulse of the last data bit is output to the SCLK pin Note: 1: The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected...
Page 677 RM0401 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Bit 9 CTSE: CTS enable 0: CTS hardware flow control disabled 1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while a data is being transmitted, then the transmission is completed before stopping.
Page 678: Guard Time And Prescaler Register (Usart_Gtpr)
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Bit 0 EIE: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USART_SR register) in case of Multi Buffer Communication (DMAR=1 in the USART_CR3 register).
Page 679: Usart Register Map
RM0401 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver 24.6.8 USART register map The table below gives the USART register map and reset values. Table 123. USART register map and reset values Offset Register USART_SR 0x00 Reset value USART_DR DR[8:0] 0x04 Reset value DIV_Fraction...
Page 680: Serial Peripheral Interface/ Inter-Ic Sound (Spi/I2S)
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S) 25.1 Introduction The SPI/I²S interface can be used to communicate with external devices using the SPI protocol or the I S audio protocol. SPI or I S mode is selectable by software. SPI mode is selected by default after a device reset.
Page 681: Spi Main Features
RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S) 25.1.1 SPI main features • Master or slave operation • Full-duplex synchronous transfers on three lines • Half-duplex synchronous transfer on two lines (with bidirectional data line) • Simplex synchronous transfers on two lines (with unidirectional data line) •...
Page 682: Spi Extended Features
S (I2S1, I2S2 and I2S5) clock can be derived from an external clock mapped on the I2S_CKIN pin. 25.2 SPI/I2S implementation This manual describes the full set of features implemented in SPI1, SPI2 and SPI5. Table 124. STM32F410 SPI implementation Features SPI1 SPI2 SPI5...
Page 683: Spi Functional Description
RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S) 25.3 SPI functional description 25.3.1 General description The SPI allows synchronous, serial communication between the MCU and external devices. Application software can manage the communication by polling the status flag or using dedicated SPI interrupt. The main elements of SPI and their interactions are shown in the following block diagram Figure 239.
Page 684: Communications Between One Master And One Slave
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0401 25.3.2 Communications between one master and one slave The SPI allows the MCU to communicate using different configurations, depending on the device targeted and the application requirements. These configurations use 2 or 3 wires (with software NSS management) or 3 or 4 wires (with hardware NSS management).
Page 685: Figure 241. Half-Duplex Single Master/ Single Slave Application
RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S) Figure 241. Half-duplex single master/ single slave application 1. The NSS pins can be used to provide a hardware control flow between master and slave. Optionally, the pins can be left unused by the peripheral. Then the flow has to be handled internally for both master and slave.
Page 686: Figure 242. Simplex Single Master/Single Slave Application
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0401 Figure 242. Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) 1. The NSS pins can be used to provide a hardware control flow between master and slave. Optionally, the pins can be left unused by the peripheral.
Page 687: Standard Multi-Slave Communication
RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S) 25.3.3 Standard multi-slave communication In a configuration with two or more independent slaves, the master uses GPIO pins to manage the chip select lines for each slave (see Figure 243.). The master must select one of the slaves individually by pulling low the GPIO connected to the slave NSS input.
Page 688: Multi-Master Communication
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0401 25.3.4 Multi-master communication Unless SPI bus is not designed for a multi-master capability primarily, the user can use build in feature which detects a potential conflict between two nodes trying to master the bus at the same time.
Page 689: Figure 245. Hardware/Software Slave Select Management
RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S) – NSS output enable (SSM=0,SSOE = 1): this configuration is only used when the MCU is set as master. The NSS pin is managed by the hardware. The NSS signal is driven low as soon as the SPI is enabled in master mode (SPE=1), and is kept low until the SPI is disabled (SPE =0).
Page 690: Communication Formats
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0401 25.3.6 Communication formats During SPI communication, receive and transmit operations are performed simultaneously. The serial clock (SCK) synchronizes the shifting and sampling of the information on the data lines. The communication format depends on the clock phase, the clock polarity and the data frame format.
Page 691: Figure 246. Data Clock Timing Diagram
RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S) Figure 246. Data clock timing diagram Note: The order of data bits depends on LSBFIRST bit setting. Data frame format The SPI shift register can be set up to shift out MSB-first or LSB-first, depending on the value of the LSBFIRST bit.
Page 692: Spi Configuration
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0401 25.3.7 SPI configuration The configuration procedure is almost the same for master and slave. For specific mode setups, follow the dedicated chapters. When a standard communication is to be initialized, perform these steps: Write proper GPIO registers: Configure GPIO for MOSI, MISO and SCK pins.
Page 693: Data Transmission And Reception Procedures
RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S) 25.3.9 Data transmission and reception procedures Rx and Tx buffers In reception, data are received and then stored into an internal Rx buffer while in transmission, data are first stored into an internal Tx buffer before being transmitted. A read access to the SPI_DR register returns the Rx buffered value whereas a write access to the SPI_DR stores the written data into the Tx buffer.
Page 694: Figure 247. Txe/Rxne/Bsy Behavior In Master / Full-Duplex Mode (Bidimode=0, Rxonly=0) In The Case Of Continuous Transfers
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0401 underflow error signal for slave operating in SPI mode, and that data from the slave are always transacted and processed by the master even if the slave cannot not prepare them correctly in time. It is preferable for the slave to use DMA, especially when data frames are shorter and bus rate is high.
Page 695: Procedure For Disabling The Spi
RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S) Figure 248. TXE/RXNE/BSY behavior in slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in the case of continuous transfers 25.3.10 Procedure for disabling the SPI When SPI is disabled, it is mandatory to follow the disable procedures described in this paragraph.
Page 696: Communication Using Dma (Direct Memory Addressing)
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0401 Note: During discontinuous communications, there is a 2 APB clock period delay between the write operation to the SPI_DR register and BSY bit setting. As a consequence it is mandatory to wait first until TXE is set and then until BSY is cleared after writing the last data.
Page 697: Figure 249. Transmission Using Dma
RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S) To close communication it is mandatory to follow these steps in order: Disable DMA streams for Tx and Rx in the DMA registers, if the streams are used. Disable the SPI by following the SPI disable procedure. Disable DMA Tx and Rx buffers by clearing the TXDMAEN and RXDMAEN bits in the SPI_CR2 register, if DMA Tx and/or DMA Rx are used.
Page 698: Spi Status Flags
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0401 Figure 250. Reception using DMA 25.3.12 SPI status flags Three status flags are provided for the application to completely monitor the state of the SPI bus. Tx buffer empty flag (TXE) When it is set, the TXE flag indicates that the Tx buffer is empty and that the next data to be transmitted can be loaded into the buffer.
Page 699: Spi Error Flags
RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S) The BSY flag is cleared under any one of the following conditions: • When the SPI is correctly disabled • When a fault is detected in Master mode (MODF bit set to 1) •...
Page 700: Spi Special Features
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0401 CRC error (CRCERR) This flag is used to verify the validity of the value received when the CRCEN bit in the SPIx_CR1 register is set. The CRCERR flag in the SPIx_SR register is set if the value received in the shift register does not match the receiver SPIx_RXCRC value.
Page 701: Crc Calculation
RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S) Note: To detect TI frame errors in slave transmitter only mode by using the Error interrupt (ERRIE=1), the SPI must be configured in 2-line unidirectional mode by setting BIDIMODE and BIDIOE to 1 in the SPI_CR1 register. When BIDIMODE is set to 0, OVR is set to 1 because the data register is never read and error interrupts are always generated, while when BIDIMODE is set to 1, data are not received and OVR is never set.
Page 702 Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0401 The received CRC is stored in the Rx buffer like any other data frame. A CRC-format transaction takes one more data frame to communicate at the end of data sequence. When the last CRC data is received, an automatic check is performed comparing the received value and the value in the SPIx_RXCRC register.
Page 703: Spi Interrupts
RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S) 25.5 SPI interrupts During SPI communication an interrupts can be generated by the following events: • Transmit Tx buffer ready to be loaded • Data received in Rx buffer • Master mode fault •...
Page 704: S Functional Description
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0401 25.6 S functional description 25.6.1 S general description The block diagram of the I S is shown in Figure 252. Figure 252. I S block diagram 1. MCK is mapped on the MISO pin. The SPI can function as an audio I S interface when the I S capability is enabled (by setting...
Page 705: I2S Full-Duplex
RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S) The I S shares three common pins with the SPI: • SD: Serial Data (mapped on the MOSI pin) to transmit or receive the two time- multiplexed data channels (in half-duplex mode only). •...
Page 706: Supported Audio Protocols
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0401 Figure 253. Full-duplex communication 25.6.3 Supported audio protocols The three-line bus has to handle only audio data generally time-multiplexed on two channels: the right channel and the left channel. However there is only one 16-bit register for transmission or reception.
Page 707: Figure 254. I 2 S Philips Protocol Waveforms (16/32-Bit Full Accuracy, Cpol = 0)
RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S) The I S interface supports four audio standards, configurable using the I2SSTD[1:0] and PCMSYNC bits in the SPIx_I2SCFGR register. S Philips standard For this standard, the WS signal is used to indicate which channel is being transmitted. It is activated one CK clock cycle before the first bit (MSB) is available.
Page 708: Figure 256. Transmitting 0X8Eaa33
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0401 • In transmission mode: If 0x8EAA33 has to be sent (24-bit): Figure 256. Transmitting 0x8EAA33 • In reception mode: If data 0x8EAA33 is received: Figure 257. Receiving 0x8EAA33 Figure 258. I S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) When 16-bit data frame extended to 32-bit channel frame is selected during the I configuration phase, only one access to the SPIx_DR register is required.
Page 709: Figure 259. Example Of 16-Bit Data Frame Extended To 32-Bit Channel Frame
RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S) Figure 259. Example of 16-bit data frame extended to 32-bit channel frame For transmission, each time an MSB is written to SPIx_DR, the TXE flag is set and its interrupt, if allowed, is generated to load the SPIx_DR register with the new value to send. This takes place even if 0x0000 have not yet been sent because it is done by hardware.
Page 710: Figure 262. Msb Justified 16-Bit Extended To 32-Bit Packet Frame With Cpol = 0
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0401 Figure 262. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 LSB justified standard This standard is similar to the MSB justified standard (no difference for the 16-bit and 32-bit full-accuracy frame formats).
Page 711: Figure 265. Operations Required To Transmit 0X3478Ae
RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S) • In transmission mode: If data 0x3478AE have to be transmitted, two write operations to the SPIx_DR register are required by software or by DMA. The operations are shown below. Figure 265. Operations required to transmit 0x3478AE •...
Page 712: Figure 268. Example Of 16-Bit Data Frame Extended To 32-Bit Channel Frame
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0401 Figure 268. Example of 16-bit data frame extended to 32-bit channel frame In transmission mode, when a TXE event occurs, the application has to write the data to be transmitted (in this case 0x76A3). The 0x000 field is transmitted first (extension on 32-bit). The TXE flag is set again as soon as the effective data (0x76A3) is sent on SD.
Page 713: Clock Generator
RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S) Note: For both modes (master and slave) and for both synchronizations (short and long), the number of bits between two consecutive pieces of data (and so two synchronization signals) needs to be specified (DATLEN and CHLEN bits in the SPIx_I2SCFGR register) even in slave mode.
Page 714: Table 126. Audio-Frequency Precision Using Standard 8 Mhz Hse
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0401 The audio sampling frequency may be 192 KHz, 96 kHz, 48 kHz, 44.1 kHz, 32 kHz, 22.05 kHz, 16 kHz, 11.025 kHz or 8 kHz (or any other value within this range). In order to reach the desired frequency, the linear divider needs to be programmed according to the formulas below: When the master clock is generated (MCKOE in the SPIx_I2SPR register is set):...
Page 715: I 2 S Master Mode
RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S) Table 126. Audio-frequency precision using standard 8 MHz HSE (continued) SYSCLK Data Target f I2SDIV I2SODD MCLK Real f (KHz) Error length (Hz) (MHz) 22050 20833.333 5.5178% 16000 15625 2.3438% 16000 15625 2.3438% 11025 11029.4118 0.0400%...
Page 716 Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0401 indicates which channel is to be transmitted. It has a meaning when the TXE flag is set because the CHSIDE flag is updated when TXE goes high. A full frame has to be considered as a left channel data transmission followed by a right channel data transmission.
Page 717: I 2 S Slave Mode
RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S) Then wait 1 I S clock cycle (using a software loop) Disable the I S (I2SE = 0) • For all other combinations of DATLEN and CHLEN, whatever the audio mode selected through the I2SSTD bits, carry out the following sequence to switch off the I Wait for the second to last RXNE = 1 (n –...
Page 718: I 2 S Status Flags
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0401 Note that the TXE flag should be checked to be at 1 before attempting to write the Tx buffer. For more details about the write operations depending on the I S Standard-mode selected, refer to Section 25.6.3: Supported audio protocols.
Page 719: I 2 S Error Flags
RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S) The BSY flag is useful to detect the end of a transfer if the software needs to disable the I This avoids corrupting the last transfer. For this, the procedure described below must be strictly respected.
Page 720: I 2 S Interrupts
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0401 ERRIE bit in the SPIx_CR2 register is set. The UDR bit is cleared by a read operation on the SPIx_SR register. Overrun flag (OVR) This flag is set when data are received and the previous data have not yet been read from the SPIx_DR register.
Page 721: Spi And I 2 S Registers
RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S) 25.7 SPI and I S registers The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). SPI_DR in addition by can be accessed by 8-bit access. Refer to Section 1.2 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16 bits) or words (32 bits).
Page 722 Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0401 Bit 11 DFF: Data frame format 0: 8-bit data frame format is selected for transmission/reception 1: 16-bit data frame format is selected for transmission/reception Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation. It is not used in I S mode.
Page 723: Spi Control Register 2 (Spi_Cr2)
RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S) Bit 2 MSTR: Master selection 0: Slave configuration 1: Master configuration Note: This bit should not be changed when communication is ongoing. It is not used in I S mode. Bit1 CPOL: Clock polarity 0: CK to 0 when idle 1: CK to 1 when idle Note: This bit should not be changed when communication is ongoing.
Page 724: Spi Status Register (Spi_Sr)
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0401 Bit 2 SSOE: SS output enable 0: SS output is disabled in master mode and the cell can work in multimaster configuration 1: SS output is enabled in master mode and when the cell is enabled. The cell cannot work in a multimaster environment.
Page 725 RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S) Bit 5 MODF: Mode fault 0: No mode fault occurred 1: Mode fault occurred This flag is set by hardware and reset by a software sequence. Refer to Section 25.4 on page 700 for the software sequence.
Page 726: Spi Data Register (Spi_Dr)
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0401 25.7.4 SPI data register (SPI_DR) Address offset: 0x0C Reset value: 0x0000 DR[15:0] Bits 15:0 DR[15:0]: Data register Data received or to be transmitted. The data register is split into 2 buffers - one for writing (Transmit Buffer) and another one for reading (Receive buffer).
Page 727: Spi Rx Crc Register (Spi_Rxcrcr) (Not Used In I 2 S Mode)
RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S) 25.7.6 SPI RX CRC register (SPI_RXCRCR) (not used in I S mode) Address offset: 0x14 Reset value: 0x0000 RXCRC[15:0] Bits 15:0 RXCRC[15:0]: Rx CRC register When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently received bytes.
Page 728: Spi_I 2 S Configuration Register (Spi_I2Scfgr)
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0401 25.7.8 SPI_I S configuration register (SPI_I2SCFGR) Address offset: 0x1C Reset value: 0x0000 ASTRE PCMSY Res. Res. Res. I2SMOD I2SE I2SCFG Res. I2SSTD CKPOL DATLEN CHLEN Bits 15:13 Reserved, must be kept at reset value. Bit 12 ASTREN: Asynchronous start enable.
Page 729: Spi_I 2 S Prescaler Register (Spi_I2Spr)
RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S) Bits 5:4 I2SSTD: I2S standard selection 00: I S Philips standard. 01: MSB justified standard (left justified) 10: LSB justified standard (right justified) 11: PCM standard For more details on I S standards, refer to Section 25.6.3 on page 706.
Page 730 Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0401 Bit 9 MCKOE: Master clock output enable 0: Master clock output is disabled 1: Master clock output is enabled Note: This bit should be configured when the I S is disabled. It is used only when the I S is in master mode.
Page 731: Spi Register Map
RM0401 Serial peripheral interface/ inter-IC sound (SPI/I2S) 25.7.10 SPI register map The table provides shows the SPI register map and reset values. Table 128. SPI register map and reset values Offset Register SPI_CR1 [2:0] 0x00 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI_CR2 0x04 Reset value...
Page 732: Debug Support (Dbg)
26.1 Overview ® The STM32F410 is built around a Cortex -M4 with FPU core which contains hardware extensions for advanced debugging features. The debug extensions allow the core to be stopped either on a given instruction fetch (breakpoint) or data access (watchpoint). When stopped, the core’s internal state and the system’s external state may be examined.
Page 733: Reference Arm® Documentation
CoreSight Design Kit revision r0p1 Technical Reference Manual 26.3 SWJ debug port (serial wire and JTAG) The STM32F410 core of the integrates the Serial Wire / JTAG Debug Port (SWJ-DP). It is ® an Arm standard CoreSight debug port that combines a JTAG-DP (5-pin) interface and a SW-DP (2-pin) interface.
Page 734: Mechanism To Select The Jtag-Dp Or The Sw-Dp
Send more than 50 TCK cycles with TMS (SWDIO) =1 26.4 Pinout and debug port pins The STM32F410 MCUs are available in various packages with different numbers of available pins. As a result, some functionality (ETM) related to pin availability may differ between packages.
Page 735: Swj Debug Port Pins
Debug support (DBG) 26.4.1 SWJ debug port pins Five pins are used as outputs from the STM32F410 for the SWJ-DP as alternate functions of general-purpose I/Os. These pins are available on all packages. Table 129. SWJ debug port pins JTAG debug port...
Page 736: Internal Pull-Up And Pull-Down On Jtag Pins
Debug support (DBG) RM0401 26.4.3 Internal pull-up and pull-down on JTAG pins It is necessary to ensure that the JTAG input pins are not floating since they are directly connected to flip-flops to control the debug mode features. Special care must be taken with the SWCLK/TCK pin which is directly connected to the clock of some of these flip-flops.
Page 737: Using Serial Wire And Releasing The Unused Debug Pins As Gpios
RM0401 Debug support (DBG) 26.4.4 Using serial wire and releasing the unused debug pins as GPIOs To use the serial wire DP to release some GPIOs, the user software must change the GPIO (PA15, PB3 and PB4) configuration mode in the GPIO_MODER register. This releases PA15, PB3 and PB4 which now become available as GPIOs.
Page 738: Figure 275. Jtag Tap Connections
Debug support (DBG) RM0401 Figure 275. JTAG TAP connections 738/771 RM0401 Rev 3...
Page 739: Id Codes And Locking Mechanism
0xE0042000. 26.6.1 MCU device ID code The MCUs integrate an MCU ID code. This ID identifies the ST MCU part-number and the die revision. It is part of the DBG_MCU component and is mapped on the external PPB bus (see Section 26.16 on page...
Page 740: Cortex ® -M4 With Fpu Jedec-106 Id Code
Debug support (DBG) RM0401 ® 26.6.4 Cortex -M4 with FPU JEDEC-106 ID code ® ® The Arm Cortex -M4 with FPU integrates a JEDEC-106 ID code. It is located in the 4KB ROM table mapped on the internal PPB bus at address 0xE00F FFD0_0xE00F FFE0. This code is accessible by the JTAG Debug Port (4 to 5 pins) or by the SW Debug Port (two pins) or by the user software.
Page 741: Table 132. 32-Bit Debug Port Registers Addressed Through The Shifted Value A[3:2]
RM0401 Debug support (DBG) Table 131. JTAG debug port data registers (continued) IR(3:0) Data register Details Access port access register Initiates an access port and allows access to an access port register. – When transferring data IN: Bits 34:3 = DATA[31:0] = 32-bit data to shift in for a write request Bits 2:1 = A[3:2] = 2-bit address (sub-address AP registers).
Page 742: Sw Debug Port
Debug support (DBG) RM0401 26.8 SW debug port 26.8.1 SW protocol introduction This synchronous serial protocol uses two pins: • SWCLK: clock from host to target • SWDIO: bidirectional The protocol allows two banks of registers (DPACC registers and APACC registers) to be read and written to.
Page 743: Sw-Dp State Machine (Reset, Idle States, Id Code)
RM0401 Debug support (DBG) Table 134. ACK response (3 bits) Name Description 001: FAULT 0..2 010: WAIT 100: OK The ACK Response must be followed by a turnaround time only if it is a READ transaction or if a WAIT or FAULT acknowledge has been received. Table 135.
Page 744: Sw-Dp Registers
Access to these registers are initiated when APnDP=0 Table 136. SW-DP registers CTRLSEL bit A[3:2] of SELECT Register Notes register The manufacturer code is not set to ST Read IDCODE code. 0x2BA01477 (identifies the SW-DP) Write ABORT Purpose is to: – request a system or debug power-up –...
Page 745: Sw-Ap Registers
RM0401 Debug support (DBG) 26.8.6 SW-AP registers Access to these registers are initiated when APnDP=1 There are many AP Registers (see AHB-AP) addressed as the combination of: • The shifted value A[3:2] • The current value of the DP SELECT register 26.9 AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP...
Page 746: Core Debug
Debug support (DBG) RM0401 26.10 Core debug Core debug is accessed through the core debug registers. Debug access to these registers is by means of the Advanced High-performance Bus (AHB-AP) port. The processor can access these registers directly over the internal Private Peripheral Bus (PPB). It consists of 4 registers: Table 138.
Page 747: Capability Of The Debugger Host To Connect Under System Reset
RM0401 Debug support (DBG) 26.11 Capability of the debugger host to connect under system reset The reset system of the MCUs comprises the following reset sources: • POR (power-on reset) which asserts a RESET at each power-up. • Internal watchdog reset •...
Page 748: Dwt (Data Watchpoint Trigger)
Debug support (DBG) RM0401 26.13 DWT (data watchpoint trigger) The DWT unit consists of four comparators. They are configurable as: • a hardware watchpoint or • a trigger to an ETM or • a PC sampler or • a data address sampler The DWT also provides some means to give some profiling informations.
Page 749: Table 139. Main Itm Registers
RM0401 Debug support (DBG) For this, the DWT must be configured to trigger the ITM: the bit CYCCNTENA (bit0) of the DWT Control Register must be set. In addition, the bit2 (SYNCENA) of the ITM Trace Control Register must be set. Note: If the SYNENA bit is not set, the DWT generates Synchronization triggers to the TPIU which will send only TPIU synchronization packets and not ITM synchronization packets.
Page 750: Etm (Embedded Trace Macrocell)
Debug support (DBG) RM0401 Example of configuration To output a simple value to the TPIU: • Configure the TPIU and assign TRACE I/Os by configuring the DBGMCU_CR (refer to Section 26.17.2: TRACE pin assignment Section 26.16.3: Debug MCU configuration register) •...
Page 751: Configuration Example
RM0401 Debug support (DBG) Table 140. Main ETM registers Address Register Details Write 0xC5ACCE55 to unlock the write access to the 0xE0041FB0 ETM Lock Access other ETM registers. This register controls the general operation of the ETM, 0xE0041000 ETM Control for instance how tracing is enabled.
Page 752: Debug Support For Timers, Watchdog, And I C
Debug support (DBG) RM0401 For this, the debugger host must first set some debug configuration registers to change the low-power mode behavior: • In Sleep mode, DBG_SLEEP bit of DBGMCU_CR register must be previously set by the debugger. This will feed HCLK with the same clock that is provided to FCLK (system clock previously configured by the software).
Page 753: Debug Mcu Apb1 Freeze Register (Dbgmcu_Apb1_Fz)
RM0401 Debug support (DBG) Bits 31:8 Reserved, must be kept at reset value. Bits 7:5 TRACE_MODE[1:0] and TRACE_IOEN: Trace pin assignment control – With TRACE_IOEN=0: TRACE_MODE=xx: TRACE pins not assigned (default state) – With TRACE_IOEN=1: – TRACE_MODE=00: TRACE pin assignment for Asynchronous Mode –...
Page 754 Debug support (DBG) RM0401 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:25 Reserved, must be kept at reset value. Bit 24 DBG_I2CFMP_SMBUS_TIMEOUT: FMPI2C SMBUS timeout mode stopped when Core is halted 0: Same behavior as in normal mode 1: The SMBUS timeout is frozen...
Page 755: Debug Mcu Apb2 Freeze Register (Dbgmcu_Apb2_Fz)
RM0401 Debug support (DBG) Bit 4 DBG_TIM6_STOP: TIM6 counter stopped when core is halted 0: The clock of the involved Timer Counter is fed even if the core is halted 1: The clock of the involved Timer counter is stopped when the core is halted Bit 3 DBG_TIM5_STOP: TIM5 counter stopped when core is halted 0: The clock of the involved Timer Counter is fed even if the core is halted 1: The clock of the involved Timer counter is stopped when the core is halted...
Page 756: Tpiu (Trace Port Interface Unit)
Debug support (DBG) RM0401 26.17 TPIU (trace port interface unit) 26.17.1 Introduction The TPIU acts as a bridge between the on-chip trace data from the ITM and the ETM. The output data stream encapsulates the trace source ID, that is then captured by a trace port analyzer (TPA).
Page 757: Trace Pin Assignment
RM0401 Debug support (DBG) 26.17.2 TRACE pin assignment • Asynchronous mode The asynchronous mode requires 1 extra pin and is available on all packages. It is only available if using Serial Wire mode (not in JTAG mode). Table 141. Asynchronous TRACE pin assignment Trace synchronous mode TPUI pin name Pin assignment...
Page 758: Tpui Formatter
Debug support (DBG) RM0401 Table 143. Flexible TRACE pin assignment DBGMCU_CR TRACE IO pin assigned register Pins TRAC TRACE PB3 /JTDO/ PC10/ PC11/ PC12/ PB11/ assigned for: E_IOE _MODE TRACESW TRACED[0 TRACED[1 TRACED[2 TRACED[3 TRACEC [1:0] No Trace Released (default state) Asynchronou TRACESW Released...
Page 759: Tpui Frame Synchronization Packets
RM0401 Debug support (DBG) ® ® Note: Refer to the Arm CoreSight Architecture Specification v1.0 (Arm IHI 0029B) for further information 26.17.4 TPUI frame synchronization packets The TPUI can generate two types of synchronization packets: • The Frame Synchronization packet (or Full Word Synchronization packet) It consists of the word: 0x7F_FF_FF_FF (LSB emitted first).
Page 760: Asynchronous Mode
Debug support (DBG) RM0401 26.17.7 Asynchronous mode This is a low cost alternative to output the trace using only 1 pin: this is the asynchronous output pin TRACESWO. Obviously there is a limited bandwidth. TRACESWO is multiplexed with JTDO when using the SW-DP pin. This way, this functionality is available in all packages.
Page 761: 26.17.10 Example Of Configuration
RM0401 Debug support (DBG) Table 144. Important TPIU registers (continued) Address Register Description Bits 31-9 = always ‘0 Bit 8 = TrigIn = always ‘1 to indicate that triggers are indicated Bits 7-4 = always 0 Bits 3-2 = always 0 Bit 1 = EnFCont.
Page 762: Dbg Register Map
Debug support (DBG) RM0401 26.18 DBG register map The following table summarizes the Debug registers. Table 145. DBG register map and reset values Addr. Register DBGMCU REV_ID DEV_ID 0xE004 _IDCODE 2000 X X X X X X X X X X X X X X X X X X X X X X X X X X X X Reset value DBGMCU_CR...
Page 763: Device Electronic Signature
RM0401 Device electronic signature Device electronic signature The electronic signature is stored in the Flash memory area. It can be read using the JTAG/SWD or the CPU. It contains factory-programmed identification data that allow the user firmware or other external devices to automatically match its interface to the characteristics of the STM32F4xx microcontrollers.
Page 764: Flash Size
Device electronic signature RM0401 Address offset: 0x08 Read only = 0xXXXX XXXX where X is factory-programmed U_ID[95:80] U_ID[79:64] Bits 31:0 U_ID[95:64]: 95:64 Unique ID bits. 27.2 Flash size Base address: 0x1FFF 7A22 Address offset: 0x00 Read only = 0xXXXX where X is factory-programmed F_SIZE Bits 15:0 F_ID[15:0]: Flash memory size This bitfield indicates the size of the device Flash memory expressed in Kbytes.
Page 765: Revision History
RM0401 Revision history Revision history Table 146. Document revision history Date Revision Changes 07-Sep-2015 Initial release. System and memory overview Updated Figure 2: Memory map. Interrupts and events (EXTI) Updated Section 9.1.2: SysTick calibration value register. Analog-to-digital converted (ADC) Removed note in Section : Temperature sensor, V and V REFINT...
Page 766 Index RM0401 Index ADC_CCR ......240 ADC_CR1 ......230 ADC_CR2 .
Page 767 RM0401 Index EXTI_EMR ......206 EXTI_FTSR ......207 EXTI_IMR .
Page 768 Index RM0401 I2Cx_CR2 ......578 IWDG_KR ......482 IWDG_PR .
Page 769 RM0401 Index RTC_DR ......503 RTC_ISR ......506 RTC_PRER .
Page 770 Index RM0401 TIMx_SMCR ......316 TIMx_SR ......320 USART_BRR .
Page 771 ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

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