NEC 78K0 User Manual page 355

(1) When internal reset is executed by oscillation stop of X1 input clock
X1 input clock
Ring-OSC clock
Internal reset signal
CLME
CLMRF
(CLME = 1 is set after RESET input and during X1 input clock oscillation stabilization time)
Normal
operation
CPU operation
X1 input clock
Ring-OSC clock
RESET
CLME
Clock monitor status
Monitoring
RESET input clears bit 0 (CLME) of the clock monitor mode register (CLM) to 0 and stops the clock monitor
operation. Even if CLME is set to 1 by software during the oscillation stabilization time (reset value of OSTS register
16
is 05H (2 /f )) of the X1 input clock, monitoring is not performed until the oscillation stabilization time of the X1 input
XP
clock ends. Monitoring is automatically started at the end of the oscillation stabilization time.
CHAPTER 19 CLOCK MONITOR
Figure 19-3. Timing of Clock Monitor (1/4)
4 clocks of Ring-OSC clock
(2) Clock monitor status after RESET input
Clock supply
stopped
Reset
Oscillation
stopped
Oscillation 17 clocks
stopped
Monitoring stopped
User's Manual U16227EJ2V0UD
Normal operation (Ring-OSC clock)
Oscillation stabilization time
Set to 1 by software
Waiting for end
of oscillation
stabilization time
Monitoring
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