Cpu-Timer Interrupts Signals And Output Signal; Cpu-Timers 0, 1, 2 Configuration And Control Registers - Texas Instruments TMS320x2833 series Reference Manual

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Figure 3-20. CPU-Timer Interrupts Signals and Output Signal
28x
CPU
A The timer registers are connected to the Memory Bus of the 28x processor.
B The timing of the timers is synchronized to SYSCLKOUT of the processor clock.
The general operation of the CPU-timer is as follows: The 32-bit counter register TIMH:TIM is loaded with
the value in the period register PRDH:PRD. The counter register decrements at the SYSCLKOUT rate of
the 28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The
registers listed in Table 3-18
Table 3-18. CPU-Timers 0, 1, 2 Configuration and Control Registers
Name Address
TIMER0TIM 0x0C00
TIMER0TIMH 0x0C01
TIMER0PRD 0x0C02
TIMER0PRDH 0x0C03
TIMER0TCR 0x0C04
Reserved 0x0C05
TIMER0TPR 0x0C06
TIMER0TPRH 0x0C07
TIMER1TIM 0x0C08
TIMER1TIMH 0x0C09
TIMER1PRD 0x0C0A
TIMER1PRDH 0x0C0B
TIMER1TCR 0x0C0C
Reserved 0x0C0D
TIMER1TPR 0x0C0E
TIMER1TPRH 0x0C0F
TIMER2TIM 0x0C10
TIMER2TIMH 0x0C11
TIMER2PRD 0x0C12
TIMER2PRDH 0x0C13
TIMER2TCR 0x0C14
Reserved 0x0C15
TIMER2TPR 0x0C16
TIMER2TPRH 0x0C17
SPRUFB0C – September 2007 – Revised May 2009
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INT1
PIE
to
INT12
INT13
TINT2
INT14
are used to configure the timers.
Size (x16) Description
1 CPU-Timer 0, Counter Register
1 CPU-Timer 0, Counter Register High
1 CPU-Timer 0, Period Register
1 CPU-Timer 0, Period Register High
1 CPU-Timer 0, Control Register
1
1 CPU-Timer 0, Prescale Register
1 CPU-Timer 0, Prescale Register High
1 CPU-Timer 1, Counter Register
1 CPU-Timer 1, Counter Register High
1 CPU-Timer 1, Period Register
1 CPU-Timer 1, Period Register High
1 CPU-Timer 1, Control Register
1
1 CPU-Timer 1, Prescale Register
1 CPU-Timer 1, Prescale Register High
1 CPU-Timer 2, Counter Register
1 CPU-Timer 2, Counter Register High
1 CPU-Timer 2, Period Register
1 CPU-Timer 2, Period Register High
1 CPU-Timer 2, Control Register
1
1 CPU-Timer 2, Prescale Register
1 CPU-Timer 2, Prescale Register High
TINT0
CPU-TIMER 0
TINT1
CPU-TIMER 1
XINT13
CPU-TIMER 2
(Reserved for DSP/BIOS)
32-Bit CPU Timers 0/1/2
Bit Description
Figure 3-21
Figure 3-22
Figure 3-23
Figure 3-24
Figure 3-25
Figure 3-26
Figure 3-27
Figure 3-21
Figure 3-22
Figure 3-23
Figure 3-24
Figure 3-25
Figure 3-26
Figure 3-27
Figure 3-21
Figure 3-22
Figure 3-23
Figure 3-24
Figure 3-25
Figure 3-26
Figure 3-27
Clocking 61