6.3.1 Procedure For Handling Multiplexed Interrupts - Texas Instruments TMS320x2833 series Reference Manual

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6.3.1 Procedure for Handling Multiplexed Interrupts

The PIE module multiplexes eight peripheral and external pin interrupts into one CPU interrupt. These
interrupts are divided into 12 groups: PIE group 1 - PIE group 12. Each group has an associated enable
PIEIER and flag PIEIFR register. These registers are used to control the flow of interrupts to the CPU. The
PIE module also uses the PIEIER and PIEIFR registers to decode to which interrupt service routine the
CPU should branch.
There are three main rules that should be followed when clearing bits within the PIEIFR and the PIEIER
registers:
Rule 1: Never clear a PIEIFR bit by software
An incoming interrupt may be lost while a write or a read-modify-write operation to the PIEIFR register
takes place. To clear a PIEIFR bit, the pending interrupt must be serviced. If you want to clear the PIEIFR
bit without executing the normal service routine, then use the following procedure:
1. Set the EALLOW bit to allow modification to the PIE vector table.
2. Modify the PIE vector table so that the vector for the peripheral's service routine points to a temporary
ISR. This temporary ISR will only perform a return from interrupt (IRET) operation.
3. Enable the interrupt so that the interrupt will be serviced by the temporary ISR.
4. After the temporary interrupt routine is serviced, the PIEIFR bit will be clear
5. Modify the PIE vector table to re-map the peripheral's service routine to the proper service routine.
6. Clear the EALLOW bit.
Rule 2: Procedure for software-prioritizing interrupts
Use the method found in the C2833x C/C++ Header Files and Peripheral Examples in C (literature
number SPRC530).
a. Use the CPU IER register as a global priority and the individual PIEIER registers for group priorities. In
this case the PIEIER register is only modified within an interrupt. In addition, only the PIEIER for the
same group as the interrupt being serviced is modified. This modification is done while the PIEACK bit
holds additional interrupts back from the CPU.
b. Never disable a PIEIER bit for a group when servicing an interrupt from an unrelated group.
Rule 3: Disabling interrupts using PIEIER
If the PIEIER registers are used to enable and then later disable an interrupt then the procedure described
in Section 6.3.2 must be followed.
SPRUFB0C – September 2007 – Revised May 2009
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Interrupt Sources
Peripheral Interrupt Expansion (PIE) 129