Texas Instruments TMS320F28335 Manuals

Manuals and User Guides for Texas Instruments TMS320F28335. We have 1 Texas Instruments TMS320F28335 manual available for free PDF download: Reference Manual

Texas Instruments TMS320F28335 Reference Manual

Texas Instruments TMS320F28335 Reference Manual (868 pages)

Brand: Texas Instruments | Category: Controller | Size: 7.72 MB

Table of Contents

List of Figures

12
Enhanced Capture (Ecap)

349
- Description
  351
- Multiple Ecap Modules in a C28X System
  352
- Capture and APWM Modes of Operation
  353
- Capture and APWM Operating Mode
  353
- Counter Compare and PRD Effects on the Ecap Output in APWM Mode
  354
- Capture Mode Description
  355
- Ecap Block Diagram
  355
- Event Prescale Control
  356
- Prescale Function Waveforms
  356
- Details of the Continuous/One-Shot Block
  358
- Details of the Counter and Synchronization Block
  359
- Interrupts in Ecap Module
  361
- PWM Waveform Details of APWM Mode Operation
  362
- Time-Base Frequency and Period Calculation
  363
- Application of the Ecap Module
  364
- Capture Sequence for Absolute Time-Stamp and Rising Edge Detect
  364
- Capture Sequence for Absolute Time-Stamp with Rising and Falling Edge Detect
  365
- Capture Sequence for Delta Mode Time-Stamp and Rising Edge Detect
  366
- Capture Sequence for Delta Mode Time-Stamp with Rising and Falling Edge Detect
  367
- Application of the APWM Mode
  368
- PWM Waveform Details of APWM Mode Operation
  368
- Multi-Phase (Channel) Interleaved PWM Example Using 3 Ecap Modules
  369
- ECAP Base Address Table
  371
- Ecap Registers
  371
- 5.8.2 ECAP_REGS Registers
  372
- ECAP_REGS Access Type Codes
  372
- TSCTR Register
  373
- TSCTR Register Field Descriptions
  373
- CTRPHS Register
  374
- CTRPHS Register Field Descriptions
  374
- CAP1 Register
  375
- CAP1 Register Field Descriptions
  375
- CAP2 Register
  376
- CAP2 Register Field Descriptions
  376
- CAP3 Register
  377
- CAP3 Register Field Descriptions
  377
- CAP4 Register
  378
- CAP4 Register Field Descriptions
  378
- ECCTL1 Register
  379
- ECCTL1 Register Field Descriptions
  379
- ECCTL2 Register
  381
- ECCTL2 Register Field Descriptions
  381
- ECEINT Register
  383
- ECEINT Register Field Descriptions
  383
- ECFLG Register
  385
- ECFLG Register Field Descriptions
  385
- ECCLR Register
  387
- ECCLR Register Field Descriptions
  387
- ECFRC Register
  388
- ECFRC Register Field Descriptions
  388
Enhanced Quadrature Encoder Pulse (Eqep)

389
- Introduction
  390
- Optical Encoder Disk
  390
- QEP Encoder Output Signal for Forward/Reverse Movement
  390
- Index Pulse Example
  391
- Configuring Device Pins
  392
- Description
  392
- Functional Block Diagram of the Eqep Peripheral
  393
- 6.3.3 Eqep Memory Map
  394
- Functional Block Diagram of Decoder Unit
  395
- Quadrature Decoder Unit (QDU)
  395
- Quadrature Decoder State Machine
  396
- Quadrature Decoder Truth Table
  396
- Quadrature-Clock and Direction Decoding
  397
- Position Counter and Control Unit (PCCU)
  398
- Position Counter Reset by Index Pulse for 1000 Line Encoder (QPOSMAX = 3999 or 0Xf9F)
  399
- Position Counter Underflow/Overflow (QPOSMAX = 4)
  400
- Software Index Marker for 1000-Line Encoder (QEPCTL[IEL] = 1)
  401
- Strobe Event Latch (QEPCTL[SEL] = 1)
  402
- Eqep Position-Compare Unit
  403
- Eqep Edge Capture Unit
  404
- Eqep Position-Compare Event Generation Points
  404
- Eqep Position-Compare Sync Output Pulse Stretcher
  404
- Eqep Edge Capture Unit
  406
- Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010)
  406
- Eqep Edge Capture Unit - Timing Details
  407
- Eqep Watchdog
  408
- Eqep Watchdog Timer
  408
- Eqep Unit Time Base
  409
- Unit Timer Base
  409
- 6.10 Eqep Registers
  410
- EQEP Base Address Table
  410
- EQEP Interrupt Generation
  410
- Eqep Interrupt Structure
  410
- 6.10.2 EQEP_REGS Registers
  411
- EQEP_REGS Access Type Codes
  411
- QPOSCNT Register
  413
- QPOSCNT Register Field Descriptions
  413
- QPOSINIT Register
  414
- QPOSINIT Register Field Descriptions
  414
- QPOSMAX Register
  415
- QPOSMAX Register Field Descriptions
  415
- QPOSCMP Register
  416
- QPOSCMP Register Field Descriptions
  416
- QPOSILAT Register
  417
- QPOSILAT Register Field Descriptions
  417
- QPOSSLAT Register
  418
- QPOSSLAT Register Field Descriptions
  418
- QPOSLAT Register
  419
- QPOSLAT Register Field Descriptions
  419
- QUTMR Register
  420
- QUTMR Register Field Descriptions
  420
- QUPRD Register
  421
- QUPRD Register Field Descriptions
  421
- QWDTMR Register
  422
- QWDTMR Register Field Descriptions
  422
- QWDPRD Register
  423
- QWDPRD Register Field Descriptions
  423
- QDECCTL Register
  424
- QDECCTL Register Field Descriptions
  424
- QEPCTL Register
  426
- QEPCTL Register Field Descriptions
  426
- QCAPCTL Register
  429
- QCAPCTL Register Field Descriptions
  429
- QPOSCTL Register
  430
- QPOSCTL Register Field Descriptions
  430
- QEINT Register
  431
- QEINT Register Field Descriptions
  431
- QFLG Register
  433
- QFLG Register Field Descriptions
  433
- QCLR Register
  435
- QCLR Register Field Descriptions
  435
- QFRC Register
  437
- QFRC Register Field Descriptions
  437
- QEPSTS Register
  439
- QEPSTS Register Field Descriptions
  439
- QCTMR Register
  441
- QCTMR Register Field Descriptions
  441
- QCPRD Register
  442
- QCPRD Register Field Descriptions
  442
- QCTMRLAT Register
  443
- QCTMRLAT Register Field Descriptions
  443
- QCPRDLAT Register
  444
- QCPRDLAT Register Field Descriptions
  444
- Block Diagram of the ADC Module
  446
- ADC Core Clock and Sample-And-Hold (S/H) Clock
  448
- Clock Chain to the ADC
  448
- Clock Chain to the ADC
  449
- Adcinx Input Model
  450
- Estimated Droop Error from N
  453
- External Bias for 2.048-V External Reference
  455
- Power Options
  456
- Flow Chart of Offset Error Correction Process
  459
- Ideal Code Distribution of Sampled 0-V Reference
  460
- Input Triggers
  461
- Block Diagram of Autosequenced ADC in Cascaded Mode
  463
- Block Diagram of Autosequenced ADC with Dual Sequencers
  464
- Comparison of Single and Cascaded Operating Modes
  465
- Sequential Sampling Mode (SMODE = 0)
  466
- Simultaneous Sampling Mode (SMODE = 1)
  467
- Values for Adcchselseqn Registers (MAX_CONV1 Set to 6)
  470
- Flow Chart for Uninterrupted Autosequenced Mode
  471
- Example of Epwm Triggers to Start the Sequencer
  472
- Values after Second Autoconversion Session
  473
- Values for Adcchselseqn (MAX_CONV1 Set to 2)
  473
- Interrupt Operation During Sequenced Conversions
  475
- ADC Registers
  477
- ADCTRL1 Register
  478
- ADCTRL1 Register Field Descriptions
  478
- ADCTRL2 Register
  480
- ADCTRL2 Register Field Descriptions
  480
- ADCMAXCONV Register
  483
- Bit Selections for MAX_CONV1 for Various Number of Conversions
  483
- ADCCHSELSEQ1 Register
  485
- ADCCHSELSEQ2 Register
  486
- ADCCHSELSEQ3 Register
  487
- Convnn Bit Values and the ADC Input Channels Selected
  487
- ADCCHSELSEQ4 Register
  488
- ADCASEQSR Register
  489
- State of Active Sequencer
  489
- ADCRESULT_0 to ADCRESULT_15 Register
  490
- ADCRESULT_0 to ADCRESULT_15 Register Field Descriptions
  490
- ADCTRL3 Register
  491
- ADCTRL3 Register Field Descriptions
  491
- ADCST Register
  492
- ADCST Register Field Descriptions
  492
- ADCREFSEL Register
  493
- ADCREFSEL Register Field Descriptions
  493
- ADCOFFTRIM Register
  494
- DMA Block Diagram
  497
- Peripheral Interrupt Trigger Input Diagram
  498
- Peripheral Interrupt Trigger Source Options
  499
- DMA State Diagram
  507
- ADC Sync Input Diagram
  509
- DMA Register Summary
  510
- Overrun Detection Logic
  510
- DMACTRL Register
  515
- DMACTRL Register Field Descriptions
  515
- DEBUGCTRL Register
  516
- DEBUGCTRL Register Field Descriptions
  516
- REVISION Register
  517
- REVISION Register Field Descriptions
  517
- PRIORITYCTRL1 Register
  518
- PRIORITYSTAT Register
  519
- MODE Register
  520
- MODE Register Field Descriptions
  520
- PREINTSEL Values
  521
- CONTROL Register
  523
- CONTROL Register Field Descriptions
  523
- BURST_SIZE Register
  526
- BURST_SIZE Register Field Descriptions
  526
- BURST_COUNT Register
  527
- SRC_BURST_STEP Register
  528
- DST_BURST_STEP Register
  529
- TRANSFER_SIZE Register
  530
- TRANSFER_COUNT Register
  531
- TRANSFER_COUNT Register Field Descriptions
  531
- SRC_TRANSFER_STEP Register
  532
- SRC_TRANSFER_STEP Register Field Descriptions
  532
- DST_TRANSFER_STEP Register
  533
- DST_TRANSFER_STEP Register Field Descriptions
  533
- SRC_WRAP_SIZE Register
  534
- SRC_WRAP_COUNT Register
  535
- SRC_WRAP_COUNT Register Field Descriptions
  535
- SRC_WRAP_STEP Register
  536
- DST_WRAP_SIZE Register
  537
- DST_WRAP_COUNT Register
  538
- DST_WRAP_COUNT Register Field Descriptions
  538
- DST_WRAP_STEP Register
  539
- SRC_BEG_ADDR_SHADOW Register
  540
- SRC_BEG_ADDR_SHADOW Register Field Descriptions
  540
- SRC_ADDR_SHADOW Register
  541
- SRC_ADDR_SHADOW Register Field Descriptions
  541
- SRC_BEG_ADDR Register
  542
- SRC_BEG_ADDR Register Field Descriptions
  542
- SRC_ADDR Register
  543
- SRC_ADDR Register Field Descriptions
  543
- DST_BEG_ADDR_SHADOW Register
  544
- DST_BEG_ADDR_SHADOW Register Field Descriptions
  544
- DST_ADDR_SHADOW Register
  545
- DST_ADDR_SHADOW Register Field Descriptions
  545
- DST_BEG_ADDR Register
  546
- DST_BEG_ADDR Register Field Descriptions
  546
- DST_ADDR Register
  547
- DST_ADDR Register Field Descriptions
  547
- SPI CPU Interface
  550
- SPI Module Signal Summary
  550
- SPI Interrupt Flag Modes
  552
- SPI Interrupt Flags and Enable Logic Generation
  552
- SPI Master/Slave Connection
  553
- Serial Peripheral Interface Block Diagram
  554
- SPI Clocking Scheme Selection Guide
  558
- SPICLK Signal Options
  558
- SPI: SPICLK-LSPCLK Characteristic When (BRR + 1) Is Odd, BRR > 3, and CLKPOLARITY
  559
- Five Bits Per Character
  561
- SPI Base Address Table
  562
- 9.5.2 SPI_REGS Registers
  563
- SPI_REGS Access Type Codes
  563
- SPICCR Register
  564
- SPICCR Register Field Descriptions
  564
- SPICTL Register
  566
- SPICTL Register Field Descriptions
  566
- SPISTS Register
  568
- SPISTS Register Field Descriptions
  568
- SPIBRR Register
  570
- SPIBRR Register Field Descriptions
  570
- SPIRXEMU Register
  571
- SPIRXEMU Register Field Descriptions
  571
- SPIRXBUF Register
  572
- SPIRXBUF Register Field Descriptions
  572
- SPITXBUF Register
  573
- SPITXBUF Register Field Descriptions
  573
- SPIDAT Register
  574
- SPIDAT Register Field Descriptions
  574
- SPIFFTX Register
  575
- SPIFFTX Register Field Descriptions
  575
- SPIFFRX Register
  577
- SPIFFRX Register Field Descriptions
  577
- SPIFFCT Register
  579
- SPIFFCT Register Field Descriptions
  579
- SPIPRI Register
  580
- SPIPRI Register Field Descriptions
  580
- SCI CPU Interface
  582
- Serial Communications Interface (SCI) Module Block Diagram
  583
- SCI Module Signal Summary
  584
- Programming the Data Format Using SCICCR
  585
- Typical SCI Data Frame Formats
  585
- Idle-Line Multiprocessor Communication Format
  587
- Double-Buffered WUT and TXSHF
  588
- Address-Bit Multiprocessor Communication Format
  589
- SCI Asynchronous Communications Format
  590
- SCI RX Signals in Communication Modes
  590
- SCI TX Signals in Communications Mode
  591
- Asynchronous Baud Register Values for Common SCI Bit Rates
  592
- SCI FIFO Interrupt Flags and Enable Logic
  593
- SCI Interrupt Flags
  594
- SCI_REGS Access Type Codes
  596
- SCI_REGS Registers
  596
- SCICCR Register
  597
- SCICCR Register Field Descriptions
  597
- SCICTL1 Register
  599
- SCICTL1 Register Field Descriptions
  599
- SCIHBAUD Register
  601
- SCIHBAUD Register Field Descriptions
  601
- SCILBAUD Register
  602
- SCILBAUD Register Field Descriptions
  602
- SCICTL2 Register
  603
- SCICTL2 Register Field Descriptions
  603
- SCIRXST Register
  605
- SCIRXST Register Field Descriptions
  605
- SCIRXEMU Register
  607
- SCIRXEMU Register Field Descriptions
  607
- SCIRXBUF Register
  608
- SCIRXBUF Register Field Descriptions
  608
- SCITXBUF Register
  609
- SCITXBUF Register Field Descriptions
  609
- SCIFFTX Register
  610
- SCIFFTX Register Field Descriptions
  610
- SCIFFRX Register
  612
- SCIFFRX Register Field Descriptions
  612
- SCIFFCT Register
  614
- SCIFFCT Register Field Descriptions
  614
- SCIPRI Register
  615
- SCIPRI Register Field Descriptions
  615
- Multiple I2C Modules Connected
  617
- Clocking Diagram for the I2C Module
  619
- I2C Module Conceptual Block Diagram
  619
- Dependency of Delay D on the Divide-Down Value IPSC
  620
- The Roles of the Clock Divide-Down Values (ICCL and ICCH)
  620
- Bit Transfer on the I2C Bus
  621
- Operating Modes of the I2C Module
  621
- Master-Transmitter/Receiver Bus Activity Defined by the RM, STT, and STP Bits of I2CMDR
  622
- I2C Module START and STOP Conditions
  623
- I2C Module 10-Bit Addressing Format (FDF = 0, XA = 1 in I2CMDR)
  624
- I2C Module 7-Bit Addressing Format (FDF = 0, XA = 0 in I2CMDR)
  624
- I2C Module Data Transfer (7-Bit Addressing with 8-Bit Data Configuration Shown)
  624
- How the MST and FDF Bits of I2CMDR Affect the Role of the TRX Bit of I2CMDR
  625
- I2C Module Free Data Format (FDF = 1 in I2CMDR)
  625
- Repeated START Condition (in this Case, 7-Bit Addressing Format)
  625
- Synchronization of Two I2C Clock Generators During Arbitration
  626
- Ways to Generate a NACK Bit
  626
- Arbitration Procedure between Two Master-Transmitters
  627
- Pin Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit
  628
- Descriptions of the Basic I2C Interrupt Requests
  629
- Enable Paths of the I2C Interrupt Requests
  629
- Backwards Compatibility Mode Bit, Slave Transmitter
  630
- I2C_Fifo_Interrupt
  630
- I2C Base Address Table
  632
- I2C_REGS Access Type Codes
  633
- I2C_REGS Registers
  633
- I2COAR Register
  634
- I2COAR Register Field Descriptions
  634
I2Cier Register Field Descriptions/Reserved R 0H

635

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