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Texas Instruments TMS320C674X User Manual

Texas Instruments TMS320C674X User Manual

Processor ethernet media access controller (emac)/ management data input/output (mdio) module
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TMS320C674x/OMAP-L1x Processor
Ethernet Media Access Controller (EMAC)/
Management Data Input/Output (MDIO) Module
User's Guide
Literature Number: SPRUFL5B
April 2011

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  • Page 1 TMS320C674x/OMAP-L1x Processor Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) Module User's Guide Literature Number: SPRUFL5B April 2011...
  • Page 2 SPRUFL5B – April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated...

  • Page 3: Table Of Contents

    EMAC Control Module Interrupt Core Transmit Interrupt Status Registers (C0TXSTAT-C2TXSTAT) 3.11 EMAC Control Module Interrupt Core Miscellaneous Interrupt Status Registers (C0MISCSTAT-C2MISCSTAT) 3.12 EMAC Control Module Interrupt Core Receive Interrupts Per Millisecond Registers SPRUFL5B – April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Table of Contents...
  • Page 4 5.27 Receive Channel Flow Control Threshold Registers (RX0FLOWTHRESH-RX7FLOWTHRESH) 5.28 Receive Channel Free Buffer Count Registers (RX0FREEBUFFER-RX7FREEBUFFER) 5.29 MAC Control Register (MACCONTROL) 5.30 MAC Status Register (MACSTATUS) Contents © 2011, Texas Instruments Incorporated www.ti.com SPRUFL5B – April 2011 Submit Documentation Feedback...
  • Page 5 Receive Channel DMA Head Descriptor Pointer Registers (RX0HDP-RX7HDP) 5.48 Transmit Channel Completion Pointer Registers (TX0CP-TX7CP) 5.49 Receive Channel Completion Pointer Registers (RX0CP-RX7CP) 5.50 Network Statistics Registers Appendix A Glossary Appendix B Revision History SPRUFL5B – April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Contents...
  • Page 6 Receive Revision ID Register (RXREVID) Receive Control Register (RXCONTROL) Receive Teardown Register (RXTEARDOWN) Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) List of Figures List of Figures © 2011, Texas Instruments Incorporated www.ti.com SPRUFL5B – April 2011 Submit Documentation Feedback...
  • Page 7 Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Transmit Channel n Completion Pointer Register (TXnCP) Receive Channel n Completion Pointer Register (RXnCP) Statistics Register SPRUFL5B – April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated List of Figures...
  • Page 8 Receive Teardown Register (RXTEARDOWN) Field Descriptions Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions List of Tables List of Tables © 2011, Texas Instruments Incorporated www.ti.com SPRUFL5B – April 2011 Submit Documentation Feedback...
  • Page 9 Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Field Descriptions Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions Physical Layer Definitions Document Revision History SPRUFL5B – April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated List of Tables...

  • Page 10: Preface

    – Reserved bits in a register figure designate a bit that is used for future device expansion. Related Documentation From Texas Instruments The following documents describe the TMS320C674x Digital Signal Processors (DSPs) and OMAP-L1x Applications Processors. Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com.
  • Page 11 ARM interrupt controller (AINTC), and system configuration module. SPRUFK9 — TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide. Provides an overview and briefly describes the peripherals available on the TMS320C674x Digital Signal Processors (DSPs) and OMAP-L1x Applications Processors. SPRUFK5 — TMS320C674x DSP Megamodule Reference Guide. Describes the TMS320C674x digital signal processor (DSP) megamodule.

  • Page 12: Introduction

    Programmable interrupt logic permits the software driver to restrict the generation of back-to-back interrupts, which allows more work to be performed in a single call to the interrupt service routine. EMAC/MDIO Module EMAC/MDIO Module © 2011, Texas Instruments Incorporated User's Guide SPRUFL5B – April 2011 SPRUFL5B – April 2011...

  • Page 13: Functional Block Diagram

    Register Bus SPRUFL5B – April 2011 Submit Documentation Feedback EMAC Sub System Control Module 8K CPPI Master Interrupt Combiner EMAC MDIO Interrupts Interrupts EMAC MDIO Module Module MII/RMII Bus MDIO Bus © 2011, Texas Instruments Incorporated Introduction Interrupts EMAC/MDIO Module...

  • Page 14: Industry Standard(S) Compliance Statement

    The EMAC module does not include a transmit error (MTXER) pin. In the case of transmit error, CRC inversion is used to negate the validity of the transmitted frame. EMAC/MDIO Module © 2011, Texas Instruments Incorporated www.ti.com SPRUFL5B – April 2011...

  • Page 15: Ethernet Configuration-Mii Connections

    SPRUFL5B – April 2011 Submit Documentation Feedback MII_TXCLK MII_TXD[3−0] MII_TXEN MII_COL MII_CRS Physical layer MII_RXCLK device MII_RXD[3−0] (PHY) MII_RXDV MII_RXER MDIO_CLK MDIO_D © 2011, Texas Instruments Incorporated Architecture Table 1. For more 2.5 MHz 25 MHz Transformer RJ−45 EMAC/MDIO Module...

  • Page 16: Ethernet Configuration-Rmii Connections

    EMAC/MDIO Module RMII_TXD[1-0] RMII_TXEN 50 MHz RMII_MHZ_50_CLK Physical RMII_RXD[1-0] Layer Transformer Device RMII_CRS_DV (PHY) RMII_RXER RJ-45 MDIO_CLK MDIO_D © 2011, Texas Instruments Incorporated www.ti.com Table 2. For more SPRUFL5B – April 2011 Submit Documentation Feedback...

  • Page 17: Ethernet Protocol Overview

    60 to 1514 bytes of the packet data. Note that this 4-byte field may or may not be included as part of the packet data, depending on how the EMAC is configured. © 2011, Texas Instruments Incorporated Architecture 46−1500...

  • Page 18: Programming Interface

    Word Offset EMAC/MDIO Module Table Figure 5. Basic Descriptor Format Bit Fields 16 15 Next Descriptor Pointer Buffer Pointer Buffer Offset Flags © 2011, Texas Instruments Incorporated www.ti.com Figure Buffer Length Packet Length SPRUFL5B – April 2011 Submit Documentation Feedback...

  • Page 19: Typical Descriptor Linked List

    1514 pNext pBuffer −−− −−− pNext pBuffer −−− pNext (NULL) pBuffer 1514 1514 © 2011, Texas Instruments Incorporated Architecture Section 2.5.4 Section 2.5.5. Packet A 60 bytes Packet B Fragment 1 512 bytes Packet B Fragment 2 502 bytes...
  • Page 20 HDP that started the process. This process applies when adding packets to a transmit list, and empty buffers to a receive list. EMAC/MDIO Module © 2011, Texas Instruments Incorporated www.ti.com Section 2.5.1. The lists used by SPRUFL5B –...
  • Page 21 SPRUFL5B – April 2011 Submit Documentation Feedback Section 2.5.2. (Figure 7) is a contiguous block of four 32-bit data words aligned on a Example 1 © 2011, Texas Instruments Incorporated Architecture Section 2.5.1, using the linked list shows the transmit buffer EMAC/MDIO Module...

  • Page 22: Transmit Buffer Descriptor Format

    #define EMAC_DSC_FLAG_TDOWNCMPLT 0x08000000u #define EMAC_DSC_FLAG_PASSCRC 0x04000000u EMAC/MDIO Module Figure 7. Transmit Buffer Descriptor Format Next Descriptor Pointer Buffer Pointer 16 15 PASSCRC Packet Length © 2011, Texas Instruments Incorporated www.ti.com Buffer Length Reserved SPRUFL5B – April 2011 Submit Documentation Feedback...
  • Page 23 EOP flag. This bit is set by the software application and is not altered by the EMAC. SPRUFL5B – April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Architecture EMAC/MDIO Module...
  • Page 24 CRC bytes, as they are part of the valid packet data. Note that this flag is valid on SOP descriptors only. EMAC/MDIO Module © 2011, Texas Instruments Incorporated www.ti.com SPRUFL5B – April 2011 Submit Documentation Feedback...

  • Page 25: Receive Buffer Descriptor Format

    8) is a contiguous block of four 32-bit data words aligned on a Example 2 Figure 8. Receive Buffer Descriptor Format Next Descriptor Pointer Buffer Pointer 16 15 TDOWNCMPLT OVERRUN CODEERROR Packet Length © 2011, Texas Instruments Incorporated Architecture shows the receive buffer Buffer Length PASSCRC JABBER OVERSIZE ALIGNERROR CRCERROR NOMATCH...
  • Page 26 The range of legal values for the BUFFEROFFSET register is 0 to (Buffer Length – 1) for the smallest value of buffer length for all descriptors in the list. EMAC/MDIO Module © 2011, Texas Instruments Incorporated www.ti.com SPRUFL5B – April 2011...
  • Page 27 This would happen under device driver reset or shutdown conditions. The EMAC sets this bit in the descriptor of the first free buffer when the tear down occurs. No additional queue processing is performed. SPRUFL5B – April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Architecture EMAC/MDIO Module...
  • Page 28 EMAC’s address match criteria and was not discarded because the RXCAFEN bit was set in the RXMBPENABLE. Although the packet is a valid Ethernet data packet, it was only received because the EMAC is in promiscuous mode. EMAC/MDIO Module © 2011, Texas Instruments Incorporated www.ti.com SPRUFL5B – April 2011 Submit Documentation Feedback...

  • Page 29: Emac Control Module

    SPRUFL5B – April 2011 Submit Documentation Feedback 9) interfaces the EMAC and MDIO modules to the rest of the system, Arbiter and bus switches 8K byte descriptor memory Configuration registers Interrupt logic © 2011, Texas Instruments Incorporated Architecture Interrupts to CPU EMAC/MDIO Module...

  • Page 30: Mdio Module

    • MDIO clock generator • Global PHY detection and link state monitoring • Active PHY monitoring • PHY register user access EMAC/MDIO Module © 2011, Texas Instruments Incorporated www.ti.com SPRUFL5B – April 2011 Submit Documentation Feedback...

  • Page 31: Mdio Module Block Diagram

    USERACCESSn allows the software to submit the access requests for the PHY connected to the device. SPRUFL5B – April 2011 Submit Documentation Feedback Figure 10. MDIO Module Block Diagram MDIO clock generator monitoring Control registers and logic © 2011, Texas Instruments Incorporated Architecture MDCLK MDIO interface MDIO polling EMAC/MDIO Module...
  • Page 32 USERACCESSn before initiating a new transaction, to ensure that the previous transaction has completed. The application software can use the ACK bit in USERACCESSn to determine the status of a read transaction. EMAC/MDIO Module © 2011, Texas Instruments Incorporated www.ti.com SPRUFL5B – April 2011 Submit Documentation Feedback...
  • Page 33 (USERINTMASKSET), then the bit is also set in the MDIO user command complete interrupt register (USERINTMASKED) and an interrupt is triggered on the CPU. SPRUFL5B – April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Architecture EMAC/MDIO Module...
  • Page 34 Synchronize operation (make sure read/write is idle) Wait for read to complete and return data read Section 2.7.2.3). Since the MDIO PHY alive status register (ALIVE) is © 2011, Texas Instruments Incorporated www.ti.com Example 3 SPRUFL5B – April 2011 Submit Documentation Feedback...

  • Page 35: Emac Module

    FIFO. The MAC receiver also detects errors and passes statistics to the statistics RAM. SPRUFL5B – April 2011 Submit Documentation Feedback Receive address Receive FIFO receiver State Statistics Transmit FIFO transmitter © 2011, Texas Instruments Incorporated Architecture SYNC RMII EMAC/MDIO Module...
  • Page 36 Accepted packets are then written to the receive FIFO in bursts of 64-byte cells. The receive DMA controller then writes the packet data to memory. Receive statistics are counted by the statistics block. EMAC/MDIO Module © 2011, Texas Instruments Incorporated www.ti.com SPRUFL5B – April 2011 Submit Documentation Feedback...

  • Page 37: Mac Interface

    Two forms of receive buffer flow control are available: • Collision-based flow control for half-duplex mode • IEEE 802.3x pause frames flow control for full-duplex mode SPRUFL5B – April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Architecture EMAC/MDIO Module...
  • Page 38 If the RXBUFFERFLOWEN bit in MACCONTROL is cleared to 0 while the pause time is nonzero, then the pause time is cleared to 0 and a zero count pause frame is sent. EMAC/MDIO Module © 2011, Texas Instruments Incorporated www.ti.com SPRUFL5B – April 2011...
  • Page 39 MII_TXEN is deasserted, then 96 bit times (approximately, but not less) is measured from MII_CRS. 2.9.2.5 Back Off The EMAC implements the 802.3 binary exponential back-off algorithm. SPRUFL5B – April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Architecture EMAC/MDIO Module...
  • Page 40 The MAC operates at 10 Mbps or 100 Mbps, in half-duplex or full-duplex mode, and with or without pause frame support as configured by the host. EMAC/MDIO Module © 2011, Texas Instruments Incorporated www.ti.com SPRUFL5B – April 2011 Submit Documentation Feedback...

  • Page 41: 2.10 Packet Receive Operation

    (MACADDRLO). Since all eight MAC addresses share the upper 40 bits of address, MACADDRHI needs to be written only the first time (for the first channel configured). SPRUFL5B – April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Architecture EMAC/MDIO Module...
  • Page 42 (note that there is no buffer descriptor in this case). Software may read RXnCP to determine if the interrupt was due to a commanded teardown. The read value is FFFF FFFCh, if the interrupt was due to a teardown command. EMAC/MDIO Module © 2011, Texas Instruments Incorporated www.ti.com SPRUFL5B – April 2011 Submit Documentation Feedback...
  • Page 43 64 bytes and the value in the receive maximum length register (RXMAXLEN) bytes in length inclusive and contain no code, align, or CRC errors. SPRUFL5B – April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Architecture EMAC/MDIO Module...

  • Page 44: Receive Frame Treatment Summary

    Proper/oversize/jabber/code/align/CRC data and control frames transferred to address match channel. No undersized/fragment frames are transferred. All address matching frames with and without errors transferred to the address match channel © 2011, Texas Instruments Incorporated www.ti.com SPRUFL5B – April 2011 Submit Documentation Feedback...

  • Page 45: Middle Of Frame Overrun Treatment

    The appropriate overrun statistic(s) is incremented and the OVERRUN flag is set in the SOP buffer descriptor. Note that the RXMAXLEN number of bytes cannot be reached for an overrun to occur (it would be truncated). © 2011, Texas Instruments Incorporated Architecture EMAC/MDIO Module...

  • Page 46: 2.11 Packet Transmit Operation

    (TXnCP) to determine if the interrupt was due to a commanded teardown. The read value is FFFF FFFCh, if the interrupt was due to a teardown command. EMAC/MDIO Module © 2011, Texas Instruments Incorporated www.ti.com SPRUFL5B – April 2011 Submit Documentation Feedback...

  • Page 47: 2.12 Receive And Transmit Latency

    The short-term average, each 64-byte memory read/write request from the EMAC must be serviced in no more than 5.12 μs. • Any single latency event in request servicing can be no longer than (5.12 × TXCELLTHRESH) μs. SPRUFL5B – April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Architecture EMAC/MDIO Module...

  • Page 48: 2.14 Reset Considerations

    MAC status register (MACSTATUS) that gives information about the type of software error that needs to be corrected. For detailed information on error interrupts, see EMAC/MDIO Module Section Section 2.15. © 2011, Texas Instruments Incorporated www.ti.com 2.17. Section 2.16.1.4. SPRUFL5B – April 2011...

  • Page 49: 2.15 Initialization

    Also, a PHY can take up to 3 seconds to negotiate a link. Thus, it is advisable to run the MDIO software off a time-based event rather than polling. For more information on PHY control registers, see your PHY device documentation. SPRUFL5B – April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Architecture EMAC/MDIO Module...
  • Page 50 TXEN bit in TXCONTROL. Then set the GMIIEN bit in MACCONTROL. 17. Enable the device interrupt in EMAC control module registers CnRXTHRESHEN, CnRXEN, CnTXEN, and CnMISCEN. EMAC/MDIO Module © 2011, Texas Instruments Incorporated www.ti.com SPRUFL5B – April 2011 Submit Documentation Feedback...

  • Page 51: 2.16 Interrupt Support

    (RXINTMASKCLEAR). The raw and masked receive interrupt status may be read by reading the receive interrupt status (unmasked) register (RXINTSTATRAW) and the receive interrupt status (masked) register (RXINTSTATMASKED), respectively. SPRUFL5B – April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Architecture EMAC/MDIO Module...
  • Page 52 Ownership bit not set in SOP buffer • Zero next buffer descriptor pointer with EOP • Zero buffer pointer • Zero buffer length • Packet length error EMAC/MDIO Module © 2011, Texas Instruments Incorporated www.ti.com SPRUFL5B – April 2011 Submit Documentation Feedback...
  • Page 53 The application software must acknowledge the EMAC control module after receiving MDIO interrupts by writing the appropriate CnMISC key to the EMAC End-Of-Interrupt Vector (MACEOIVECTOR). See Section 5.12 for the acknowledge key values. SPRUFL5B – April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Architecture EMAC/MDIO Module...
  • Page 54 28 interrupt signals: TXPENDn, RXPENDn, RXTHRESHPENDn, STATPEND, HOSTPEND, LINKINT0, and USERINT0. For more details on the interrupt mapping, see your device-specific System Reference Guide. EMAC/MDIO Module © 2011, Texas Instruments Incorporated www.ti.com Section 5.12 SPRUFL5B – April 2011 Submit Documentation Feedback...

  • Page 55: 2.17 Power Management

    SOFT and FREE bits affect the operation of the emulation suspend. NOTE: Emulation suspend has not been tested. SOFT FREE SPRUFL5B – April 2011 Submit Documentation Feedback Table 7. Emulation Control Description Normal operation Emulation suspend Normal operation © 2011, Texas Instruments Incorporated Architecture EMAC/MDIO Module...

  • Page 56: Emac Control Module Registers

    EMAC Control Module Interrupt Core 2 Receive Interrupt Status Register EMAC Control Module Interrupt Core 2 Transmit Interrupt Status Register EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Status Register © 2011, Texas Instruments Incorporated www.ti.com Section Section 3.1 Section 3.2 Section 3.3 Section 3.4...

  • Page 57: Emac Control Module Revision Id Register (Revid)

    EMAC Control Module Interrupt Core 2 Receive Interrupts Per Millisecond Register EMAC Control Module Interrupt Core 2 Transmit Interrupts Per Millisecond Register Figure 12 R-4EC8 0100h © 2011, Texas Instruments Incorporated EMAC Control Module Registers Section Section 3.12 Section 3.13 Section 3.12 Section 3.13...

  • Page 58: Emac Control Module Software Reset Register (Softreset)

    Software reset bit for the EMAC Control Module. Clears the interrupt status, control registers, and CPPI Ram on the clock cycle following a write of 1. No software reset. Perform a software reset. EMAC/MDIO Module Reserved Reserved © 2011, Texas Instruments Incorporated www.ti.com Figure 13 and described RESET R/W-0 SPRUFL5B – April 2011...

  • Page 59: Emac Control Module Interrupt Control Register (Intcontrol)

    Pacing for RX interrupts on Core 0 enabled. Reserved Number of internal EMAC module reference clock periods within a 4 μs time window (see your device-specific data manual for information). © 2011, Texas Instruments Incorporated EMAC Control Module Registers Figure 14 and described...

  • Page 60: Emac Control Module Interrupt Core Receive Threshold Interrupt Enable Registers (C0Rxthreshen-C2Rxthreshen)

    CnRXTHRESHPULSE generation is enabled for RX Channel 1. Enable CnRXTHRESHPULSE interrupt generation for RX Channel 0 CnRXTHRESHPULSE generation is disabled for RX Channel 0. CnRXTHRESHPULSE generation is enabled for RX Channel 0. © 2011, Texas Instruments Incorporated www.ti.com RXCH2 RXCH1...

  • Page 61: Emac Control Module Interrupt Core Receive Interrupt Enable Registers (C0Rxen-C2Rxen)

    CnRXPULSE generation is disabled for RX Channel 0. CnRXPULSE generation is enabled for RX Channel 0. SPRUFL5B – April 2011 Submit Documentation Feedback Reserved Reserved RXCH4EN RXCH3EN RXCH2EN R/W-0 R/W-0 R/W-0 © 2011, Texas Instruments Incorporated EMAC Control Module Registers RXCH1EN RXCH0EN R/W-0 R/W-0 EMAC/MDIO Module...

  • Page 62: Emac Control Module Interrupt Core Transmit Interrupt Enable Registers (C0Txen-C2Txen)

    CnTXPULSE generation is disabled for TX Channel 0. CnTXPULSE generation is enabled for TX Channel 0. EMAC/MDIO Module Reserved Reserved TXCH4EN TXCH3EN TXCH2EN R/W-0 R/W-0 R/W-0 © 2011, Texas Instruments Incorporated www.ti.com TXCH1EN TXCH0EN R/W-0 R/W-0 SPRUFL5B – April 2011 Submit Documentation Feedback...

  • Page 63: Emac Control Module Interrupt Core Miscellaneous Interrupt Enable Registers (C0Miscen-C2Miscen)

    CnMISCPULSE generation is enabled for MDIO LINKINT0 interrupts. Enable CnMISCPULSE interrupt generation when MDIO USERINT0 interrupts (corresponding to USERACCESS0) are generated CnMISCPULSE generation is disabled for MDIO USERINT0. CnMISCPULSE generation is enabled for MDIO USERINT0. © 2011, Texas Instruments Incorporated EMAC Control Module Registers LINKINT0EN USERINT0EN R/W-0...

  • Page 64: Emac Control Module Interrupt Core Receive Threshold Interrupt Status Registers (C0Rxthreshstat-C2Rxthreshstat)

    Interrupt status for RX Channel 0 masked by the CnRXTHRESHEN register RX Channel 0 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt. RX Channel 0 satisfies conditions to generate a CnRXTHRESHPULSE interrupt. © 2011, Texas Instruments Incorporated www.ti.com RXCH2THRESH...

  • Page 65: Emac Control Module Interrupt Core Receive Interrupt Status Registers (C0Rxstat-C2Rxstat)

    Interrupt status for RX Channel 0 masked by the CnRXEN register RX Channel 0 does not satisfy conditions to generate a CnRXPULSE interrupt. RX Channel 0 satisfies conditions to generate a CnRXPULSE interrupt. © 2011, Texas Instruments Incorporated EMAC Control Module Registers RXCH2STAT...

  • Page 66: Emac Control Module Interrupt Core Transmit Interrupt Status Registers (C0Txstat-C2Txstat)

    Interrupt status for TX Channel 0 masked by the CnTXEN register TX Channel 0 does not satisfy conditions to generate a CnTXPULSE interrupt. TX Channel 0 satisfies conditions to generate a CnTXPULSE interrupt. © 2011, Texas Instruments Incorporated www.ti.com TXCH2STAT...

  • Page 67: Emac Control Module Interrupt Core Miscellaneous Interrupt Status Registers (C0Miscstat-C2Miscstat)

    Interrupt status for MDIO USERINT0 masked by the CnMISCEN register MDIO USERINT0 does not satisfy conditions to generate a CnMISCPULSE interrupt. MDIO USERINT0 satisfies conditions to generate a CnMISCPULSE interrupt. © 2011, Texas Instruments Incorporated EMAC Control Module Registers LINKINT0STAT...

  • Page 68: 3.12 Emac Control Module Interrupt Core Receive Interrupts Per Millisecond Registers

    = previous_pace_counter - 1; else if(interrupt_count != 0) pace_counter = previous_pace_counter/2; else pace_counter = 0; previous_pace_counter = pace_counter; EMAC/MDIO Module Table 20 (CnRXIMAX) Reserved (CnRXIMAX) © 2011, Texas Instruments Incorporated www.ti.com RXIMAX R/W-0 SPRUFL5B – April 2011 Submit Documentation Feedback...

  • Page 69: Emac Control Module Interrupt Core Transmit Interrupts Per Millisecond Registers (C0Tximax-C2Tximax)

    = previous_pace_counter - 1; else if(interrupt_count != 0) pace_counter = previous_pace_counter/2; else pace_counter = 0; previous_pace_counter = pace_counter; SPRUFL5B – April 2011 Submit Documentation Feedback Table 21 (CnTXIMAX) Reserved (CnTXIMAX) © 2011, Texas Instruments Incorporated EMAC Control Module Registers TXIMAX R/W-0 EMAC/MDIO Module...

  • Page 70: Mdio Registers

    MDIO User Access Register 1 MDIO User PHY Select Register 1 Figure 25 and described in Figure 25. MDIO Revision ID Register (REVID) R-0007 0104h © 2011, Texas Instruments Incorporated www.ti.com Section Section 4.1 Section 4.2 Section 4.3 Section 4.4 Section 4.5...

  • Page 71: Mdio Control Register (Control)

    Clock Divider bits. This field specifies the division ratio between the peripheral clock and the frequency of MDIO_CLK. MDIO_CLK is disabled when CLKDIV is cleared to 0. MDIO_CLK frequency = peripheral clock frequency/(CLKDIV + 1). © 2011, Texas Instruments Incorporated MDIO Registers Table...

  • Page 72: Phy Acknowledge Status Register (Alive)

    The PHY with the corresponding address has a link and the PHY acknowledges the read transaction. EMAC/MDIO Module Figure 27 ALIVE R/W1C-0 Figure 28 and described in Figure 28. PHY Link Status Register (LINK) LINK © 2011, Texas Instruments Incorporated www.ti.com and described in Table Table SPRUFL5B – April 2011 Submit Documentation Feedback...

  • Page 73: Mdio Link Status Change Interrupt (Unmasked) Register (Linkintraw)

    An MDIO link change event (change in the LINK register) corresponding to the PHY address in MDIO user PHY select register USERPHYSEL0 SPRUFL5B – April 2011 Submit Documentation Feedback Reserved Reserved Field Descriptions © 2011, Texas Instruments Incorporated MDIO Registers Figure 29 USERPHY1 USERPHY0 R/W1C-0 R/W1C-0...

  • Page 74: Mdio Link Status Change Interrupt (Masked) Register (Linkintmasked)

    An MDIO link change event (change in the LINK register) corresponding to the PHY address in MDIO user PHY select register USERPHYSEL0 and the LINKINTENB bit in USERPHYSEL0 is set to 1. EMAC/MDIO Module Reserved Reserved Field Descriptions © 2011, Texas Instruments Incorporated www.ti.com Figure 30 USERPHY1 USERPHY0 R/W1C-0 R/W1C-0 SPRUFL5B –...

  • Page 75: Mdio User Command Complete Interrupt (Unmasked) Register (Userintraw)

    Writing a 1 will clear the event, writing a 0 has no effect. No MDIO user command complete event. The previously scheduled PHY read or write command using MDIO user access register USERACCESS0 has completed. © 2011, Texas Instruments Incorporated MDIO Registers Figure 31 USERACCESS1 USERACCESS0...

  • Page 76: Mdio User Command Complete Interrupt (Masked) Register (Userintmasked)

    No MDIO user command complete event. The previously scheduled PHY read or write command using MDIO user access register USERACCESS0 has completed and the corresponding bit in USERINTMASKSET is set to 1. © 2011, Texas Instruments Incorporated www.ti.com USERACCESS1 USERACCESS0...

  • Page 77: Mdio User Command Complete Interrupt Mask Set Register (Userintmaskset)

    USERACCESS0 is disabled if the corresponding bit is 0. Writing a 0 to this bit has no effect. MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is disabled. MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is enabled. © 2011, Texas Instruments Incorporated MDIO Registers USERACCESS1 USERACCESS0 R/W1S-0 R/W1S-0...

  • Page 78: Mdio User Command Complete Interrupt Mask Clear Register (Userintmaskclear)

    MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is enabled. MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is disabled. © 2011, Texas Instruments Incorporated www.ti.com USERACCESS1 USERACCESS0 R/W1C-0 R/W1C-0 SPRUFL5B –...

  • Page 79: Mdio User Access Register 0 (Useraccess0)

    User data bits. These bits specify the data value read from or to be written to the specified PHY register. SPRUFL5B – April 2011 Submit Documentation Feedback Figure 35 REGADR R/W-0 DATA R/W-0 © 2011, Texas Instruments Incorporated MDIO Registers and described in Table PHYADR R/W-0 EMAC/MDIO Module...

  • Page 80: Mdio User Phy Select Register 0 (Userphysel0)

    PHYADRMON 0-1Fh PHY address whose link status is to be monitored. EMAC/MDIO Module Figure 36 Reserved LINKSEL LINKINTENB Rsvd R/W-0 R/W-0 © 2011, Texas Instruments Incorporated www.ti.com and described in Table PHYADRMON R/W-0 SPRUFL5B – April 2011 Submit Documentation Feedback...

  • Page 81: Mdio User Access Register 1 (Useraccess1)

    User data bits. These bits specify the data value read from or to be written to the specified PHY register. SPRUFL5B – April 2011 Submit Documentation Feedback Figure 37 REGADR R/W-0 DATA R/W-0 © 2011, Texas Instruments Incorporated MDIO Registers and described in Table PHYADR R/W-0 EMAC/MDIO Module...

  • Page 82: Mdio User Phy Select Register 1 (Userphysel1)

    PHYADRMON 0-1Fh PHY address whose link status is to be monitored. EMAC/MDIO Module Figure 38 Reserved LINKSEL LINKINTENB Rsvd R/W-0 R/W-0 © 2011, Texas Instruments Incorporated www.ti.com and described in Table PHYADRMON R/W-0 SPRUFL5B – April 2011 Submit Documentation Feedback...

  • Page 83: Emac Module Registers

    Receive Channel 4 Free Buffer Count Register Receive Channel 5 Free Buffer Count Register Receive Channel 6 Free Buffer Count Register Receive Channel 7 Free Buffer Count Register MAC Control Register © 2011, Texas Instruments Incorporated EMAC Module Registers Section Section 5.1 Section 5.2 Section 5.3...
  • Page 84 Receive Channel 2 Completion Pointer Register Receive Channel 3 Completion Pointer Register Receive Channel 4 Completion Pointer Register Receive Channel 5 Completion Pointer Register Receive Channel 6 Completion Pointer Register © 2011, Texas Instruments Incorporated www.ti.com Section Section 5.30 Section 5.31 Section 5.32...
  • Page 85 Transmit and Receive 1024 to RXMAXLEN Octet Frames Register Network Octet Frames Register Receive FIFO or DMA Start of Frame Overruns Register Receive FIFO or DMA Middle of Frame Overruns Register Receive DMA Overruns Register © 2011, Texas Instruments Incorporated EMAC Module Registers Section Section 5.49 Section 5.50.1 Section 5.50.2...

  • Page 86: Transmit Revision Id Register (Txrevid)

    Transmit is disabled. Transmit is enabled. EMAC/MDIO Module Figure 39 and described in TXREV R-4EC0 020Dh Figure 40 and described in Reserved Reserved © 2011, Texas Instruments Incorporated www.ti.com Table Table TXEN R/W-0 SPRUFL5B – April 2011 Submit Documentation Feedback...

  • Page 87: Transmit Teardown Register (Txteardown)

    Teardown transmit channel 4 Teardown transmit channel 5 Teardown transmit channel 6 Teardown transmit channel 7 SPRUFL5B – April 2011 Submit Documentation Feedback Figure 41 Reserved Reserved © 2011, Texas Instruments Incorporated EMAC Module Registers and described in Table TXTDNCH R/W-0 EMAC/MDIO Module...

  • Page 88: Receive Revision Id Register (Rxrevid)

    Figure 42 RXREV R-4EC0 020Dh Description Receive module revision Current receive revision value Figure 43 Reserved Reserved © 2011, Texas Instruments Incorporated www.ti.com and described in Table and described in Table RXEN R/W-0 SPRUFL5B – April 2011 Submit Documentation Feedback...

  • Page 89: Receive Teardown Register (Rxteardown)

    Teardown receive channel 4 Teardown receive channel 5 Teardown receive channel 6 Teardown receive channel 7 SPRUFL5B – April 2011 Submit Documentation Feedback Figure 44 Reserved Reserved © 2011, Texas Instruments Incorporated EMAC Module Registers and described in Table RXTDNCH R/W-0 EMAC/MDIO Module...

  • Page 90: Transmit Interrupt Status (Unmasked) Register (Txintstatraw)

    TX1PEND TX1PEND raw interrupt read (before mask) TX0PEND TX0PEND raw interrupt read (before mask) EMAC/MDIO Module Reserved Reserved TX4PEND TX3PEND TX2PEND © 2011, Texas Instruments Incorporated www.ti.com Figure 45 and described TX1PEND TX0PEND SPRUFL5B – April 2011 Submit Documentation Feedback...

  • Page 91: Transmit Interrupt Status (Masked) Register (Txintstatmasked)

    TX2PEND masked interrupt read TX1PEND TX1PEND masked interrupt read TX0PEND TX0PEND masked interrupt read SPRUFL5B – April 2011 Submit Documentation Feedback Reserved Reserved TX4PEND TX3PEND TX2PEND © 2011, Texas Instruments Incorporated EMAC Module Registers Figure 46 TX1PEND TX0PEND EMAC/MDIO Module...

  • Page 92: Transmit Interrupt Mask Set Register (Txintmaskset)

    Transmit channel 0 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. EMAC/MDIO Module Reserved Reserved TX4MASK TX3MASK TX2MASK R/W1S-0 R/W1S-0 R/W1S-0 © 2011, Texas Instruments Incorporated www.ti.com Figure 47 and described in TX1MASK TX0MASK R/W1S-0 R/W1S-0 SPRUFL5B – April 2011 Submit Documentation Feedback...

  • Page 93: Transmit Interrupt Mask Clear Register (Txintmaskclear)

    Transmit channel 0 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. SPRUFL5B – April 2011 Submit Documentation Feedback Reserved Reserved TX4MASK TX3MASK TX2MASK R/W1C-0 R/W1C-0 R/W1C-0 © 2011, Texas Instruments Incorporated EMAC Module Registers Figure 48 and described in TX1MASK TX0MASK R/W1C-0 R/W1C-0 EMAC/MDIO Module...

  • Page 94: Mac Input Vector Register (Macinvector)

    Transmit channels 0-7 interrupt (TXnPEND) pending status. Bit 16 is TX0PEND. Receive channels 0-7 interrupt (RXnTHRESHPEND) pending status. Bit 8 is RX0THRESHPEND. Receive channels 0-7 interrupt (RXnPEND) pending status bit. Bit 0 is RX0PEND. © 2011, Texas Instruments Incorporated www.ti.com and described in Table...

  • Page 95: Mac End Of Interrupt Vector Register (Maceoivector)

    Acknowledge C2RX Interrupt Acknowledge C2TX Interrupt Acknowledge C2MISC Interrupt (STATPEND, HOSTPEND, MDIO LINKINT0, MDIO USERINT0) Ch-1Fh Reserved SPRUFL5B – April 2011 Submit Documentation Feedback Reserved © 2011, Texas Instruments Incorporated EMAC Module Registers Figure 50 and described in INTVECT R/W-0 EMAC/MDIO Module...

  • Page 96: Receive Interrupt Status (Unmasked) Register (Rxintstatraw)

    RX4PEND raw interrupt read (before mask) RX3PEND raw interrupt read (before mask) RX2PEND raw interrupt read (before mask) RX1PEND raw interrupt read (before mask) RX0PEND raw interrupt read (before mask) © 2011, Texas Instruments Incorporated www.ti.com Figure 51 and described RX2THRESHPEND...

  • Page 97: Receive Interrupt Status (Masked) Register (Rxintstatmasked)

    RX6PEND masked interrupt read RX5PEND masked interrupt read RX4PEND masked interrupt read RX3PEND masked interrupt read RX2PEND masked interrupt read RX1PEND masked interrupt read RX0PEND masked interrupt read © 2011, Texas Instruments Incorporated EMAC Module Registers Figure 52 RX2THRESHPEND RX1THRESHPEND RX0THRESHPEND RX2PEND...

  • Page 98: Receive Interrupt Mask Set Register (Rxintmaskset)

    Receive channel 1 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. Receive channel 0 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. © 2011, Texas Instruments Incorporated www.ti.com...

  • Page 99: Receive Interrupt Mask Clear Register (Rxintmaskclear)

    Receive channel 1 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. Receive channel 0 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. © 2011, Texas Instruments Incorporated EMAC Module Registers...

  • Page 100: Mac Interrupt Status (Unmasked) Register (Macintstatraw)

    HOSTPEND Host pending interrupt (HOSTPEND); masked interrupt read. STATPEND Statistics pending interrupt (STATPEND); masked interrupt read. EMAC/MDIO Module Reserved Reserved Reserved Reserved © 2011, Texas Instruments Incorporated www.ti.com Figure 55 and described HOSTPEND STATPEND Figure 56 and described HOSTPEND STATPEND SPRUFL5B –...

  • Page 101: Mac Interrupt Mask Set Register (Macintmaskset)

    Statistics interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. SPRUFL5B – April 2011 Submit Documentation Feedback Reserved Reserved Reserved Reserved © 2011, Texas Instruments Incorporated EMAC Module Registers Figure 57 and described in HOSTMASK STATMASK R/W1S-0...

  • Page 102: Receive Multicast/Broadcast/Promiscuous Channel Enable Register (Rxmbpenable)

    / code errors and undersized are short frames without errors. Short frames are filtered. Short frames are transferred to memory. EMAC/MDIO Module RXNOCHAIN Reserved R/W-0 Reserved Reserved Reserved Field Descriptions © 2011, Texas Instruments Incorporated www.ti.com RXCMFEN R/W-0 RXPROMCH R/W-0 RXBROADCH R/W-0 RXMULTCH R/W-0 SPRUFL5B – April 2011...
  • Page 103 RXMULTCH bits. Multicast frames are filtered. Multicast frames are copied to the channel selected by RXMULTCH bits. Reserved Reserved SPRUFL5B – April 2011 Submit Documentation Feedback Field Descriptions (continued) © 2011, Texas Instruments Incorporated EMAC Module Registers EMAC/MDIO Module...
  • Page 104 Select channel 4 to receive multicast frames Select channel 5 to receive multicast frames Select channel 6 to receive multicast frames Select channel 7 to receive multicast frames EMAC/MDIO Module Field Descriptions (continued) © 2011, Texas Instruments Incorporated www.ti.com SPRUFL5B – April 2011 Submit Documentation Feedback...

  • Page 105: Receive Unicast Enable Set Register (Rxunicastset)

    Receive channel 0 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May be read. SPRUFL5B – April 2011 Submit Documentation Feedback Figure 60 Reserved Reserved RXCH4EN RXCH3EN RXCH2EN R/W1S-0 R/W1S-0 R/W1S-0 © 2011, Texas Instruments Incorporated EMAC Module Registers and described in RXCH1EN RXCH0EN R/W1S-0 R/W1S-0 EMAC/MDIO Module...

  • Page 106: Receive Unicast Clear Register (Rxunicastclear)

    Receive channel 0 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. EMAC/MDIO Module Figure 61 Reserved Reserved RXCH4EN RXCH3EN RXCH2EN R/W1C-0 R/W1C-0 R/W1C-0 © 2011, Texas Instruments Incorporated www.ti.com and described in Table RXCH1EN RXCH0EN R/W1C-0 R/W1C-0 SPRUFL5B – April 2011 Submit Documentation Feedback...

  • Page 107: Receive Maximum Length Register (Rxmaxlen)

    15 bytes of the buffer are to be ignored by the EMAC and that valid buffer data starts on byte 16 of the buffer. This value is used for all channels. © 2011, Texas Instruments Incorporated EMAC Module Registers...

  • Page 108: Receive Filter Low Priority Frame Threshold Register (Rxfilterlowthresh)

    This field should remain 0, if no filtering is desired. Reserved Field Descriptions Description Reserved Receive flow threshold. These bits contain the threshold value for issuing flow control on incoming frames for channel n (when enabled). © 2011, Texas Instruments Incorporated www.ti.com Figure 64 RXFILTERTHRESH R/W-0 Figure 65 RXnFLOWTHRESH R/W-0 SPRUFL5B –...

  • Page 109: Receive Channel Free Buffer Count Registers (Rx0Freebuffer-Rx7Freebuffer)

    The host must write this field with the number of buffers that have been freed due to host processing. SPRUFL5B – April 2011 Submit Documentation Feedback Reserved RXnFREEBUF WI-0 © 2011, Texas Instruments Incorporated EMAC Module Registers Figure 66 EMAC/MDIO Module...

  • Page 110: Mac Control Register (Maccontrol)

    Transmit pacing is disabled. Transmit pacing is enabled. GMII enable bit GMII RX and TX are held in reset. GMII RX and TX are enabled for receive and transmit. © 2011, Texas Instruments Incorporated www.ti.com and described in Table TXPTYPE...
  • Page 111 FULLDUPLEX bit. The loopback bit should be changed only when GMIIEN bit is deasserted. Loopback mode is disabled. Loopback mode is enabled. Full duplex mode. Half-duplex mode is enabled. Full-duplex mode is enabled. © 2011, Texas Instruments Incorporated EMAC Module Registers EMAC/MDIO Module...

  • Page 112: Mac Status Register (Macstatus)

    The host error occurred on transmit channel 6 The host error occurred on transmit channel 7 EMAC/MDIO Module Figure 68 and described in TXERRCODE Reserved RXQOSACT © 2011, Texas Instruments Incorporated www.ti.com Table Rsvd TXERRCH RXERRCH RXFLOWACT TXFLOWACT SPRUFL5B – April 2011...
  • Page 113 Any transmission in progress when this bit is asserted will complete. Transmit flow control is inactive. Transmit flow control is active. SPRUFL5B – April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated EMAC Module Registers EMAC/MDIO Module...

  • Page 114: Emulation Control Register (Emcontrol)

    Three 64-byte packet cells required to be in the transmit FIFO. EMAC/MDIO Module Figure 69 and described in Reserved Reserved Figure 70 and described in Reserved Reserved © 2011, Texas Instruments Incorporated www.ti.com Table SOFT FREE R/W-0 R/W-0 Table TXCELLTHRESH R/W-2h SPRUFL5B –...

  • Page 115: Mac Configuration Register (Macconfig)

    A software reset has occurred. SPRUFL5B – April 2011 Submit Documentation Feedback Figure 71 Figure 72 and described in Figure 72. Soft Reset Register (SOFTRESET) Reserved Reserved © 2011, Texas Instruments Incorporated EMAC Module Registers and described in Table RXCELLDEPTH R-3h MACCFIG R-2h Table...

  • Page 116: Mac Source Address Low Bytes Register (Macsrcaddrlo)

    MACSRCADDR4 0-FFh MAC source address bits 39-32 (byte 4) MACSRCADDR5 0-FFh MAC source address bits 47-40 (byte 5) EMAC/MDIO Module Reserved © 2011, Texas Instruments Incorporated www.ti.com Figure 73 and described in MACSRCADDR1 R/W-0 Figure 74 and described in MACSRCADDR3...

  • Page 117: Mac Hash Address Register 1 (Machash1)

    Most-significant 32 bits of the hash table corresponding to hash values 32 to 63. If a hash table bit is set, then a group address that hashes to that bit index is accepted. © 2011, Texas Instruments Incorporated EMAC Module Registers...

  • Page 118: Back Off Test Register (Bofftest)

    IPG time is not stretched to four times the normal value. Transmit pacing helps reduce capture effects, which improves overall network bandwidth. EMAC/MDIO Module Figure 77 and described in TXBACKOFF Reserved © 2011, Texas Instruments Incorporated www.ti.com Table RNDNUM Figure 78 and described in PACEVAL SPRUFL5B –...

  • Page 119: Receive Pause Timer Register (Rxpause)

    0, at which time EMAC transmit frames are again enabled. SPRUFL5B – April 2011 Submit Documentation Feedback Figure 79 and described in Reserved PAUSETIMER Figure 80 and described in Reserved PAUSETIMER © 2011, Texas Instruments Incorporated EMAC Module Registers Table Table EMAC/MDIO Module...

  • Page 120: Mac Address Low Bytes Register (Macaddrlo)

    15-8 MACADDR0 0-FFh MAC address lower 8-0 bits (byte 0) MACADDR1 0-FFh MAC address bits 15-8 (byte 1) EMAC/MDIO Module VALID R/W-x © 2011, Texas Instruments Incorporated www.ti.com Figure 81 MATCHFILT CHANNEL R/W-x R/W-x MACADDR1 R/W-x SPRUFL5B – April 2011...

  • Page 121: Mac Address High Bytes Register (Macaddrhi)

    SPRUFL5B – April 2011 Submit Documentation Feedback Figure 83 and described in Figure 83. MAC Index Register (MACINDEX) Reserved Reserved © 2011, Texas Instruments Incorporated EMAC Module Registers Figure 82 and described in Table MACADDR3 R/W-x MACADDR5...

  • Page 122: Transmit Channel Dma Head Descriptor Pointer Registers (Tx0Hdp-Tx7Hdp)

    DMA operations in the selected channel when a channel frame is received. Writing to these locations when they are nonzero is an error (except at reset). Host software must initialize these locations to 0 on reset. © 2011, Texas Instruments Incorporated www.ti.com Figure 84 Figure 85 SPRUFL5B –...

  • Page 123: Transmit Channel Completion Pointer Registers (Tx0Cp-Tx7Cp)

    SPRUFL5B – April 2011 Submit Documentation Feedback TXnCP R/W-x RXnCP R/W-x © 2011, Texas Instruments Incorporated EMAC Module Registers Figure 86 and described in Figure 87 and described in EMAC/MDIO Module...

  • Page 124: 5.50 Network Statistics Registers

    CRC errors. Overruns have no effect on this statistic. EMAC/MDIO Module Figure 88) are write-to-decrement. The value written is Figure 88. Statistics Register COUNT R/WD-0 © 2011, Texas Instruments Incorporated www.ti.com SPRUFL5B – April 2011 Submit Documentation Feedback...
  • Page 125 CRC alignment or code errors can be calculated by summing receive alignment errors, receive code errors, and receive CRC errors. SPRUFL5B – April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated EMAC Module Registers Section 2.5.5 for definitions of...
  • Page 126 The address matching process decided that the frame should be discarded (filtered) because it did not match the unicast, broadcast, or multicast address, and it did not match due to promiscuous mode. EMAC/MDIO Module © 2011, Texas Instruments Incorporated www.ti.com SPRUFL5B – April 2011...
  • Page 127 Any data or MAC control frame that was destined for any unicast, broadcast, or multicast address • Was any length • Had no late or excessive collisions, no carrier loss, and no underrun SPRUFL5B – April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated EMAC Module Registers EMAC/MDIO Module...
  • Page 128 • When the EMAC is in half-duplex mode, flow control is active, and a frame reception begins. CRC errors have no effect on this statistic. EMAC/MDIO Module © 2011, Texas Instruments Incorporated www.ti.com SPRUFL5B – April 2011 Submit Documentation Feedback...
  • Page 129 The number of frames sent by the EMAC that experienced FIFO underrun. Late collisions, CRC errors, carrier loss, and underrun have no effect on this statistic. SPRUFL5B – April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated EMAC Module Registers EMAC/MDIO Module...
  • Page 130 Did not experience late collisions, excessive collisions, underrun, or carrier sense error • Was 128-bytes to 255-bytes long CRC errors, alignment/code errors, underruns, and overruns do not affect the recording of frames in this statistic. EMAC/MDIO Module © 2011, Texas Instruments Incorporated www.ti.com SPRUFL5B – April 2011 Submit Documentation Feedback...
  • Page 131 Error conditions such as alignment errors, CRC errors, code errors, overruns, and underruns do not affect the recording of bytes in this statistic. The objective of this statistic is to give a reasonable indication of Ethernet utilization. SPRUFL5B – April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated EMAC Module Registers EMAC/MDIO Module...
  • Page 132 (zero head descriptor pointer at the start or during the middle of the frame reception). CRC errors, alignment errors, and code errors have no effect on this statistic. EMAC/MDIO Module © 2011, Texas Instruments Incorporated www.ti.com SPRUFL5B – April 2011...

  • Page 133: Appendix A Glossary

    Jabber— A condition wherein a station transmits for a period of time longer than the maximum permissible packet length, usually due to a fault condition. Link— The transmission path between any two instances of generic cabling. SPRUFL5B – April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated Glossary...

  • Page 134: Physical Layer Definitions

    A cable element that consists of two insulated conductors twisted together in a regular fashion to form a balanced transmission line. Port— Ethernet device. Promiscuous Mode— EMAC receives frames that do not match its address. Glossary Table 87. Physical Layer Definitions © 2011, Texas Instruments Incorporated www.ti.com Table SPRUFL5B – April 2011 Submit Documentation Feedback...

  • Page 135: Appendix B Revision History

    Reference Additions/Modifications/Deletions Figure 2 Changed figure. Section 2.5.2 Changed first paragraph. Section 2.5.3 Changed third paragraph. SPRUFL5B – April 2011 Submit Documentation Feedback Table 88. Document Revision History © 2011, Texas Instruments Incorporated Revision History...

  • Page 136: Important Notice

    Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

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