Gpio Port A Set, Clear And Toggle (Gpaset, Gpaclear, Gpatoggle) Registers; Gpio Port A Set (Gpaset) Register Field Descriptions; Gpio Port A Clear (Gpaclear) Register Field Descriptions; Gpio Port A Toggle (Gpatoggle) Register Field Descriptions - Texas Instruments TMS320x2833 series Reference Manual

Register Bit Definitions
Figure 4-29. GPIO Port A Set, Clear and Toggle (GPASET, GPACLEAR, GPATOGGLE) Registers
31 30
GPIO31 GPIO30
R/W-0 R/W-0
23 22
GPIO23 GPIO22
R/W-0 R/W-0
15 14
GPIO15 GPIO14
R/W-0 R/W-0
7 6
GPIO7 GPIO6
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-33. GPIO Port A Set (GPASET) Register Field Descriptions
Bits Field
31-0 GPIO31-GPIO0
Table 4-34. GPIO Port A Clear (GPACLEAR) Register Field Descriptions
Bits Field
31-0 GPIO31 - GPIO0
Table 4-35. GPIO Port A Toggle (GPATOGGLE) Register Field Descriptions
Bits Field
31-0 GPIO31-GPIO0
104 General-Purpose Input/Output (GPIO)
29 28
GPIO29 GPIO28
R/W-0 R/W-0
21 20
GPIO21 GPIO20
R/W-0 R/W-0
13 12
GPIO13 GPIO12
R/W-0 R/W-0
5 4
GPIO5 GPIO4
R/W-0 R/W-0
Value
Each GPIO port A pin (GPIO0-GPIO31) corresponds to one bit in this register as shown in
Figure 4-29.
0 Writes of 0 are ignored. This register always reads back a 0.
1 Writing a 1 forces the respective output data latch to high. If the pin is configured as a GPIO
output then it will be driven high. If the pin is not configured as a GPIO output then the latch is set
high but the pin is not driven.
Value
Each GPIO port A pin (GPIO0-GPIO31) corresponds to one bit in this register as shown in
Figure 4-29.
0 Writes of 0 are ignored. This register always reads back a 0.
1 Writing a 1 forces the respective output data latch to low. If the pin is configured as a GPIO output
then it will be driven low. If the pin is not configured as a GPIO output then the latch is cleared but
the pin is not driven.
Value
Each GPIO port A pin (GPIO0-GPIO31) corresponds to one bit in this register as shown in
Figure 4-29.
0 Writes of 0 are ignored. This register always reads back a 0.
1 Writing a 1 forces the respective output data latch to toggle from its current state. If the pin is
configured as a GPIO output then it will be driven in the opposite direction of its current state. If the
pin is not configured as a GPIO output then the latch is toggled but the pin is not driven.
27 26
GPIO27 GPIO26
R/W-0 R/W-0
19 18
GPIO19 GPIO18
R/W-0 R/W-0
11 10
GPIO11 GPIO10
R/W-0 R/W-0
3 2
GPIO3 GPIO2
R/W-0 R/W-0
Description
Description
Description
SPRUFB0C – September 2007 – Revised May 2009
www.ti.com
25 24
GPIO25 GPIO24
R/W-0 R/W-0
17 16
GPIO17 GPIO16
R/W-0 R/W-0
9 8
GPIO9 GPIO8
R/W-0 R/W-0
1 0
GPIO1 GPIO0
R/W-0 R/W-0
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