User Performance Monitor Counter Registers (Upmc0-Upmc3); Performance Monitor Apu Instructions - Freescale Semiconductor PowerPC e500 Core Reference Manual

The response to an overflow depends on the configuration, as follows:
• If PMLCan[CE] is clear, no special actions occur on overflow: the counter continues
incrementing, and no exception is signaled.
• If PMLCan[CE] and PMGC0[FCECE] are set, all counters are frozen when PMCn
overflows.
• If PMLCan[CE] and PMGC0[PMIE] are set, an exception is signaled when PMCn reaches
overflow. Interrupts are masked by clearing MSR[EE]. An exception may be signaled while
EE is zero, but the interrupt is not taken until it is set and only if the overflow condition is
still present and the configuration has not been changed in the meantime to disable the
exception.
However, if EE remains clear until after the counter leaves the overflow state (msb becomes
0), or if EE remains clear until after PMLCan[CE] or PMGC0[PMIE] cleared, the
exception is not signaled.
The following sequence is recommended for setting counter values and configurations:
1. Set PMGC0[FAC] to freeze the counters.
2. Using mtpmr instructions, initialize counters and configure control registers.
3. Release the counters by clearing PMGC0[FAC] with a final mtpmr.
7.2.8 User Performance Monitor Counter Registers
(UPMC0–UPMC3)
The contents of PMC0–PMC3 are reflected to UPMC0–UPMC3, which can be read by user-level
software with the mfpmr instruction using PMR numbers in
7.3

Performance Monitor APU Instructions

The APU defines instructions for reading and writing the PMRs as shown in
Move from Performance Monitor Register
Move to Performance Monitor Register
Freescale Semiconductor
Table 7-7. Performance Monitor APU Instructions
Name
PowerPC e500 Core Family Reference Manual, Rev. 1
Performance Monitor
Table 7-2.
Table
Mnemonic Syntax
mfpmr rD,PMRN
mtpmr PMRN,rS
7-7.
7-9