Freescale Semiconductor PowerPC e500 Core Reference Manual

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PowerPC™ e500 Core

Family Reference Manual

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e500v1

e500v2

E500CORERM

Rev. 1, 4/2005

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Summary of Contents for Freescale Semiconductor PowerPC e500 Core

Page 1 PowerPC™ e500 Core Family Reference Manual Supports e500v1 e500v2 E500CORERM Rev. 1, 4/2005...
Page 2 Freescale Semiconductor product For Literature Requests Only: could create a situation where personal injury or death may occur. Should Buyer...
Page 3 Part I—e500 Core Core Complex Overview Register Model Instruction Model Execution Timing Interrupts and Exceptions Power Management Performance Monitor Debug Support Part II—e500 Core Complex Timer Facilities Auxiliary Processing Units (APUs) L1 Caches Memory Management Units Core Complex Bus (CCB) Appendix A—Programming Examples Appendix B—Guidelines for 32-Bit Book E Appendix C—Simplified Mnemonics for PowerPC Instructions...
Page 4 Part I—e500 Core Core Complex Overview Register Model Instruction Model Execution Timing Interrupts and Exceptions Power Management Performance Monitor Debug Support Part II—e500 Core Complex Timer Facilities Auxiliary Processing Units (APUs) L1 Caches Memory Management Units Core Complex Bus (CCB) Appendix A—Programming Examples Appendix B—Guidelines for 32-Bit Book E Appendix C—Simplified Mnemonics for PowerPC Instructions...
Page 5: Table Of Contents
Interrupt Types ......................1-21 1.8.4 Upper Bound on Interrupt Latencies ................. 1-22 1.8.5 Interrupt Registers...................... 1-22 Memory Management....................1-24 1.9.1 Address Translation ....................1-26 1.9.2 MMU Assist Registers (MAS0–MAS4 and MAS6–MAS7)........1-27 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 6: Paragraph Page
Processor Control Registers................... 2-10 2.5.1 Machine State Register (MSR) .................. 2-10 2.5.2 Processor ID Register (PIR) ..................2-12 2.5.3 Processor Version Register (PVR)................2-13 2.5.4 System Version Register (SVR)................. 2-13 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 7 L1 Cache Configuration Register 1 (L1CFG1) ............2-35 2.12 MMU Registers......................2-35 2.12.1 Process ID Registers (PID0–PID2)................2-36 2.12.2 MMU Control and Status Register 0 (MMUCSR0) ..........2-36 2.12.3 MMU Configuration Register (MMUCFG) .............. 2-37 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 8 2.16 Synchronization Requirements for SPRs............... 2-58 Chapter 3 Instruction Model Operand Conventions ...................... 3-1 3.1.1 Data Organization in Memory and Data Transfers............3-1 3.1.2 Alignment and Misaligned Accesses................3-2 PowerPC e500 Core Family Reference Manual, Rev. 1 viii Freescale Semiconductor...
Page 9 (MO = 1)....................3-31 3.3.1.7 Atomic Update Primitives Using lwarx and stwcx..........3-32 3.3.1.7.1 Reservations....................... 3-34 3.3.1.7.2 Forward Progress ....................3-36 3.3.1.7.3 Reservation Loss Due to Granularity ..............3-36 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 10 Performance Monitor APU..................3-60 3.8.4 Cache Locking APU ....................3-61 3.8.5 Machine Check APU ....................3-63 e500-Specific Instructions ..................... 3-63 3.9.1 Branch Target Buffer (BTB) Locking Instructions............ 3-63 3.10 Instruction Listing......................3-66 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 11 MU Divide Execution.................... 4-28 4.4.3.2 MU Floating-Point Execution................4-29 4.4.4 Load/Store Execution ....................4-29 4.4.4.1 Effect of Operand Placement on Performance ............4-30 Memory Performance Considerations ................4-30 Instruction Latency Summary..................4-31 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 12 Core Complex Bus (CCB) and L1 Cache Machine Check Errors......5-16 5.7.2.2 Cache Parity Error Injection .................. 5-18 5.7.3 Data Storage Interrupt....................5-19 5.7.4 Instruction Storage Interrupt ..................5-20 5.7.5 External Input Interrupt ..................... 5-21 5.7.6 Alignment Interrupt ....................5-22 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 13 Interrupts and Power Management .................. 6-6 Chapter 7 Performance Monitor Overview.......................... 7-1 Performance Monitor APU Registers ................7-2 7.2.1 Global Control Register 0 (PMGC0) ................7-4 7.2.2 User Global Control Register 0 (UPMGC0)..............7-5 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor xiii...
Page 14 Effective Address Mode ..................8-10 8.4.2.4 Data Address Compare (DAC) Mode..............8-10 8.4.3 Trap Debug Event ...................... 8-11 8.4.4 Branch Taken Debug Event ..................8-12 8.4.5 Instruction Complete Debug Event................8-12 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 15 Floating-Point Conversion Models................10-22 10.4.5.1 Common Functions....................10-22 10.4.5.2 Convert from Double-Precision Floating-Point to Integer Word with Saturation....................10-23 10.4.5.3 Convert to Double-Precision Floating-Point from Integer Word with Saturation....................10-25 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 16 L1 Instruction and Data Cache Flash Invalidation ..........11-18 11.4.4 L1 Instruction and Data Cache Line Locking/Unlocking........11-19 11.4.4.1 Effects of Other Cache Instructions on Locked Lines......... 11-21 11.4.4.2 Flash Clearing of Lock Bits................. 11-21 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 17 Round-Robin Replacement for TLB0—e500v2..........12-14 12.3.3 Consistency Between L1 and L2 TLBs ..............12-15 12.3.4 L1 and L2 TLB Access Times ................. 12-16 12.3.5 The G Bit (of WIMGE) ................... 12-16 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor xvii...
Page 18 L2 Unlocking ......................13-8 13.5.3 L1 Overlock ....................... 13-8 13.6 Reservation Management ....................13-8 13.7 Remote Atomic Status Monitoring ................13-9 13.8 Proper Reporting of Bus Faults ..................13-9 PowerPC e500 Core Family Reference Manual, Rev. 1 xviii Freescale Semiconductor...
Page 19 Subtract ........................C-2 Rotate and Shift Simplified Mnemonics................C-2 C.3.1 Operations on Words ....................C-3 Branch Instruction Simplified Mnemonics..............C-4 C.4.1 Key Facts about Simplified Branch Mnemonics ............C-5 C.4.2 Eliminating the BO Operand ..................C-5 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 20 Instructions (Binary) by Mnemonic................D-1 Instructions (Decimal and Hexadecimal) by Opcode ........... D-22 Instructions by Form ..................... D-35 Appendix E Revision History Major Changes From Revision 0 to Revision 1.............. A-1 Index PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 21 MMU Control and Status Register 0 (MMUCSR0) ............. 2-36 2-26 MMU Configuration Register (MMUCFG) ................. 2-37 2-27 TLB Configuration Register 0 (TLB0CFG) ................. 2-38 2-28 TLB Configuration Register 1 (TLB1CFG) ................. 2-39 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 22 Core Power Management State Diagram................6-2 Example Core Power Management Handshaking ..............6-5 Performance Monitor Global Control Register 0 (PMGC0)/ User Performance Monitor Global Control Register 0 (UPMGC0) ........7-4 PowerPC e500 Core Family Reference Manual, Rev. 1 xxii Freescale Semiconductor...
Page 23 MAS Register 7 (MAS7) ....................12-31 13-1 CCB Interface Signals......................13-2 Branch Conditional (bc) Instruction Format................C-4 BO Field (Bits 6–10 of the Instruction Encoding) ..............C-6 BI Field (Bits 11–14 of the Instruction Encoding)..............C-9 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor xxiii...
Page 24: Figure Page
Figures Figure Page Number Title Number PowerPC e500 Core Family Reference Manual, Rev. 1 xxiv Freescale Semiconductor...
Page 25 MAS3 Field Descriptions—RPN and Access Control ............2-43 2-28 MAS4 Field Descriptions—Hardware Replacement Assist Configuration......2-44 2-29 MAS6 Field Descriptions...................... 2-45 2-30 MAS7 Field Descriptions—High-Order RPN ..............2-45 2-31 DBCR0 Field Descriptions ....................2-46 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 26 Memory Synchronization Instructions.................. 3-30 3-26 User-Level Cache Instructions....................3-38 3-27 System Linkage Instructions—Supervisor-Level ..............3-40 3-28 Move to/from Machine State Register Instructions .............. 3-40 3-29 Supervisor-Level Cache Management Instruction..............3-41 PowerPC e500 Core Family Reference Manual, Rev. 1 xxvi Freescale Semiconductor...
Page 27 Data Storage Interrupt Register Settings................5-20 5-13 Instruction Storage Interrupt Exception Conditions ............. 5-20 5-14 Instruction Storage Interrupt Register Settings ..............5-21 5-15 External Input Interrupt Register Settings ................5-22 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor xxvii...
Page 28 JTAG Signal Details........................ 8-6 Debug Events .......................... 8-7 Instruction Address Compare Modes..................8-8 Data Address Compare Modes ..................... 8-10 10-1 BTB Locking APU Instructions.................... 10-2 11-1 Cache Line State Definitions ....................11-10 PowerPC e500 Core Family Reference Manual, Rev. 1 xxviii Freescale Semiconductor...
Page 29 Simplified Mnemonics for bclr and bcctr without LR Update..........C-13 C-14 Simplified Mnemonics for bcl and bcla with LR Update ............C-14 C-15 Simplified Mnemonics for bclrl and bcctrl with LR Update..........C-14 C-16 Standard Coding for Branch Conditions ................C-15 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor xxix...
Page 30 Additional Simplified Mnemonics for Accessing SPRGs ............C-24 C-29 Simplified Mnemonics......................C-26 Instructions (Binary) by Mnemonic..................D-1 Instructions (Decimal and Hexadecimal) by Opcode ............D-22 Instructions (Binary) by Form....................D-35 Revision History ........................A-1 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 31: About This Book
Freescale Book E implementation standards. This book describes all of the instructions and registers implemented on the e500, including those defined by Book E and those that are e500-specific. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor xxxi...
Page 32: Audience
Book E–defined programming model that are supported on the e500 and describes the e500-specific branch target buffer locking APU. • Chapter 11, “L1 Caches,” provides specific hardware and software details regarding the e500 cache implementation. PowerPC e500 Core Family Reference Manual, Rev. 1 xxxii Freescale Semiconductor...
Page 33: Suggested Reading
• Computer Architecture: A Quantitative Approach, Third Edition, by John L. Hennessy and David A. Patterson. • Computer Organization and Design: The Hardware/Software Interface, Second Edition, David A. Patterson and John L. Hennessy. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor xxxiii...
Page 34: Related Documentation
Internal signals are set in italics, for example, qual BG. Prefix to denote hexadecimal number Prefix to denote binary number rA, rB Instruction syntax used to identify a source GPR PowerPC e500 Core Family Reference Manual, Rev. 1 xxxiv Freescale Semiconductor...
Page 35: Terminology Conventions
Speculative memory accesses Privileged mode (or privileged state) Supervisor level Problem mode (or problem state) User level Reference bit Referenced bit Relocation Translation Storage (locations) Memory Storage (the act of) Access PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor xxxv...
Page 36 PowerPC e500 Core Family Reference Manual, Rev. 1 xxxvi Freescale Semiconductor...
Page 37: Part I E500 Core
APU that is defined by the Freescale Book E implementation standards. • Chapter 8, “Debug Support,” describes the e500 core complex internal debug capabilities and associated features. Included are important deviations to the Book E debug mode. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor Part I-1...
Page 38 PowerPC e500 Core Family Reference Manual, Rev. 1 Part I-2 Freescale Semiconductor...
Page 39: Core Complex Overview
Note that this conceptual diagram does not attempt to show how these features are physically implemented. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 40: E500 Core Complex Block Diagram
Core Complex Overview Figure 1-1. e500 Core Complex Block Diagram PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 41: Upward Compatibility
APU (SPE APU), which includes a suite of vector instructions that use the upper and lower halves of the GPRs as a single two-element operand. Most APUs implemented on the e500 are defined by the Freescale Semiconductor Book E implementation standards (EIS).
Page 42 It can also support single-beat and burst data transfers for memory accesses and memory-mapped I/O operations. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 43: E500 Processor And System Version Numbers
The APU also provides resources for detecting and handling overlocking conditions. — Machine check. The machine check interrupt is treated as a separate level of interrupt. It uses its own save and restore registers (MCSRR0 and MCSRR1) and Return from PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 44: Vector And Floating-Point Apus
– If rA or rB is zero, a floating-point divide takes 4 cycles; all other cases take 29 cycles. – 4-cycle SIMD pipelined multiply-accumulate (MAC) – 64-bit accumulator for no-stall MAC operations PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 45 — Four-entry general instruction issue queue (GIQ) • Branch unit—The branch unit (BU) is an execution unit and is distinct from the BPU. It executes (resolves) all branch and CR logical instructions. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 46: Four-Stage Mu Pipeline, Showing Divide Bypass
— Load miss queue allows up to four load misses before stalling (up to nine load misses in the e500v2). — Load hits can continue to be serviced when the load miss queue is full. — The seven-entry L1 store queue allows full pipelining of stores. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 47: Three-Stage Load/Store Unit
— Two general-purpose read data buses and one write data bus • Extended exception handling — Supports Book E interrupt model – Less than 10-cycle interrupt latency – Interrupt vector prefix register (IVPR) PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 48 ) of physical memory on the e500v1 and 64 Gbytes (2 ) on the e500v2 — Support for big-endian and true little-endian memory on a per-page basis • Power management PowerPC e500 Core Family Reference Manual, Rev. 1 1-10 Freescale Semiconductor...
Page 49: E500V2 Differences
• TBSEL and TBEE bits have been added to the performance monitor global control register 0 (PMGC0) to support monitoring of time base events. • Minor modifications to the SPE APU. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 1-11...
Page 50: Instruction Set
CT, rA, rB Instruction Cache Block Touch and Lock Set icbtls CT, rA, rB — Machine check APU. This APU defines the Return from Machine Check Interrupt instruction (rfmci). PowerPC e500 Core Family Reference Manual, Rev. 1 1-12 Freescale Semiconductor...
Page 51 — BTB locking APU instructions. The core complex provides a 512-entry BTB for efficient processing of branch instructions. The BTB is a branch target address cache, PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 1-13...
Page 52: Instruction Flow
Each of the 512 entries in the 4-way set associative address cache of branch target addresses includes a 2-bit saturating branch history counter, whose value is incremented or decremented depending on whether the branch was taken. These bits can take on four values PowerPC e500 Core Family Reference Manual, Rev. 1 1-14 Freescale Semiconductor...
Page 53 If a branch resolves as incorrect, instructions in the target stream are flushed from the execution pipeline, the branch history bits are updated in the BTB entry, and nonspeculative fetching begins from the correct path. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 1-15...
Page 54: E500 Execution Pipeline
L2 cache (if implemented). Those factors increase when it is necessary to fetch instructions from system memory and include the processor-to-bus clock ratio, the amount of bus traffic, and whether any cache coherency operations are required. PowerPC e500 Core Family Reference Manual, Rev. 1 1-16 Freescale Semiconductor...
Page 55: Gpr Issue Queue (Giq)
An instruction in GIQ1 destined for SU2 or the LSU need not wait for an MU instruction in GIQ0 that is stalled behind a long-latency divide. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 1-17...
Page 56: Programming Model
The following section describes the e500 core registers defined in Book E, the Freescale Semiconductor Book E implementation standards (EIS), and registers that are specific to the e500. Figure 1-7 shows the e500 register set. PowerPC e500 Core Family Reference Manual, Rev. 1 1-18 Freescale Semiconductor...
Page 57: E500 Core Programming Model
L1CSR0 spr 1010 L1 Cache Control/Status 0/1 spr 1011 L1CSR1 These registers are defined by the EIS e500v2 only These registers are e500-specific Figure 1-7. e500 Core Programming Model PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 1-19...
Page 58: On-Chip Cache Implementation
(ESR) or the SPEFSCR, depending on the exception, to verify the specific cause of the exception and take appropriate action. The core complex provides the interrupts described in Section 1.8.5, “Interrupt Registers.” PowerPC e500 Core Family Reference Manual, Rev. 1 1-20 Freescale Semiconductor...
Page 59: Interrupt Classes
Power PC architecture. They use save and restore registers (SRR0/SRR1) to save state when they are taken and they use the rfi instruction to restore state. Asynchronous noncritical interrupts can be masked by the external interrupt enable bit, MSR[EE]. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 1-21...
Page 60: Upper Bound On Interrupt Latencies
CSRR1 Critical save/restore register 1—Holds machine state on critical interrupts and restores machine state after an rfci instruction is executed. PowerPC e500 Core Family Reference Manual, Rev. 1 1-22 Freescale Semiconductor...
Page 61 Instruction storage interrupt offset IVOR4 External input interrupt offset IVOR5 Alignment interrupt offset IVOR6 Program interrupt offset IVOR7 Floating-point unavailable interrupt offset (not supported on the e500) IVOR8 System call interrupt offset PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 1-23...
Page 62: Memory Management
• User-definable (U0–U3), a 4-bit implementation-specific field The core complex employs a two-level memory management unit (MMU) architecture. There are separate instruction and data level-1 (L1) MMUs backed up by a unified level-2 (L2) MMU, PowerPC e500 Core Family Reference Manual, Rev. 1 1-24 Freescale Semiconductor...
Page 63: Mmu Structure
• Hardware assist for TLB miss exceptions • Software managed by tlbre, tlbwe, tlbsx, tlbsync, tlbivax, and mtspr instructions • Supports snooping of TLB by both internal and external tlbivax instructions PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 1-25...
Page 64: Address Translation
4–20 bits* 12–28 bits* 32-bit Real Address Real Page Number Byte Address * Number of bits depends on page size (4 Kbytes–256 Mbytes) Figure 1-9. Effective-to-Real Address Translation Flow PowerPC e500 Core Family Reference Manual, Rev. 1 1-26 Freescale Semiconductor...
Page 65: Mmu Assist Registers (Mas0-Mas4 And Mas6-Mas7)
TLBs and information required to identify the TLB to be accessed. To ensure consistency among Freescale Semiconductor Book E processors, certain aspects of the implementation are defined by the Freescale Semiconductor Book E standard, whereas more specific details are left to individual implementations.
Page 66: Process Id Registers (Pid0-Pid2)
(CCB) if HID1[ABE] is set. The core complex also snoops TLB invalidate transactions on the CCB from other bus masters. PowerPC e500 Core Family Reference Manual, Rev. 1 1-28 Freescale Semiconductor...
Page 67: Memory Coherency
• Data Cache Block Touch and Lock Set (dcbtls) • Data Cache Block Touch for Store and Lock Set (dcbtstls) • Instruction Cache Block Lock Clear (icblc) • Instruction Cache Block Touch and Lock Set (icbtls) PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 1-29...
Page 68: Programmable
Two instructions, mtpmr and mfpmr, are provided for moving data to and from these registers. An overview of the performance monitoring registers is provided in the following sections. PowerPC e500 Core Family Reference Manual, Rev. 1 1-30 Freescale Semiconductor...
Page 69: Global Control Register
[threshold × multiplier] times. The contents of these registers are reflected to UPMLCb0–UPMLCb3, which can be read from user mode with mfpmr. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 1-31...
Page 70: Legacy Support Of Powerpc Architecture
• The MMU architecture is different, so some TLB manipulation instructions have different semantics. • Instructions that support the BATs and segment registers are not implemented. PowerPC e500 Core Family Reference Manual, Rev. 1 1-32 Freescale Semiconductor...
Page 71: Memory Subsystem
Book E defines resources for fixed 4-Kbyte pages and multiple, variable page sizes that can be configured in a single implementation. TLB management is provided with new instructions and SPRs. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 1-33...
Page 72: Reset
Unlike the AIM version of the PowerPC architecture, where little-endian mode is controlled on a system basis, Book E allows control of byte ordering on a memory page basis. In addition, the little-endian mode used in Book E is true little endian. PowerPC e500 Core Family Reference Manual, Rev. 1 1-34 Freescale Semiconductor...
Page 73: Register Model
– Specified CR fields can be set by a move to the CR from a GPR (mtcrf). – A specified CR field can be set by a move to the CR from another CR field (mcrf), or from the XER (mcrxr). PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 74: E500 Register Model
— Machine state register (MSR)—Used by the operating system to configure parameters such as user/supervisor mode, address space, and enabling of asynchronous interrupts. MSR is described in Section 2.5.1, “Machine State Register (MSR).” PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 75: E500 Register Model
Local control b0–b3 L1CSR0 spr 1010 L1 Cache Control/Status 0/1 spr 1011 L1CSR1 These registers are defined by the EIS e500v2 only These registers are e500-specific Figure 2-1. e500 Register Model PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 76 32-bit Book E implementation. SPE APU vector instructions return 64-bit values, as do DPFP APU instructions on the e500v2; SPFP APU instructions return single-precision 32-bit values. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 77: Special-Purpose Registers (Sprs)
APU instructions at the assembly level or that uses SPE intrinsics will require rewriting for upward compatibility with next-generation PowerQUICC devices. Freescale Semiconductor offers a libmoto_e500 library that uses SPE instructions. Freescale will also provide libraries to support next-generation PowerQUICC devices.
Page 78 Instruction TLB error interrupt offset 01100 11110 Read/Write 2.7.1.5/2-19 IVOR15 Debug interrupt offset 01100 11111 Read/Write 2.7.1.5/2-19 IVPR Interrupt vector 00001 11111 Read/Write 2.7.1.4/2-19 Link register 00000 01000 Read/Write 2.4.2/2-10 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 79 The TSR is read using mfspr. It cannot be directly written to. Instead, TSR bits corresponding to 1 bits in the GPR can be cleared using mtspr. USPRG0 is a separate physical register from SPRG0. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 80 PID, not PID0. PID1 Process ID register 1 Read/Write 2.12.1/2-36 PID2 Process ID register 2 Read/Write 2.12.1/2-36 SPEFSCR Signal processing and embedded floating-point Read/Write 2.14.1/2-49 status and control register PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 81: Registers For Integer Operations
2.4.1 Condition Register (CR) The e500 implements the CR as it is defined by Book E for integer instructions. Note that the embedded floating-point instructions do not use the CR. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 82: Link Register (Lr)
MCSRR0 and MCSRR1 hold the return address and MSR information. The EIS defines the Return from Machine Check Interrupt instruction, rfmci, which restores MSR contents from MCSRR1 when it is executed. PowerPC e500 Core Family Reference Manual, Rev. 1 2-10 Freescale Semiconductor...
Page 83 GPRs, SPRs, and the MSR). 1 The processor is in user mode, cannot execute any privileged instruction, and cannot access any privileged resource. PR also affects memory access control. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 2-11...
Page 84: Processor Id Register (Pir)
The e500 implements the processor ID register (PIR) as defined by the Book E architecture. The PIR contains a value that can be used to distinguish the processor from other processors in the system. PowerPC e500 Core Family Reference Manual, Rev. 1 2-12 Freescale Semiconductor...
Page 85: Processor Version Register (Pvr)
SPR 1023 Access: Supervisor read-only System version SoC-dependent value (determined by svr [0:31]. See Reset Section 13.2, “Signal Summary.”) Figure 2-4. System Version Register (SVR) PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 2-13...
Page 86: Timer Registers
• Software can select one from of four TB bits to signal a fixed-interval interrupt whenever the bit transitions from 0 to 1. It is typically used to trigger periodic system maintenance functions. Bits that may be selected are implementation-dependent. PowerPC e500 Core Family Reference Manual, Rev. 1 2-14 Freescale Semiconductor...
Page 87: Timer Control Register (Tcr)
0 to 1. FPEXT || FP = 0000_00 selects TBU[32] (the msb of the TB) FPEXT || FP = 1111_11 selects TBL[63] (the lsb of the TB) PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 2-15...
Page 88: Timer Status Register (Tsr)
The alternate time base counter (ATB), shown in Figure 2-7, is formed by concatenating the upper and lower alternate time base registers (ATBU and ATBL). ATBL (SPR 526) provides read-only PowerPC e500 Core Family Reference Manual, Rev. 1 2-16 Freescale Semiconductor...
Page 89: Alternate Time Base Upper (Atbu)
Upper 32 bits of the alternate time base counter Interrupt Registers Section 2.7.1, “Interrupt Registers Defined by Book E,” Section 2.7.2, “e500-Specific Interrupt Registers,” describe registers used for interrupt handling. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 2-17...
Page 90: Interrupt Registers Defined By Book E
The e500 implements DEAR as it is defined by the Book E architecture. DEAR is loaded with the effective address of a data access (caused by a load, store, or cache management instruction) that results in an alignment, data TLB miss, or DSI exception. PowerPC e500 Core Family Reference Manual, Rev. 1 2-18 Freescale Semiconductor...
Page 91: Interrupt Vector Prefix Register (Ivpr)
409 Auxiliary processor unavailable (Not supported on the e500) IVOR10 410 Decrementer IVOR11 411 Fixed-interval timer interrupt IVOR12 412 Watchdog timer interrupt IVOR13 413 Data TLB error IVOR14 414 Instruction TLB error IVOR15 415 Debug PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 2-19...
Page 92: Exception Syndrome Register (Esr)
Access: Supervisor-only 39 40 41 44 45 46 — PIL PPR PTR — ST — DLK ILK — — — Reset All zeros Figure 2-10. Exception Syndrome Register (ESR) PowerPC e500 Core Family Reference Manual, Rev. 1 2-20 Freescale Semiconductor...
Page 93 SPE/embedded floating-point exception bit (e500-specific) 0 Default 1 Any exception caused by an SPE or and SPFP instruction occurred. 57–63 — Reserved, should be cleared (defined by Book E as allocated). — PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 2-21...
Page 94: E500-Specific Interrupt Registers
MCAR are not meaningful. SPR 573 Access: Supervisor-only Machine check address Reset All zeros Figure 2-13. Machine Check Address Register (MCAR) PowerPC e500 Core Family Reference Manual, Rev. 1 2-22 Freescale Semiconductor...
Page 95: Machine Check Syndrome Register (Mcsr)
Data cache push parity error DCPERR Data cache parity error 36–55 — Reserved, should be cleared. BUS_IAERR Bus instruction address error BUS_RAERR Bus read address error BUS_WAERR Bus write address error PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 2-23...
Page 96: Software-Use Sprs (Sprg0-Sprg7 And Usprg0)
MSR[UBLE], is defined to allow user-mode programs to lock or unlock BTB entries. Section 3.9.1, “Branch Target Buffer (BTB) Locking Instructions,” for more information about BTB locking. Section 2.5.1, “Machine State Register (MSR),” describes MSR bits that support the BTB. PowerPC e500 Core Family Reference Manual, Rev. 1 2-24 Freescale Semiconductor...
Page 97: Branch Buffer Entry Address Register (Bbear)
Branch direction prediction. The user can pick the direction of the predicted branch. 0 The locked address is always predicted as not taken. 1 The locked address is always predicted as taken. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 2-25...
Page 98: Branch Unit Control And Status Register (Bucsr)
(BPEN). BBLFC is always read as 0. 58–62 — Reserved, should be cleared. BPEN Branch prediction enable 0 Branch prediction disabled 1 Branch prediction enabled (enables BTB to predict branches) PowerPC e500 Core Family Reference Manual, Rev. 1 2-26 Freescale Semiconductor...
Page 99: Hardware Implementation-Dependent Registers
Doze power management mode. If MSR[WE] is set, this bit controls the doze output signal. DOZE Interpretation of this bit is handled by integrated system logic. 0 doze is not asserted. 1 doze is asserted. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 2-27...
Page 100 NOPTI. If CT = 1, icbt does a touch load to the L2 cache. 1 dcbt, dcbtst, and icbt are treated as no-ops; dcblc and dcbtls are not treated as no-ops. PowerPC e500 Core Family Reference Manual, Rev. 1 2-28 Freescale Semiconductor...
Page 101: Hardware Implementation-Dependent Register 1 (Hid1)
Table 2-15 describes the HID1 fields. Table 2-15. HID1 Field Descriptions Bits Name Description 32–37 PLL_CFG Reflected directly from the PLL_CFG input pins (read-only) 38–46 — Reserved, should be cleared. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 2-29...
Page 102 0 R2 data bus parity checking disabled 1 R2 data bus parity checking enabled ASTME Address bus streaming mode enable 0 Address bus streaming mode disabled 1 Address bus streaming mode enabled PowerPC e500 Core Family Reference Manual, Rev. 1 2-30 Freescale Semiconductor...
Page 103: L1 Cache Configuration Registers
Access: Supervisor-only Line Locking APU Bits — CPE CPI — CSLC CUL CLO CLFR — CFI CE Reset All zeros Figure 2-20. L1 Cache Control and Status Register 0 (L1CSR0) PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 2-31...
Page 104 1 Cache invalidation operation. A cache invalidation operation is initiated by hardware. Once complete, CFI is cleared. Writing a 1 during an invalidation causes an undefined operation. (Data) Cache enable 0 The cache is neither accessed or updated. 1 Enables cache operation PowerPC e500 Core Family Reference Manual, Rev. 1 2-32 Freescale Semiconductor...
Page 105: L1 Cache Control And Status Register 1 (L1Csr1)
ICLFR Instruction cache lock bits flash reset. Writing 0 and then 1 flash clears the lock bit of all entries in the instruction cache; clearing occurs independently from the value of the enable bit (ICE). ICLFR is always read as 0. 56–61 — Reserved, should be cleared. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 2-33...
Page 106: L1 Cache Configuration Register 0 (L1Cfg0)
Cache locking APU available 0 Unavailable 1 Available Cache parity available 0 Unavailable 1 Available 45–49 — Reserved, should be cleared. 50–52 CNWAY Cache number of ways. 111 indicates eight ways PowerPC e500 Core Family Reference Manual, Rev. 1 2-34 Freescale Semiconductor...
Page 107: L1 Cache Configuration Register 1 (L1Cfg1)
• Process ID registers (PID0–PID2) • MMU control and status register 0 (MMUCSR0) • MMU configuration register (MMUCFG) • TLB configuration registers (TLBnCFG) • MMU assist registers (MAS0–MAS4, MAS6–MAS7) PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 2-35...
Page 108: Process Id Registers (Pid0-Pid2)
1 TLB1 invalidation operation. Hardware initiates a TLB1 invalidation operation. When this operation is complete, this bit is cleared. Writing a 1 during an invalidation operation causes an undefined operation. This invalidation typically takes 1 cycle. — Reserved, should be cleared. PowerPC e500 Core Family Reference Manual, Rev. 1 2-36 Freescale Semiconductor...
Page 109: Mmu Configuration Register (Mmucfg)
0b00 indicates version 1.0. 2.12.4 TLB Configuration Registers (TLB n CFG) The TLBnCFG read-only registers provide information about each specific TLB that is visible to the programming model. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 2-37...
Page 110: Tlb0 Configuration Register (Tlb0Cfg)
0 No variable-sized pages available (MINSIZE = MAXSIZE) 50–51 — Reserved, should be cleared. 52–63 NENTRY Number of entries in TLB0 0x100 TLB0 contains 256 entries (e500v1 only) 0x200 TLB0 contains 512 entries (e500v2 only) PowerPC e500 Core Family Reference Manual, Rev. 1 2-38 Freescale Semiconductor...
Page 111: Tlb1 Configuration Register 1 (Tlb1Cfg)
TLBs. They, along with MAS5 (which is not implemented in the e500), are defined by the Freescale implementation standard. Note that some fields in these registers are redefined on the e500. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 2-39...
Page 112: Mas Register 0 (Mas0)
MMU”). Note that for the e500v1, bit 62 should remain cleared and only bit 63 has significance. Note that this field is not defined for operations that specify TLB1 (when TLBSEL = 01). PowerPC e500 Core Family Reference Manual, Rev. 1 2-40 Freescale Semiconductor...
Page 113: Mas Register 1 (Mas1)
1000 64 Mbyte 0011 64 Kbyte 1001 256 Mbyte 0100 256 Kbyte 1010 1 Gbyte 0101 1 Mbyte 1011 4 Gbyte 0110 4 Mbyte 56–63 — Reserved, should be cleared. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 2-41...
Page 114: Mas Register 2 (Mas2)
PowerPC architecture. 0 The page is accessed in big-endian byte order. 1 The page is accessed in true little-endian byte order. PowerPC e500 Core Family Reference Manual, Rev. 1 2-42 Freescale Semiconductor...
Page 115: Mas Register 3 (Mas3)
Access: Supervisor-only 32 33 55 56 — TLBSELD — TIDSELD — TSIZED — X0D X1D WD ID MD GD ED Reset All zeros Figure 2-33. MAS Register 4 (MAS4) PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 2-43...
Page 116: Mas Register 6 (Mas6)
Section 2.16, “Synchronization Requirements for SPRs.” SPR 630 Access: Supervisor-only 39 40 47 48 — SPID0 — Reset All zeros Figure 2-34. MAS Register 6 (MAS6) PowerPC e500 Core Family Reference Manual, Rev. 1 2-44 Freescale Semiconductor...
Page 117: Mas Register 7 (Mas7)-E500V2 Only
This section describes debug-related registers that are accessible to software running on the processor. These registers are intended for use by special debug tools and debug software, and not by general application or operating system code. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 2-45...
Page 118: Debug Control Registers (Dbcr0-Dbcr2)
10 IAC2 debug events are based on effective addresses and can occur only if MSR[IS] = 0. 11 IAC2 debug events are based on effective addresses and can occur only if MSR[IS] = 1. PowerPC e500 Core Family Reference Manual, Rev. 1 2-46...
Page 119: Debug Control Register 2 (Dbcr2)
• Implementation-specific events that cause an unconditional debug event are defined in Table 2-34 (DBSR[UDE]). • The MRR field is affected by the e500 definition of the HRESET signal, as defined in Table 2-34. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 2-47...
Page 120: Instruction Address Compare Registers (Iac1-Iac4)
DAC1 or DAC2, inside or outside a range specified by the DAC1 and DAC2, PowerPC e500 Core Family Reference Manual, Rev. 1 2-48...
Page 121: Spe And Spfp Apu Registers
APU instructions at the assembly level or that uses SPE intrinsics will require rewriting for upward compatibility with next-generation PowerQUICC devices. Freescale Semiconductor offers a libmoto_e500 library that uses SPE instructions. Freescale will also provide libraries to support next-generation PowerQUICC devices.
Page 122 FDBZS Embedded floating-point divide-by-zero sticky. FDBZS = FDBZS | FDBZH | FDBZ FUNFS Embedded floating-point underflow sticky. Storage location for software to use when implementing true IEEE floating point. PowerPC e500 Core Family Reference Manual, Rev. 1 2-50 Freescale Semiconductor...
Page 123 1 Exception enabled. a floating-point data exception is taken if FOVF or FOVFH is set by a floating-point instruction. 62–63 FRMC Embedded floating-point rounding mode control 00 Round to nearest 01 Round toward zero 10 Round toward +infinity 11 Round toward –infinity PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 2-51...
Page 124: Accumulator (Acc)
PMC0 Performance monitor counter 0 00000 10000 2.15.7/2-57 PMC1 Performance monitor counter 1 00000 10001 PMC2 Performance monitor counter 2 00000 10010 PMC3 Performance monitor counter 3 00000 10011 PowerPC e500 Core Family Reference Manual, Rev. 1 2-52 Freescale Semiconductor...
Page 125: Global Control Register 0 (Pmgc0)
User Performance Monitor Global Control Register 0 (UPMGC0) PMGC0 is cleared by a hard reset. Reading this register does not change its contents. Table 2-38 describes the PMGC0 fields. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 2-53...
Page 126: User Global Control Register 0 (Upmgc0)
2.15.2 User Global Control Register 0 (UPMGC0) The contents of PMGC0 are reflected to UPMGC0, which is read by user-level software. UPMGC0 is read with the mfpmr instruction using PMR384. PowerPC e500 Core Family Reference Manual, Rev. 1 2-54 Freescale Semiconductor...
Page 127: Local Control A Registers (Pmlca0-Pmlca3)
It is recommended that CE be cleared when counter PMC x is selected for chaining. 38–40 — Reserved, should be cleared. 41–47 EVENT Event selector. Up to 128 events selectable. 48–63 — Reserved, should be cleared. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 2-55...
Page 128: User Local Control A Registers (Upmlca0-Upmlca3)
PowerPC e500 Core Family Reference Manual, Rev. 1 2-56 Freescale Semiconductor...
Page 129: User Local Control B Registers (Upmlcb0-Upmlcb3)
PMLCan[CE] are set and the mtpmr loads an overflowed value into PMCx, an interrupt may be generated without an event counting having taken place. PMC registers are accessed with mtpmr and mfpmr using the PMR numbers in Table 2-36. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 2-57...
Page 130: User Performance Monitor Counter Registers (Upmc0-Upmc3)
L1CSR1 mtspr l1csr1 None isync MAS[0-4,6] mtspr mas[0–4,6] None isync MMUCSR0 mtspr mmucsr0 None isync PID0–PID2 mtspr pid[0–2] None isync SPEFSCR mtspr spefscr None isync PowerPC e500 Core Family Reference Manual, Rev. 1 2-58 Freescale Semiconductor...
Page 131: Instruction Model
The address of a memory operand is the address of its first byte (that is, of its lowest-numbered byte). Operand length is implicit for each instruction. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 132: Alignment And Misaligned Accesses
• The scalar single-precision floating-point APU supports single-precision floating-point operations using the lower 32 bits of the GPRs. • The scalar double-precision floating-point APU (implemented on the e500v2) supports double-precision floating-point operations using both halves of the GPRs. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 133: Unsupported Book E Instructions
APU instructions at the assembly level or that uses SPE intrinsics will require rewriting for upward compatibility with next-generation PowerQUICC devices. Freescale Semiconductor offers a libmoto_e500 library that uses SPE instructions. Freescale will also provide libraries to support next-generation PowerQUICC devices..
Page 134 Move To FPSCR Bit 0 [and record CR] mtfsb0[.] Move To FPSCR Bit 1 [and record CR] mtfsb1[.] Move To FPSCR Field [Immediate] [and record CR] mtfsf[i][.] Store Floating-Point Double [with Update] [Indexed] stfd[u][x] PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 135: Instruction Set Summary
Integer instructions operate on word operands. The PowerPC architecture uses instructions that are 4 bytes long and word-aligned. It provides for byte, half-word, and word operand loads and stores between memory and a set of 32 general-purpose registers (GPRs). PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 136: Classes Of Instructions
Synchronization Requirements This section discusses synchronization requirements for special registers and TLBs. The synchronization described in this section refers to the state of the processor that is performing the synchronization. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 137 3-5, because all instructions before the context-altering instruction are fetched and decoded before the context-altering instruction is executed. (The processor must determine whether any of the preceding instructions are context-synchronizing.) PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 138: Synchronization Requirements For E500-Specific Sprs
SPRs beyond those stated in Book E and described in Section 3.2.3, “Synchronization Requirements.” Table 3-4. Synchronization Requirements for e500-Specific SPRs Registers Instruction Instruction Required Before Instruction Required After BBEAR mtspr bbear None isync BBTAR mtspr bbtar None isync PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 139 (DAC n ) — mtspr (DBCR n ) — mtspr (DBSR) — mtspr (DEC) None None mtspr (IAC n ) — mtspr (IVOR n ) None None mtspr (IVPR) None None PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 140: Synchronization With Tlbwe And Tlbivax Instructions
The following sequence shows why, for data accesses, it is necessary to ensure that all memory accesses due to instructions before the tlbwe or tlbivax have completed to a point at which they PowerPC e500 Core Family Reference Manual, Rev. 1 3-10...
Page 141: Context Synchronization
(see Section 3.2.3.3, “Context Synchronization”). msync is treated like isync with respect to item 1 (that is, the conditions described in item 1 apply to completion of msync). PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-11...
Page 142: Instruction-Related Interrupts
• Execution of an allocated instruction that is not implemented by the implementation (illegal instruction exception or unimplemented operation exception-type program interrupt) PowerPC e500 Core Family Reference Manual, Rev. 1 3-12 Freescale Semiconductor...
Page 143: Instruction Set Overview
Integer instructions use the content of the GPRs as source operands and place results into GPRs and the XER and CR fields. 3.3.1.1.1 Integer Arithmetic Instructions Table 3-6 lists the integer arithmetic instructions for the PowerPC processors. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-13...
Page 144 Timing,” describes how the e500 handles CR dependencies. The summary overflow (SO) and overflow (OV) bits in the XER are set to reflect an overflow condition of a 32-bit result only if the instruction’s OE bit is set. PowerPC e500 Core Family Reference Manual, Rev. 1 3-14 Freescale Semiconductor...
Page 145: Integer Compare Instructions
Equivalent eqv (eqv.) rA,rS,rB — Extend Sign Byte extsb (extsb.) rA,rS — Extend Sign Half Word extsh (extsh.) rA,rS — NAND nand (nand.) rA,rS,rB — nor (nor.) rA,rS,rB — PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-15...
Page 146: Integer Rotate And Shift Instructions
Mnemonic Syntax Shift Left Word slw (slw.) rA,rS,rB Shift Right Word srw (srw.) rA,rS,rB Shift Right Algebraic Word Immediate srawi (srawi.) rA,rS,SH Shift Right Algebraic Word sraw (sraw.) rA,rS,rB PowerPC e500 Core Family Reference Manual, Rev. 1 3-16 Freescale Semiconductor...
Page 147: Load And Store Instructions
(Additional synchronization is needed when one processor modifies instructions that another processor will execute.) PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-17...
Page 148: Integer Load And Store Address Generation
Instruction Encoding: Opcode rD/rS 15 16 Sign Extension rA=0? GPR (rA) Effective Address Store Memory GPR (rD/rS) Load Interface Figure 3-1. Register Indirect with Immediate Index Addressing for Integer Loads/Stores PowerPC e500 Core Family Reference Manual, Rev. 1 3-18 Freescale Semiconductor...
Page 149: Register Indirect With Index Addressing For Integer Loads/Stores
The option to specify rA or 0 is shown in the instruction descriptions as (rA|0). PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-19...
Page 150: Integer Load Instructions
Load Half Word Algebraic Indexed lhax rD,rA,rB Load Half Word Algebraic with Update lhau rD,d(rA) Load Half Word Algebraic with Update Indexed lhaux rD,rA,rB Load Word and Zero rD,d(rA) PowerPC e500 Core Family Reference Manual, Rev. 1 3-20 Freescale Semiconductor...
Page 151: Integer Store Instructions
= 1) to be an invalid form. Table 3-12 summarizes integer store instructions. Table 3-12. Integer Store Instructions Name Mnemonic Syntax Store Byte rS,d(rA) Store Byte Indexed stbx rS,rA,rB PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-21...
Page 152: Integer Load And Store With Byte-Reverse Instructions
The Book E architecture defines the Load Multiple Word (lmw) instruction with rA in the range of registers to be loaded as an invalid form. Load and store multiple accesses must be word aligned; otherwise, they cause an alignment exception. PowerPC e500 Core Family Reference Manual, Rev. 1 3-22 Freescale Semiconductor...
Page 153: Branch And Flow Control Instructions
Decrement the CTR, then branch if the decremented CTR ≠ 0 and the condition is FALSE. 0000 y 0001 y Decrement the CTR, then branch if the decremented CTR = 0 and the condition is FALSE. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-23...
Page 154: Branch Instructions
Branch b (ba bl bla) target_addr Branch Conditional bc (bca bcl bcla) BO,BI,target_addr Branch Conditional to Link Register bclr (bclrl) BO,BI Branch Conditional to Count Register bcctr (bcctrl) BO,BI PowerPC e500 Core Family Reference Manual, Rev. 1 3-24 Freescale Semiconductor...
Page 155: Condition Register Logical Instructions
Interrupt.” If the tested conditions are not met, instruction execution continues normally. See Appendix C, “Simplified Mnemonics for PowerPC Instructions.” Table 3-19. Trap Instructions Name Mnemonic Syntax Trap Word Immediate TO,rA,SIMM Trap Word TO,rA,rB PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-25...
Page 156: System Linkage Instruction
Table 3-22 lists the mtspr and mfspr instructions. Table 3-22. Move to/from Special-Purpose Register Instructions Name Mnemonic Syntax Move to Special-Purpose Register mtspr SPR,rS Move from Special-Purpose Register mfspr rD,SPR PowerPC e500 Core Family Reference Manual, Rev. 1 3-26 Freescale Semiconductor...
Page 157 Link register 00000 01000 Read/Write 2.4.2/2-10 Process ID register 00001 10000 Read/Write 2.12.1/2-36 Processor ID register 01000 11110 Read only 2.5.2/2-12 Processor version register 01000 11111 Read only 2.5.3/2-13 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-27...
Page 158 The TSR is read using mfspr. It cannot be directly written to. Instead, TSR bits corresponding to 1 bits in the GPR can be cleared using mtspr. USPRG0 is a separate physical register from SPRG0. PowerPC e500 Core Family Reference Manual, Rev. 1 3-28 Freescale Semiconductor...
Page 159: Number
Read/Write SPEFSCR Signal processing and embedded floating-point status Read/Write 2.14.1/2-49 and control register TLB0CFG TLB configuration register 0 Read only 2.12.4/2-37 TLB1CFG TLB configuration register 1 Read only 2.12.4.2/2-39 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-29...
Page 160: Memory Synchronization Instructions
. . . mbar . . . free lock ..lock . . . read & write . . . mbar . . . free lock PowerPC e500 Core Family Reference Manual, Rev. 1 3-30 Freescale Semiconductor...
Page 161: Mbar (Mo = 1)
No ordering is performed for dcbz if the instruction causes the system alignment error handler to be invoked. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-31...
Page 162: Atomic Update Primitives Using Lwarx And Stwcx
The lwarx and stwcx. instructions together permit atomic update of a memory location. Book E provides word and double-word forms of each of these instructions. Described here is the operation of lwarx and stwcx.. PowerPC e500 Core Family Reference Manual, Rev. 1 3-32 Freescale Semiconductor...
Page 163 However, a subsequent lwarx from the given location on the other processor followed by a successful stwcx. on that processor is PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 164: Reservations
• Another processor executes a store or dcbz to the same reservation granule. • Another processor executes a dcbtst, dcbst, or dcbf to the same reservation granule; whether the reservation is lost is undefined. PowerPC e500 Core Family Reference Manual, Rev. 1 3-34 Freescale Semiconductor...
Page 165 — Watchdog timer • Snoops — RWITM, RCLAIM — Writes, flush, kill, dkill • Another processor executes any of the following to the reservation granule: — dcbtst — dcbf — dcba PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-35...
Page 166: Forward Progress
Reservation granularity may vary for each implementation. There are no architectural restrictions bounding the granularity implementations must support, so reasonably portable code must PowerPC e500 Core Family Reference Manual, Rev. 1 3-36 Freescale Semiconductor...
Page 167: Memory Control Instructions
On some implementations, HID1[ABE] must be set to allow management of external L2 caches as well as other L1 caches in the system. Section 3.8.4, “Cache Locking APU,” describes cache-locking APU instructions. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-37...
Page 168 Otherwise, if no data is in the cache location, the e500 requests a cache line fill. Data brought into the cache is validated as if it were a load instruction. The memory reference of a dcbt sets the reference bit. PowerPC e500 Core Family Reference Manual, Rev. 1 3-38 Freescale Semiconductor...
Page 169: Supervisor-Level Instructions
The supervisor-level rfi instruction is used for returning from an interrupt handler. The rfci instruction is used for critical interrupts; rfmci is used for machine check interrupts. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-39...
Page 170: Supervisor-Level Memory Control Instructions
This section describes supervisor-level memory control instructions. Section 3.3.1.8, “Memory Control Instructions,” describes user-level memory control instructions. 3.3.2.2.1 Supervisor-Level Cache Instruction Table 3-29 lists the only supervisor-level cache management instruction. PowerPC e500 Core Family Reference Manual, Rev. 1 3-40 Freescale Semiconductor...
Page 171: Supervisor-Level Tlb Management Instructions
The RTL for the Freescale implementation of tlbre is as follows: tlb_entry_id = MAS0(TLBSEL, ESEL | MAS2(EPN) result = MMU(tlb_entry_id) MAS0, MAS1, MAS2, MAS3, (and MAS7 if HID0[EN_MAS7_UPDATE] = 1) = result PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-41...
Page 172: Recommended Simplified Mnemonics
Programs written to be portable across the various assemblers for the Book E architecture should not assume the existence of mnemonics not described in this document. PowerPC e500 Core Family Reference Manual, Rev. 1 3-42 Freescale Semiconductor...
Page 173: Book E Instructions With Implementation-Specific Features
3.8.2/3-60 Move from Performance Monitor Register mfpmr rD,PMRN 3.8.2/3-60 Move to Performance Monitor Register mtpmr PMRN,rS Return from Machine Check Interrupt rfmci — 3.8.5/3-63 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-43...
Page 174: Context Synchronization
Table 3-33. Natural Alignment Boundaries for Extended Vector Instructions Instruction Boundary evld{d,w,h} Double word evld{d,w,h}x evstd{d,w,h} evstd{d,w,h}x evlwwsplat{x} Word evlwhe{x} evlwhou{x} evlwhos{x} evlwhsplat{x} evstwwe{x} evstwwo{x} evstwhe{x} evstwho{x} evlhhesplat{x} Half word evlhhousplat{x} evlhhossplat{x} PowerPC e500 Core Family Reference Manual, Rev. 1 3-44 Freescale Semiconductor...
Page 175: Using Msync And Mbar To Order Memory Accesses
If lwarx and stwcx. instructions are used to obtain a pointer into a shared data structure, an import barrier is not needed if all the accesses to the shared data structure depend on the value obtained for the pointer. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 176: Lock Release And Export Barriers
The msync ensures that the store that releases the lock are not performed with respect to any other processor until all stores caused by instructions preceding the msync have been performed with respect to that processor. PowerPC e500 Core Family Reference Manual, Rev. 1 3-46 Freescale Semiconductor...
Page 177: Export Shared Memory And Release Lock Using Mbar (Mo = 0)
The update portion of the instruction is executed by one of the simple units, and the load portion is executed by the load/store unit. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 178: Memory Synchronization
EIS-Defined Instructions and APUs Implemented on the e500 Instructions that are specific to the e500 core are implemented as auxiliary processing units (APUs) and are described in the following sections. PowerPC e500 Core Family Reference Manual, Rev. 1 3-48 Freescale Semiconductor...
Page 179: Spe And Embedded Floating-Point Apus
The embedded double-precision floating-point APU (e500v2 only) uses the 64-bit GPRs to hold 64-bit, double-precision operands. Figure 3-4 shows how the SPE and floating-point APU programming models compare, indicating how each APU uses the GPRs. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-49...
Page 180: Spe And Floating-Point Apu Gpr Usage
Vector compare instructions specify a CR field and two source registers as well as the type of compare: greater than, less than, or equal. Two bits in the CR field PowerPC e500 Core Family Reference Manual, Rev. 1 3-50...
Page 181: Spe Operands: Signed Fractions
• The most negative number is represented by SF(0) = 1 and SF[1:N–1] = 0 (that is, N=32; 0x8000_0000 = –1.0). • The most positive number is represented by SF(0) = 0 and SF[1:N–1] = all 1s (that is, N=32; –(N–1) 0x7FFF_FFFF = 1.0 – 2 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-51...
Page 182: Spe Integer And Fractional Operations
(32x32→64) Low word versions of signed saturate and signed modulo fractional instructions are not supported. Attempting to execute an opcode corresponding to these instructions causes boundedly undefined results. PowerPC e500 Core Family Reference Manual, Rev. 1 3-52 Freescale Semiconductor...
Page 183 Multiply Half Words, Even, Guarded, Unsigned, Modulo, Integer and Accumulate Negative evmhegumian rD,rA,rB Multiply Half Words, Odd, Guarded, Signed, Modulo, Fractional and Accumulate evmhogsmfaa rD,rA,rB Multiply Half Words, Odd, Guarded, Signed, Modulo, Fractional and Accumulate Negative evmhogsmfan rD,rA,rB PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-53...
Page 184 Vector Load Half Word into Half Word Odd Unsigned and Splat Indexed evlhhousplatx rD,rA,rB Vector Load Half Word into Half Words Even and Splat evlhhesplat rD,d(rA) Vector Load Half Word into Half Words Even and Splat Indexed evlhhesplatx rD,rA,rB PowerPC e500 Core Family Reference Manual, Rev. 1 3-54 Freescale Semiconductor...
Page 185 Vector Multiply Half Words, Even, Unsigned, Saturate, Integer and Accumulate into Words evmheusiaaw rD,rA,rB Vector Multiply Half Words, Even, Unsigned, Saturate, Integer and Accumulate Negative into evmheusianw rD,rA,rB Words PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-55...
Page 186 Vector Multiply Word Low Unsigned, Modulo, Integer evmwlumi rD,rA,rB Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate evmwlumia rD,rA,rB Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate in Words evmwlumiaaw rD,rA,rB PowerPC e500 Core Family Reference Manual, Rev. 1 3-56 Freescale Semiconductor...
Page 187 Vector Shift Right Word Unsigned evsrwu rD,rA,rB Vector Splat Fractional Immediate evsplatfi rD,SIMM Vector Splat Immediate evsplati rD,SIMM Vector Store Double of Double evstdd rS,d(rA) Vector Store Double of Double Indexed evstddx rS,rA,rB PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-57...
Page 188: Embedded Floating-Point Apu Instructions
FPRs, these instructions use GPRs to offer improved performance for converting between floating-point, integer, and fractional values. Sharing GPRs allows vector floating-point instructions to use SPE load and store instructions. PowerPC e500 Core Family Reference Manual, Rev. 1 3-58 Freescale Semiconductor...
Page 189 Floating-Point Multiply efsmul efdmul evfsmul rD,rA,rB Floating-Point Negate efsneg efdneg evfsneg rD,rA Floating-Point Negative Absolute Value efsnabs efdnabs evfsnabs rD,rA Floating-Point Subtract efssub efdsub evfssub rD,rA,rB PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-59...
Page 190: Integer Select (Isel) Apu
EREF chapter, “Instruction Set.” Table 3-39. Performance Monitor APU Instructions Name Mnemonic Syntax Move from Performance Monitor Register mfpmr rD,PMRN Move to Performance Monitor Register mtpmr PMRN,rS PowerPC e500 Core Family Reference Manual, Rev. 1 3-60 Freescale Semiconductor...
Page 191: Cache Locking Apu
If CT=1 and the block already exists in the L2 cache, icbtls marks it such that it should not Lock Set be selected for replacement. If CT is not 0 or 1, icbtls is no-oped. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-61...
Page 192 The e500 implements a flash clear for all data cache lock bits (using L1CSR0[CLFR]) and in the instruction cache (using L1CSR1[ICLFR]). This allows system software to clear all data cache locking bits without knowing the addresses of the lines locked. PowerPC e500 Core Family Reference Manual, Rev. 1 3-62 Freescale Semiconductor...
Page 193: Machine Check Apu
They can be read and written in both user and supervisor modes with mfspr and mtspr. The user branch locking enable bit, MSR[UBLE], is defined to allow user mode programs to lock or unlock entries in the BTB. See Chapter 4, “Execution Timing.” PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-63...
Page 194 This instruction can always be executed in supervisor mode. In user mode, if MSR[UBLE] is cleared, a privileged instruction exception is taken; if MSR[UBLE] is set, the instruction executes without a privileged instruction exception. PowerPC e500 Core Family Reference Manual, Rev. 1 3-64 Freescale Semiconductor...
Page 195 This instruction can always be executed in supervisor mode. In user mode, if MSR[UBLE] is cleared, a privileged instruction exception is taken; if MSR[UBLE] is set, the instruction executes without a privileged instruction exception. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-65...
Page 196: Instruction Listing
SPE APU √ √ √ cmpl evstdh SPE APU √ √ √ cmpli evstdhx SPE APU √ √ √ cntlzw[.] evstdw SPE APU √ √ √ crand evstdwx SPE APU PowerPC e500 Core Family Reference Manual, Rev. 1 3-66 Freescale Semiconductor...
Page 197 √ efdctuf DPFP (e500v2) fmsubs[.] √ √ efdctui DPFP (e500v2) fmsub[.] √ √ efdctuiz DPFP (e500v2) fmuls[.] √ √ efddiv DPFP (e500v2) fmul[.] √ √ efdmul DPFP (e500v2) fnabs[.] PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-67...
Page 198 SPE APU lfsu √ √ evaddsmiaaw SPE APU lfsux √ √ evaddssiaaw SPE APU lfsx √ √ √ evaddumiaaw SPE APU √ √ √ evaddusiaaw SPE APU lhau PowerPC e500 Core Family Reference Manual, Rev. 1 3-68 Freescale Semiconductor...
Page 199 √ evfsneg Vector SPFP msync √ √ √ evfssub Vector SPFP mtcrf √ evfststeq Vector SPFP mtdcr √ √ evfststgt Vector SPFP mtfsb0[.] √ √ evfststlt Vector SPFP mtfsb1[.] PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-69...
Page 200 SPE APU rldicr. √ evmhesmfaaw SPE APU rldimi. √ √ √ evmhesmfanw SPE APU rlwimi[.] √ √ √ evmhesmi SPE APU rlwinm[.] √ √ √ evmhesmia SPE APU rlwnm[.] PowerPC e500 Core Family Reference Manual, Rev. 1 3-70 Freescale Semiconductor...
Page 201 SPE APU stmw √ √ evmhoumia SPE APU stswi √ √ evmhoumiaaw SPE APU stswx √ √ √ evmhoumianw SPE APU √ √ √ evmhousiaaw SPE APU stwbrx PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 3-71...
Page 202 SPE APU wrtee √ √ evmwsmfa SPE APU wrteei √ √ √ evmwsmfaa SPE APU xori[.] √ √ √ evmwsmfan SPE APU xor[.] evmwsmi SPE APU evmwsmia SPE APU PowerPC e500 Core Family Reference Manual, Rev. 1 3-72 Freescale Semiconductor...
Page 203: Execution Timing
• Complete—An instruction is eligible to complete after it finishes executing and makes its results available for subsequent instructions. Instructions must complete in order from the bottom two entries of the completion queue (CQ). The completion unit coordinates how PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 204 The ability to forward results to rename registers allows subsequent instructions to access the new values before they have been written back to the architectural registers. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 205 Results in the write-back buffer cannot be flushed. If an exception occurs, results from previous instructions must write back before the exception is taken. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 206: Instruction Timing Overview
Finish Stage 4 Stage 4 Stage 4 Stage 5 Stage 6 Maximum two-instruction Completion Stage completion per clock cycle Write-Back Stage Figure 4-1. Instruction Flow Pipeline Diagram Showing Pipeline Stages PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 207: E500 Instruction Flow Diagram-Details
Completion queue (in program order) CQ13 CQ12 CQ11 • • • 1 or 2 instructions complete per clock cycle. Last event in the completion stage is retirement. Figure 4-2. e500 Instruction Flow Diagram—Details PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 208 — Space must be available in the CQ for an instruction to decode and dispatch. In this chapter, dispatch is treated as an event at the end of the decode stage. Dispatch dependencies are described in Section 4.7.2, “Dispatch Unit Resource Requirements.” PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 209: Gpr Issue Queue (Giq)
— Two simple units (SU1 and SU2)—execute move to/from SPR instructions, logical instructions, and all computational instructions except multiply and divide instructions. These execution units also execute all vector and scalar computational instructions PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 210 If no dependencies exist, as many as two instructions are retired in program order. Section 4.7.4, “Completion Unit Resource Requirements” describes completion dependencies. The write-back stage occurs in the clock cycle after the instruction is retired. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 211: Execution Pipeline Stages And Events
CQ and in one of the two issue queues. • Issue (at the end of the issue stage)—The issue stage ends when the instruction is issued to the appropriate execution unit. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 212: General Timing Considerations
The e500 executes multiple instructions in parallel, using hardware to handle dependencies. When an instruction is issued, source data is provided to the appropriate reservation station from either the architected register (GPR or CRF) or from a rename register. PowerPC e500 Core Family Reference Manual, Rev. 1 4-10 Freescale Semiconductor...
Page 213: General Instruction Flow
The dispatch rate is affected by the serializing behavior of some instructions and the availability of issue queues and CQ entries. Instructions are dispatched in program order; an instruction in IQ1 cannot be dispatched ahead of one in IQ0. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 4-11...
Page 214: Instruction Fetch Timing Considerations
• An instruction TLB error interrupt occurs when the effective address translation for a fetch is not found in the TLBs. This interrupt is described in detail in Section 5.7.13, “Instruction TLB Error Interrupt.” PowerPC e500 Core Family Reference Manual, Rev. 1 4-12 Freescale Semiconductor...
Page 215: Cache-Related Latency
Where caching is permitted, memory is configured as either write-back or write-through, as described in Section 11.3.4, “WIMGE Settings and Effect on L1 Caches .” PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 4-13...
Page 216: Dispatch, Issue, And Completion Considerations
Program-related exceptions are signaled when the instruction causing the exception reaches CQ0. Previous instructions are allowed to complete before the exception is taken, which ensures that any exceptions those instructions may cause are taken. PowerPC e500 Core Family Reference Manual, Rev. 1 4-14 Freescale Semiconductor...
Page 217: Gpr And Cr Rename Register Operation
Only mfcr and mfspr[XER] are move-from serialized, so that they do not examine architectural state until all older instructions that could affect the architectural state have completed. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 4-15...
Page 218: Interrupt Latency
• For guarded loads, the data must be returned. If a bus error occurs on a guarded load, the load is aborted and the interrupt is taken. PowerPC e500 Core Family Reference Manual, Rev. 1 4-16 Freescale Semiconductor...
Page 219: Memory Synchronization Timing Considerations
It may be used, for example, to ensure that reads and writes to an I/O device or between I/O devices occur in program order or to ensure that memory updates occur before a semaphore is released. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 4-17...
Page 220: Execution
Branch instructions are not folded on the e500; all branch instructions receive a CQ entry (and CRF and GPR renames) at dispatch and must write back in program order. PowerPC e500 Core Family Reference Manual, Rev. 1 4-18 Freescale Semiconductor...
Page 221: Branch Completion (Lr/Ctr Write-Back)
GIQ. The cmp is retired from the CQ at the end of cycle 4. In cycle 5, bc, add1, and add2 finish execution, and bc and add1 retire. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 4-19...
Page 222: Btb Branch Prediction And Resolution
(the branch execute unit, the BIQ, and the IQ). The presence of speculative branches allocated in the BTB slightly reduces speculation depth. PowerPC e500 Core Family Reference Manual, Rev. 1 4-20...
Page 223: Btb Operations
BTB locking APU can be used to lock all possible addresses whose fetch groups may contain the branch instruction. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 224: Fetch Group Addresses
Possible FGAs are a0…ai Is an IB at location j where Possible FGAs are aj+1…ai j=i-1,i-2,i-3? Possible FGAs are ai-3, ai-2, ai-1, ai Figure 4-9. Fetch Group Addresses PowerPC e500 Core Family Reference Manual, Rev. 1 4-22 Freescale Semiconductor...
Page 225: Btb Locking
The typical sequence of instructions to clear locked entries individually is as follows: mtspr BBEAR, rS bbelr To guarantee atomicity, these instruction sequences should be protected by lwarx and stwcx. instructions. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 4-23...
Page 226: Btb Locking Apu Programming Model
• BTB lock clearing. BUCSR[BBLFC] is used to perform a flash lock clear (unlocking) of all locked BTB entries. Writing BUCSR[BBLFC] with a 0 and then a 1 flash lock clears all locked BTB entries. PowerPC e500 Core Family Reference Manual, Rev. 1 4-24 Freescale Semiconductor...
Page 227: Btb Special Cases-Phantom Branches And Multiple Matches
Operations,” for more information on architectural coherency implications of load/store operations and the LSU on the core complex. Also, see Section 4.4.4, “Load/Store Execution,” for more information on other aspects of the LSU and instruction scheduling considerations. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 4-25...
Page 228: Cache/Core Interface Unit Integration
• The LSU tries to perform a load miss, all of the DLFB entries are full, and the load is not to any of the cache lines that are represented in the DLFB. PowerPC e500 Core Family Reference Manual, Rev. 1 4-26...
Page 229: Simple And Multiple Unit Execution
0.0 All others efddiv x All double-precision floating-point divides (e500v2 only) evfsdiv x rA or rB are 0.0 for both upper and lower All others PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 4-27...
Page 230: Mu Divide Execution
5 mulli 6 mulli 7 mulli 8 mulli 3 mulli 4 mulli 5 mulli 6 divw 1 mulli 7 Figure 4-11. MU Divide Bypass Path (Showing an 11-Cycle Divide) PowerPC e500 Core Family Reference Manual, Rev. 1 4-28 Freescale Semiconductor...
Page 231: Mu Floating-Point Execution
The LSU executes instructions that move data between the GPRs and the memory unit of the core (made up of the L1 caches and the core interface unit buffers). Figure 4-10 shows the block diagram for the LSU. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 4-29...
Page 232: Effect Of Operand Placement On Performance
If a system has multiple bus devices, one device may experience long memory latencies while another device (for example, a direct-memory access controller) is using the external bus. PowerPC e500 Core Family Reference Manual, Rev. 1 4-30 Freescale Semiconductor...
Page 233: Instruction Latency Summary
Latency depends on bus response time. mfcr Move-from SU1 only mfspr[XER] mfmsr None mfpmr None SU1 only 3, 4 mfspr[CTR] None SU1 or SU2 mfspr[LR] mfspr[DBSR] Presync, postsync SU1 only mfspr[SSCR] Presync SU1 only PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 4-31...
Page 234 1 per 4 cycles for mtctr followed by mtctr. mtlr stalls in decode until any other outstanding mtlr finishes. Throughput of 1 per 4 cycles for mtlr followed by mtlr. PowerPC e500 Core Family Reference Manual, Rev. 1 4-32...
Page 235 SU1 or SU2 1 andi. SU1 or SU2 1 andis. SU1 or SU2 1 and[.] SU1 or SU2 1 SU1 or SU2 1 cmpi SU1 or SU2 1 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 4-33...
Page 236 SU1 or SU2 1 subfc[o][.] SU1 or SU2 1 subfe[o][.] SU1 or SU2 1 subfic SU1 or SU2 1 subfme[o][.] SU1 or SU2 1 subfze[o][.] SU1 or SU2 1 PowerPC e500 Core Family Reference Manual, Rev. 1 4-34 Freescale Semiconductor...
Page 237 — dcblc — dcbst Store dcbt — dcbtls — dcbtst — dcbtstls — dcbz Store evldd — evlddx — evldh — evldhx — evldw — evldwx — evlhhesplat — PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 4-35...
Page 238 Store serialized, icbt CT=0 0 (no-op ) — icbt CT=1 — icbtls Latency is long and depends on memory Pre- and postsync serialized. latency, as well as other resource availability. PowerPC e500 Core Family Reference Manual, Rev. 1 4-36 Freescale Semiconductor...
Page 239 Latency depends on bus response time. Store and postsync serialized. Store stbu Store stbux Store stbx Store Store sthbrx Store sthu Store sthux Store sthx Store stmw 3 + n Store Store stwbrx Store PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 4-37...
Page 240 Table 4-8. SPE and Embedded Floating-Point APU Instruction Latencies Mnemonic Unit Cycles (Latency:Throughput) brinc SU1 or SU2 1 efdabs efdadd efdcfsf efdcfsi efdcfuf efdcfui efdcmpeq efdcmpgt efdcmplt efdctsf efdctsi efdctsiz efdctuf efdctui efdctuiz efddiv efdmul PowerPC e500 Core Family Reference Manual, Rev. 1 4-38 Freescale Semiconductor...
Page 241 SU1 or SU2 1 efssub efststeq SU1 or SU2 4:1 efststgt SU1 or SU2 1 efststlt SU1 or SU2 1 evabs evaddiw evaddsmiaaw evaddssiaaw evaddumiaaw evaddusiaaw evaddw evand PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 4-39...
Page 242 4 (if either rA or rB is 0.0) 29 (all other cases) evfsmul evfsnabs evfsneg evfssub PowerPC e500 Core Family Reference Manual, Rev. 1 4-40 Freescale Semiconductor...
Page 243 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 4-41...
Page 244 PowerPC e500 Core Family Reference Manual, Rev. 1 4-42 Freescale Semiconductor...
Page 245 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 4-43...
Page 246: Instruction Scheduling Guidelines
• Avoid branches where possible; favor not-taken branches over taken branches. The following sections give detailed information on optimizing code for e500 pipeline stages. PowerPC e500 Core Family Reference Manual, Rev. 1 4-44 Freescale Semiconductor...
Page 247: Fetch/Branch Considerations
• Decoding stops if there are no free entries in the GIQ, even if the next instruction to decode is to the BU or does not require an issues queue slot. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 248: Dispatch Groupings
CQ0–CQ1, where CQ0 is located at the end of the CQ (see PowerPC e500 Core Family Reference Manual, Rev. 1 4-46...
Page 249: Completion Groupings
Each SU has one reservation station in which instructions are held until operands are available. Also note that some SU1 instructions take more than one cycle and that some are not fully PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 250: Mu Considerations
(as in a partial address alias case of store to load)—the arbiter gives higher priority to the store, guaranteeing forward progress. PowerPC e500 Core Family Reference Manual, Rev. 1 4-48 Freescale Semiconductor...
Page 251: Misalignment Effects
• Accesses that cross a translation boundary where the endianness changes cause a byte-ordering DSI exception. • Future generations of high-performance microprocessors that implement the PowerPC architecture may experience greater misalignment penalties. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 4-49...
Page 252: Load Miss Pipeline
Here, the load misses in the data cache and the full line is reloaded into the data cache. Table 4-10. Data Cache Miss, L2 Cache Hit Timing Instruction lwz r4,0x0(r9) Miss LMQ0 LMQ0/E2 add r5,r4,r3 — — — — — PowerPC e500 Core Family Reference Manual, Rev. 1 4-50 Freescale Semiconductor...
Page 253: Interrupts And Exceptions
Critical input and watchdog timer critical interrupts can be masked by the critical enable bit, MSR[CE]. Debug events can be masked by the debug enable bit MSR[DE]. Book E PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 254: E500 Interrupt Definitions
(instead of ESR). See Section 2.7.2.4, “Machine Check Syndrome Register (MCSR),” for a description of the MCSR. The core complex reports the machine check exception as described in Section 5.7.2, “Machine Check Interrupt.” PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 255 Single-Precision Floating-Point Vector Single-Precision Floating-Point Scalar — Double-Precision Floating-Point For more information, see the “Embedded Vector and Scalar Single-Precision Floating-Point APU Instructions,” section of the “Instruction Model” chapter of the EREF. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 256: Recoverability From Interrupts
APU instructions at the assembly level or that uses SPE intrinsics will require rewriting for upward compatibility with next-generation PowerQUICC devices. Freescale Semiconductor offers a libmoto_e500 library that uses SPE instructions. Freescale will also provide libraries to support next-generation PowerQUICC devices.
Page 257: Interrupt Registers
Instruction TLB error IVOR4 External input IVOR15 Debug IVOR5 Alignment VOR32 SPE APU unavailable IVOR6 Program IVOR33 Embedded floating-point data IVOR8 System call IVOR34 Embedded floating-point round IVOR10 Decrementer IVOR35 Performance monitor PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 258 (EIS) Set when a DSI occurs because icbtl or icblc is executed in user mode Data storage (MSR[PR] = 1) and MSR[UCLE] = 0 44–45 — Reserved, should be cleared. — PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 259 BUS_WAERR Bus write address error BUS_IBERR Bus instruction data bus error BUS_RBERR Bus read data bus error BUS_WBERR Bus write bus error BUS_IPERR Bus instruction parity error BUS_RPERR Bus read parity error PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 260: Exceptions
Invocation of an interrupt is precise. When the interrupt is invoked imprecisely, the excepting instruction does not appear to complete before the next instruction starts (because the invocation of the interrupt required to complete execution has not occurred). PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 261: Interrupt Classes
• The exception-causing instruction may appear not to have begun execution (except for causing the exception), may be partially executed, or may have completed, depending on the interrupt type. See Section 5.9, “Partially Executed Instructions.” • Architecturally, no instruction beyond the exception-causing instruction executed. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 262: Requirements For System Reset Generation
ESR setting to indicate the cause of the interrupt. PowerPC e500 Core Family Reference Manual, Rev. 1 5-10...
Page 263 • rfi, rfci, rfmci, or isync—Ensure that instructions in the new process execute in the new context PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 5-11...
Page 264: Interrupt Definitions
— MSR[DE], DBCR0[IDM] Return from interrupt SP, C — MSR[DE], DBCR0[IDM] — Interrupt taken SI, C — MSR[DE], DBCR0[IDM] — Unconditional debug event SI, C — MSR[DE], DBCR0[IDM] — PowerPC e500 Core Family Reference Manual, Rev. 1 5-12 Freescale Semiconductor...
Page 265: Critical Input Interrupt
In addition to MSR[CE], implementations may provide other ways to mask the critical input interrupt. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 5-13...
Page 266: Machine Check Interrupt
Machine check interrupts are typically caused by a hardware or memory subsystem failure or by an attempt to access an invalid address. They may be caused indirectly by execution of an PowerPC e500 Core Family Reference Manual, Rev. 1 5-14...
Page 267 Section 13.8, “Proper Reporting of Bus Faults.” For additional information, see Section 2.10.2, “Hardware Implementation-Dependent Register 1 (HID1).” If MSR[ME] is cleared, the processor enters checkstop state immediately on detecting the machine check condition. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 5-15...
Page 268: Core Complex Bus (Ccb) And L1 Cache Machine Check Errors
• A load instruction hits in the L1 data cache. • An instruction fetch hits in the L1 instruction cache. • A line is cast out of the L1 data cache. PowerPC e500 Core Family Reference Manual, Rev. 1 5-16 Freescale Semiconductor...
Page 269 BUS_WBERR Write data bus error signaled by write-through) (It is not particularly meaningful.) memory corruption. assertion of core_wr_errin_b input MCAR is set to an address on the cache line with the error. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 5-17...
Page 270: Cache Parity Error Injection
L1CSR0[CPE], then the field L1CSR0[CPI] will not be set. If the programmer attempts to set the field L1CSR1[ICPI] without setting the field L1CSR1[ICPE], then the field L1CSR1[ICPI] will not be set. PowerPC e500 Core Family Reference Manual, Rev. 1 5-18 Freescale Semiconductor...
Page 271: Data Storage Interrupt
See the section, “Atomic Update Primitives Using lwarx and stwcx.,” in the “Instruction Model” chapter of the EREF. icbt, dcbt, dcbtst, and dcba instructions cannot cause a data storage interrupt, regardless of the effective address. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 5-19...
Page 272: Instruction Storage Interrupt
The implementation cannot fetch the instruction in the byte order specified by the page’s endian attribute. exception The EIS defines that accesses that cross a page boundary such that endianness changes cause a byte-ordering exception. PowerPC e500 Core Family Reference Manual, Rev. 1 5-20 Freescale Semiconductor...
Page 273: External Input Interrupt
MSR[EE] is set when the external interrupt signal is asserted. In addition to MSR[EE], implementations may provide other ways to mask this interrupt. The e500 does not support additional masking mechanisms. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 5-21...
Page 274: Alignment Interrupt
For lmw and stmw with a non–word-aligned operand and for load and reserve and store conditional instructions with an misaligned operand, an implementation may yield boundedly undefined results instead of causing an alignment interrupt. A store conditional to a PowerPC e500 Core Family Reference Manual, Rev. 1 5-22 Freescale Semiconductor...
Page 275 Set only if the instruction causing the exception is a store and is cleared for a load All other defined ESR bits are cleared. Instruction execution resumes at address IVPR[32–47] || IVOR5[48–59] || 0b0000. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 5-23...
Page 276: Program Interrupt
For all program interrupts except an enabled exception when in an imprecise mode (see Table 5-19), set to the EA of the instruction that caused the interrupt. SRR1 Set to the MSR contents at the time of the interrupt. PowerPC e500 Core Family Reference Manual, Rev. 1 5-24 Freescale Semiconductor...
Page 277: System Call Interrupt
Set to the MSR contents at the time of the interrupt. CE, ME, and DE are unchanged. All other MSR bits are cleared. DIS is set. Instruction execution resumes at address IVPR[32–47] || IVOR10[48–59] || 0b0000. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 5-25...
Page 278: Fixed-Interval Timer Interrupt
0 in all others. The data written to the TSR is not direct data, but a mask. Writing a 1 causes the bit to be cleared; writing a 0 has no effect. PowerPC e500 Core Family Reference Manual, Rev. 1 5-26 Freescale Semiconductor...
Page 279: Watchdog Timer Interrupt
TLB error interrupt, but the processor does not have the reservation from a load and reserve instruction, Book E defines it as implementation-dependent whether a data TLB error interrupt occurs. The EIS defines that the interrupt is taken. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 5-27...
Page 280 TSIZED EPN[32–51] EPN of access X0, X1 X0D, X1D W, I, M, G, E WD, ID, MD, GD, ED RPN[32–51] Zeros PERMIS Zeros TLBSELD — TIDSELD[0–1] — TSIZED[0–3] — PowerPC e500 Core Family Reference Manual, Rev. 1 5-28 Freescale Semiconductor...
Page 281: Instruction Tlb Error Interrupt
The “Cache and MMU Background” chapter of the EREF describes how these values are set as defined by the EIS. Instruction execution resumes at address IVPR[32–47] || IVOR14[48–59] || 0b0000. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 5-29...
Page 282: Debug Interrupt
• Instruction address compare is only supported for effective addresses. • DVC is not supported. CSRR0, CSRR1, MSR, and DBSR are updated as shown in Table 5-28. Instruction execution resumes at address IVPR[32–47] || IVOR15[48–59] || 0b0000. PowerPC e500 Core Family Reference Manual, Rev. 1 5-30 Freescale Semiconductor...
Page 283: Eis-Defined Interrupts
APU instructions at the assembly level or that uses SPE intrinsics will require rewriting for upward compatibility with next-generation PowerQUICC devices. Freescale Semiconductor offers a libmoto_e500 library that uses SPE instructions. Freescale will also provide libraries to support next-generation PowerQUICC devices.
Page 284: Embedded Floating-Point Data Interrupt
• SPEFSCR[FRMC] = 0b11 (–∞) Note that although these SPEFSCR status bits can be updated by using an mtspr[SPEFSCR], interrupts occur only if they are set as the result of an arithmetic operation. PowerPC e500 Core Family Reference Manual, Rev. 1 5-32 Freescale Semiconductor...
Page 285: Performance Monitor Interrupt
In general, the PowerPC architecture permits load and store instructions to be partially executed, interrupted, and then restarted from the beginning upon return from the interrupt. To guarantee that a particular load or store instruction completes without being interrupted and restarted, software PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 5-33...
Page 286 2. Misaligned elementary load or store, or any multiple or string: All of the above listed under item 1, plus the following: — Alignment — Data storage (if the access crosses a protection boundary) — Debug (data address compare) PowerPC e500 Core Family Reference Manual, Rev. 1 5-34 Freescale Semiconductor...
Page 287: Interrupt Ordering And Masking
(or enable) a subsequent interrupt, if SRR1 contents have not been saved. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 5-35...
Page 288: Guidelines For System Software
Therefore, within the critical-class interrupt handler, both pairs of save/restore registers may contain data necessary to system software. PowerPC e500 Core Family Reference Manual, Rev. 1 5-36 Freescale Semiconductor...
Page 289: Interrupt Order
ESR and in any status registers associated with the particular exception type (such as the SPEFSCR). PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 290 Exception priorities within each instruction type are listed in the following sections. Priority is shown highest to lowest. PowerPC e500 Core Family Reference Manual, Rev. 1 5-38 Freescale Semiconductor...
Page 291: E500 Exception Priorities
Interrupt latency of the core complex is 8 cycles or less unless a guarded load or a cache-inhibited stwcx. instruction is in the last completion queue entry (CQ0). For specific information, see Section 4.3.4, “Interrupt Latency.” PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 5-39...
Page 292: Guarded Load And Cache-Inhibited Stwcx. Instructions
• Because a cache-inhibited stwcx. finishes as soon as the address tenure completes, there is no concern about hanging a cache-inhibited stwcx. in completion due to a write bus data error. PowerPC e500 Core Family Reference Manual, Rev. 1 5-40 Freescale Semiconductor...
Page 293: Power Management
O Asserted by the core anytime the internal functional clocks of the core complex are stopped (for example after integrated device logic asserts stop ). PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 294: Core And Integrated Device Power Management States
In addition to the power-management states, dynamic power management automatically stops clocking individual internal functional units whenever they are idle. The integrated logic may similarly stop clocking to idle device-level blocks. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 295: Power Management Control Bits
If MSR[WE] = 1, signals power management logic to initiate device nap mode. The core complex enters core-stopped state (with its time base enabled) after integrated device logic asserts stop . PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 296: Software Considerations For Power Management
HID0[DOZE,NAP,SLEEP] settings. To ensure a clean transition into and out of a power-saving mode, the following program sequence is recommended: msync mtmsr (WE) isync loop: br loop PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 297: Power Management Protocol
Core Timer Facilities (negating tben disables the time base.) Core Timer HID0[TBEN] Clock (Time Base) System clock ÷ HID0[SEL_TBCLK] tbint CCB Clock Figure 6-2. Example Core Power Management Handshaking PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 298: Interrupts And Power Management
(due to the normal latency of restarting internal clock distribution and initiating the interrupt request), and then negate as the interrupt is serviced. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 299: Performance Monitor
• The performance monitor mark bit in the MSR (MSR[PMM]). This bit controls which programs are monitored. • The move to/from performance monitor registers (PMR) instructions, mtpmr and mfpmr. • The external input, pm_event. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 300: Performance Monitor Apu Registers
PMC0 00000 10001 Performance monitor counter 1 PMC1 00000 10010 Performance monitor counter 2 PMC2 00000 10011 Performance monitor counter 3 PMC3 00100 10000 Performance monitor local control a0 PMLCa0 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 301 Performance monitor local control b1 UPMLCb1 01000 00010 Performance monitor local control b2 UPMLCb2 01000 00011 Performance monitor local control b3 UPMLCb3 01100 00000 Performance monitor global control 0 UPMGC0 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 302: Global Control Register 0 (Pmgc0)
• When the msb = 1 in PMC x and PMLCa x [CE] = 1. • When the time-base bit specified by TBSEL=1 and TBEE=1. 35–50 — Reserved, should be cleared. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 303: User Global Control Register 0 (Upmgc0)
37 38 40 41 47 48 FC FCS FCU FCM1 FCM0 CE — EVENT — Reset All zeros Figure 7-2. Local Control A Registers (PMLCa0–PMLCa3)/ User Local Control A Registers (UPMLCa0–UPMLCa3) PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 304: User Local Control A Registers (Upmlca0-Upmlca3)
For the e500, thresholding is supported only for PMC0 and PMC1. PMLCb works with the corresponding PMLCa register. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 305: User Local Control B Registers (Upmlcb0-Upmlcb3)
7.2.6 User Local Control B Registers (UPMLCb0–UPMLCb3) The contents of PMLCb0–PMLCb3 are reflected to UPMLCb0–UPMLCb3, which can be read by user-level software with mfpmr using PMR numbers in Table 7-2. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 306: Performance Monitor Counter Registers (Pmc0-Pmc3)
Initializing PMCs to overflowed values is strongly discouraged. If an overflowed value is loaded into a PMCn that held a non-overflowed value (and PMGC0[PMIE], PMLCan[CE], and MSR[EE] are set), an interrupt is generated before any events are counted. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 307: User Performance Monitor Counter Registers (Upmc0-Upmc3)
The APU defines instructions for reading and writing the PMRs as shown in Table 7-7. Table 7-7. Performance Monitor APU Instructions Name Mnemonic Syntax Move from Performance Monitor Register mfpmr rD,PMRN Move to Performance Monitor Register mtpmr PMRN,rS PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 308: Performance Monitor Interrupt
(supervisor or user) and the process (marked or unmarked) may be in at any time. If this state matches an individual state specified by the PMLCan[FCS,FCU,FCM1,FCM0] fields, the state for which monitoring is enabled, counting is enabled for PMCn. PowerPC e500 Core Family Reference Manual, Rev. 1 7-10 Freescale Semiconductor...
Page 309: Examples
32 bits to a counter register where the first counter’s overflow event acts like a carry out feeding the second counter. By defining the event of interest to be another PMC’s PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 310: Thresholding
PowerPC sequential execution model (speculative processing). • Speculative counts include speculative instructions that were later flushed. • Nonspeculative counts do not include speculative operations, which are flushed. PowerPC e500 Core Family Reference Manual, Rev. 1 7-12 Freescale Semiconductor...
Page 311 Branch Prediction and Execution Events Com:12 Branches finished Spec Includes all branch instructions Com:13 Taken branches finished Spec Includes all taken branch instructions PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 7-13...
Page 312 Misaligned load or store accesses translated. translated Com:35 Total allocated to DLFB Spec — Com:36 Loads translated and allocated to Spec Applies to same class of instructions as loads translated. DLFB PowerPC e500 Core Family Reference Manual, Rev. 1 7-14 Freescale Semiconductor...
Page 313 Fetch, Instruction Cache, Instruction Line Fill Buffer (ILFB), and Instruction Prefetch Events Com:59 Instruction L1 cache locks Nonspec Counts cache lines locked in the instruction L1 cache. (Counts a lock even if an overlock occurs.) PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 7-15...
Page 314 ILFB fetch miss cycles Spec Instances when the number of cycles between allocation in the ILFB C1:77 (entry 0) and write-back to the instruction L1 cache exceeds the threshold. PowerPC e500 Core Family Reference Manual, Rev. 1 7-16 Freescale Semiconductor...
Page 315 For chaining events, if a counter is configured to count its own overflow bit, that counter does not increment. For example, if PMC2 is selected to count PMC2 overflow events, PMC2 does not increment. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 316 Performance Monitor PowerPC e500 Core Family Reference Manual, Rev. 1 7-18 Freescale Semiconductor...
Page 317: Debug Support
2.13.4/2-48 DAC2 Data address compare 2 01001 11101 DBCR0 Debug control register 0 01001 10100 2.13.1/2-46 DBCR1 Debug control register 1 01001 10101 DBCR2 Debug control register 2 01001 10110 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 318: Instruction Set
Debug interrupts do not affect the save/restore registers, SRR0 and SRR1, and CSRR registers are not affected by the Return from Interrupt (rfi) instruction. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 319: Deviations From The Book E Debug Model
(DAC1 or DAC2 debug events). • Return debug events for the rfci instruction are not logged if MSR[DE] is cleared (debug interrupts are disabled). PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 320: Hardware Facilities
Auxiliary data register (LSRL) Service bus address register Service bus data register Bypass register TAP instruction register tdo_en MUX logic Controller trst tlmsel tap_en Figure 8-1. TAP Controller with Supported Registers PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 321: Tap Interface Signals
TRST must be asserted sometime during power-up for JTAG logic initialization. Note that if TRST is connected low, unnecessary power is consumed. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 322: Book E Debug Events
(DBCR0–DBCR2) for any debug event to set a DBSR bit and thereby cause a debug exception. Setting a DBSR bit causes a debug interrupt only if debug interrupts are enabled. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 323: Instruction Address Compare Debug Event
• DBCR1[IAC1US] specifies whether IAC1 debug events can occur in user mode, in supervisor mode, or in both. • DBCR1[IAC2US] specifies whether IAC2 debug events can occur in user mode, in supervisor mode, or in both. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 324: Effective Address Mode
(if no higher priority exception has caused an interrupt). Execution of the instruction causing the exception is suppressed, and CSRR0 is set to the address of the excepting instruction. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 325: Data Address Compare Debug Event
However, because execution of these instructions may generate write activity on the processor’s data bus, they are treated as writes with respect to debug events. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 326: Data Address Compare User/Supervisor Mode
DAC debug events, which can occur regardless of the values of MSR[DE] or DBCR0[IDM]. When a DAC debug event occurs, the corresponding DBSR bit (DAC1R, DAC1W, DAC2R, or DAC2W) is set to record the exception. PowerPC e500 Core Family Reference Manual, Rev. 1 8-10 Freescale Semiconductor...
Page 327: Trap Debug Event
In this case, CSRR0 contains the address of the instruction following the one that enabled the debug interrupt (by setting MSR[DE]). The debug interrupt handler can observe DBSR[IDE] to determine how to interpret the CSRR0 value. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 8-11...
Page 328: Branch Taken Debug Event
• A debug interrupt occurs immediately (if no higher priority exception has caused an interrupt). • CSRR0 is set to the address of the instruction following the one that caused the instruction complete debug exception. PowerPC e500 Core Family Reference Manual, Rev. 1 8-12 Freescale Semiconductor...
Page 329: Interrupt Taken Debug Event
MSR[DE] or a higher priority exception has caused an interrupt). • CSRR0 is loaded with the address of the instruction that would have executed next had the interrupt not occurred. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 8-13...
Page 330: Unconditional Debug Event
CSRR0 should be interpreted as the address associated with the instruction causing the debug exception or is simply the address of the instruction after the one that set MSR[DE], thereby enabling the delayed debug interrupt. PowerPC e500 Core Family Reference Manual, Rev. 1 8-14 Freescale Semiconductor...
Page 331: E500 Core Complex
PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor Part II-1...
Page 332 PowerPC e500 Core Family Reference Manual, Rev. 1 Part II-2 Freescale Semiconductor...
Page 333: Timer Facilities
• The fixed-interval timer is essentially a selected bit of the TB, which provides a means of signaling an exception whenever the selected bit transitions from 0 to 1, in a repetitive fashion. The fixed-interval timer is typically used to trigger periodic system maintenance PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 334: Timer Registers
Implementation,” describes how these bits interact with other registers. • Timer control register (TCR). Provides control information for the on-chip timer of the core complex. The core complex implements two fields not specified in Book E: TCR[WPEXT] PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 335: The E500 Timer Implementation
The system can then implement a reset strategy. The core can be reset by asserting hreset. No automatic resetting is done when a watchdog reset occurs. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 336: Alternate Time Base Apu
The e500v2 has added the ability to count transitions of the TBL bit selected by PMGC0[TBSEL]. This count is enabled by setting PMGC0[TBEE]. For specific information, see Chapter 7, “Performance Monitor.” PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 337: Auxiliary Processing Units (Apus)
(MSR).” • Cache block lock and unlock APU • Machine check APU • The e500v2 supports the alternate time base APU, described in Section 10.3, “Alternate Time Base APU.” PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 10-1...
Page 338: Branch Target Buffer (Btb) Locking Apu
“Branch Target Buffer (BTB) Locking Instructions.” Table 10-1. BTB Locking APU Instructions Name Mnemonic Syntax Branch Buffer Load Entry and Lock Set bblels — Branch Buffer Entry Lock Reset bbelr — PowerPC e500 Core Family Reference Manual, Rev. 1 10-2 Freescale Semiconductor...
Page 339: Btb Locking Apu Registers
Section 2.6.6, “Alternate Time Base Registers (ATBL and ATBU).” The effect of power-savings mode or core frequency changes on counting in the alternate time base is implementation-dependent. See the User’s Manual for details. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 10-3...
Page 340: Double-Precision Floating-Point Apu (E500 V2 Only)
10.4.2.1 Operational Modes Double-precision floating-point operations are governed by the setting of the mode bit in SPESCR. The mode bit defines how floating-point results are computed and how floating-point exceptions PowerPC e500 Core Family Reference Manual, Rev. 1 10-4 Freescale Semiconductor...
Page 341: Floating-Point Data Formats
Double-precision not-a-Numbers (NaNs) are represented by a maximum exponent field value (2047) and a fraction f which is non-zero. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 10-5...
Page 342: Overflow And Underflow
• evstdd—Vector Store Double Word of Double Word • evstddx—Vector Store Double Word of Double Word • evmergehi—Vector Merge High • evmergelo—Vector Merge Low These instruction descriptions follow the conventions used in the EREF. PowerPC e500 Core Family Reference Manual, Rev. 1 10-6 Freescale Semiconductor...
Page 343 FG and FX are cleared if an overflow, underflow, or invalid operation/input error is signaled, regardless of enabled exceptions. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 10-7...
Page 344 If the low element of rB is Infinity, Denorm, or NaN, SPEFSCR[FINV] is set. If SPEFSCR[FINVE] is set, an interrupt is taken, and rD is not updated. FG and FX are always cleared. PowerPC e500 Core Family Reference Manual, Rev. 1 10-8 Freescale Semiconductor...
Page 345 32:63 The unsigned fractional low element in rB is converted to a double-precision floating-point value using the current rounding mode and the result is placed into rD. Exceptions: None PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 10-9...
Page 346 Otherwise, the comparison proceeds after treating NaNs, Infinities, and Denorms as normalized numbers, using their values of ‘e’ and ‘f’ directly. PowerPC e500 Core Family Reference Manual, Rev. 1 10-10 Freescale Semiconductor...
Page 347 FG and FX are cleared. If floating-point invalid input exceptions are enabled, an interrupt is taken and the condition register is not updated. Otherwise, the comparison proceeds after treating NaNs, Infinities, and Denorms as normalized numbers, using their values of ‘e’ and ‘f’ directly. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 10-11...
Page 348 FG and FX are updated so the handler can perform rounding. PowerPC e500 Core Family Reference Manual, Rev. 1 10-12 Freescale Semiconductor...
Page 349 FG and FX are updated so the handler can perform rounding. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 350 FG and FX are updated to allow the handler to perform rounding . PowerPC e500 Core Family Reference Manual, Rev. 1 10-14...
Page 351 FG and FX are updated to allow rounding to be performed in the interrupt handler. FG and FX are cleared if an overflow, underflow, divide by zero, or invalid operation/input error is signaled, regardless of enabled exceptions. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 10-15...
Page 352 FG and FX bits are properly updated to allow rounding to be performed in the interrupt handler. FG and FX are cleared if an overflow, underflow, or invalid operation/input error is signaled, regardless of enabled exceptions. PowerPC e500 Core Family Reference Manual, Rev. 1 10-16 Freescale Semiconductor...
Page 353 If rA is Infinity, Denorm, or NaN, SPEFSCR[FINV] is set, and FG and FX are cleared. If SPEFSCR[FINVE] = 0, the results are the same as for a normalized number. If SPEFSCR[FINVE] = 1, an interrupt is taken and rD is not updated. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 10-17...
Page 354 FG and FX are updated to allow the interrupt handler to perform rounding. FG and FX are cleared if an overflow, underflow, or invalid operation/input error is signaled, regardless of enabled exceptions. PowerPC e500 Core Family Reference Manual, Rev. 1 10-18 Freescale Semiconductor...
Page 355 Infinities, and Denorms as normalized numbers, using their values of ‘e’ and ‘f’ directly. No exceptions are generated during the execution of efdtstgt. If strict IEEE 754 compliance is required, the program should use efdcmpgt. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 10-19...
Page 356 Infinities, and Denorms as normalized numbers, using their values of ‘e’ and ‘f’ directly. No exceptions are generated during the execution of efdtstlt. If strict IEEE 754 compliance is required, the program should use efdcmplt. PowerPC e500 Core Family Reference Manual, Rev. 1 10-20 Freescale Semiconductor...
Page 357 FG and FX are updated so the interrupt handler can perform rounding. FG and FX are cleared if an overflow, underflow, or invalid operation/input error is signaled, regardless of enabled exceptions. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 10-21...
Page 358: Embedded Floating-Point Results Summary
= 2047) Isa64NaN(fp) ≠ 0)) return ((fp = 2047) & (fp frac Isa64Infinity(fp) return ((fp = 2047) & (fp = 0)) frac // Determine if fp value is denormalized Isa64Denorm(fp) PowerPC e500 Core Family Reference Manual, Rev. 1 10-22 Freescale Semiconductor...
Page 359: Convert From Double-Precision Floating-Point To Integer Word With Saturation
10.4.5.2 Convert from Double-Precision Floating-Point to Integer Word with Saturation // Convert 64 bit floating point to integer/fractional signed = SIGN or UNSIGN round = ROUND or TRUNC fractional = F (fractional) or I (integer) PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 10-23...
Page 360 (guard | sticky) then ← 1 SPEFSCR FINXS // Round the result if ((round = ROUND) & (SPEFSCR = 0)) then FINXE if (SPEFSCR = 0b00) then // nearest FRMC PowerPC e500 Core Family Reference Manual, Rev. 1 10-24 Freescale Semiconductor...
Page 361: Convert To Double-Precision Floating-Point From Integer Word With Saturation
← 0 // clear U bit ← maxexp - sc result // Report sticky and guard bits ← 0 SPEFSCR ← 0 SPEFSCR ← v result frac 1:31 return result PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 10-25...
Page 362 Auxiliary Processing Units (APUs) PowerPC e500 Core Family Reference Manual, Rev. 1 10-26 Freescale Semiconductor...
Page 363: Overview
L1CSR1 bits), as follows: — Instruction cache: 1 parity bit per byte of instruction — Data cache: 1 parity bit per byte of data Section 11.2.3, “L1 Cache Parity.” PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 11-1...
Page 364 (ILFB). Then, the critical double word is written to the cache and instruction fetching can resume. PowerPC e500 Core Family Reference Manual, Rev. 1 11-2...
Page 365: Block Diagram
Operations,” for more information on architectural coherency implications of load/store operations and the LSU on the core complex. Also, see Section 4.4.4, “Load/Store Execution,” for more information on other aspects of the LSU and instruction scheduling considerations. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 11-3...
Page 366: Caching-Allowed Loads And The Lsu
L1 store queue). Also, using DLFB entries for stores, frees up entries in the L1 store queue. Multiple caching-allowed store misses are merged in the DLFB. See Section 11.6.1.4, “Store Miss Merging,” for more information. PowerPC e500 Core Family Reference Manual, Rev. 1 11-4 Freescale Semiconductor...
Page 367: Data Write Buffer (Dwb)
The CCB also captures snoop addresses for the L1 data cache and the memory reservation (lwarx and stwcx.) operations. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 11-5...
Page 368: L1 Cache Organization
(allowing misses under misses). Up to four misses can be pending in the load miss queue. See Section 4.4.2.1, “Load/Store Unit Queueing Structures,” for more information. PowerPC e500 Core Family Reference Manual, Rev. 1 11-6 Freescale Semiconductor...
Page 369: L1 Instruction Cache Organization
(allowing misses under misses). When a miss is actually updating the cache, subsequent accesses are blocked for 1 cycle. (But up to four instructions being loaded into the instruction cache can be forwarded to the instruction unit simultaneously.) PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 11-7...
Page 370: L1 Cache Parity
Parity checking on the CCB read buses is disabled by default and can be enabled by setting HID1[R1DPE] and HID1[R2DPE]. If a cache parity error is detected, a machine check interrupt occurs (as described in Section 5.7.2, “Machine Check Interrupt”). PowerPC e500 Core Family Reference Manual, Rev. 1 11-8 Freescale Semiconductor...
Page 371: Cache Parity Error Injection
The core complex data cache supports four-state cache coherency protocol for cache lines in the data cache.The four-state protocol (also referred to as MESI protocol) includes the additional shared state. This protocol supports efficient and frequent sharing of data between bus masters. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 11-9...
Page 372 (CT = 0) M, E, or S same dcbtst (CT = 0) dcbtst (CT = 1) dcbtstls (CT = 0) M or E same dcbtstls (CT = 0) S or I PowerPC e500 Core Family Reference Manual, Rev. 1 11-10 Freescale Semiconductor...
Page 373: Instruction Cache Coherency Model
Table 11-3. L1 Instruction Cache Coherency State Transitions Event Initial State Final State icbi V or I icblc (CT = 0) V or I same icbtls (CT = 0) V or I PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 11-11...
Page 374: Snoop Signaling
Table 11-5 describes state changes caused by the ikill snoop. Table 11-5. Instruction Cache Snoop Coherency State Transitions Event Initial State Final State ikill V or I PowerPC e500 Core Family Reference Manual, Rev. 1 11-12 Freescale Semiconductor...
Page 375: Wimge Settings And Effect On L1 Caches
There is no restriction on how the core complex performs instruction fetching from guarded memory, if the memory area is marked as execute-permitted (UX/SX = 1) in the TLBs. Note that PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 376: Load/Store Operations
CCB. Note that loads are considered performed at the L1 data cache only if the respective cache contains a valid copy of that address. Write-back stores PowerPC e500 Core Family Reference Manual, Rev. 1 11-14...
Page 377: Sequential Consistency Of Memory Accesses
As specified in Book E, the core complex requires that, for stwcx. to succeed, its EA must be to the same reservation granule as the EA of a preceding lwarx. The core complex makes reservations on behalf of aligned 32-byte blocks of the memory address space. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 11-15...
Page 378: L1 Cache Control
Data Cache Block Touch for Store dcbtstls Data Cache Block Touch for Store and Lock Set dcbz Data Cache Block Zero icbi Instruction Cache Block Invalidate icblc Instruction Cache Block Lock Clear PowerPC e500 Core Family Reference Manual, Rev. 1 11-16 Freescale Semiconductor...
Page 379 ESR[DLK] or ESR[ILK]. CUL indicates the unable-to-lock condition that results in a no-op and sets L1CSR1[ICUL] or L1CSR0[CUL]. Acronyms are used to signify the following interrupts: • DTLB (data TLB interrupt) • ALI (alignment interrupt) • DSI (data storage interrupt) PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 11-17...
Page 380: L1 Instruction And Data Cache Enabling/Disabling
To prevent the loss of data, modified cache lines must be flushed, as described in Section 11.5, “L1 Data Cache Flushing.” PowerPC e500 Core Family Reference Manual, Rev. 1 11-18 Freescale Semiconductor...
Page 381: L1 Instruction And Data Cache Line Locking/Unlocking
If MSR[UCLE] is set, the cache-locking instructions can be executed in user mode and do not cause a DSI for cache locking. However, they may still cause a DSI for access violations. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 11-19...
Page 382 4. Execute an rfi. Failure to update SRR0 to point to the instruction after the locking/unlocking instruction causes the exception handler to be repeatedly invoked for the same instruction. PowerPC e500 Core Family Reference Manual, Rev. 1 11-20 Freescale Semiconductor...
Page 383: Effects Of Other Cache Instructions On Locked Lines
The core complex allows flash clearing of the instruction and data cache lock bits under software control. Each cache’s lock bits can be independently flash cleared through the CLFC control bits in L1CSR0 and L1CSR1. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 11-21...
Page 384: L1 Data Cache Flushing
The bit should be set just before beginning a cache flush routine and should be cleared when the series of instructions is complete. 11.6 L1 Cache Operation This section describes operations performed by the L1 instruction and data caches. PowerPC e500 Core Family Reference Manual, Rev. 1 11-22 Freescale Semiconductor...
Page 385: Cache Miss And Reload Operations
The instruction cache operates similarly to the data cache when all eight ways of a set are locked. When the instruction cache is disabled (L1CSR1[ICE] = 0), instruction accesses bypass the instruction cache. These accesses are forwarded to the memory subsystem as caching-allowed and PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 11-23...
Page 386: Cache Allocation On Misses
The push operation propagates to the DWB and then to the CCB. PowerPC e500 Core Family Reference Manual, Rev. 1 11-24 Freescale Semiconductor...
Page 387: L1 Cache Block Replacement
Table 11-8. L1 PLRU Replacement Way Selection PLRU Bits Way Selected for Replacement B0 0 B1 0 B3 0 1 B4 0 1 B2 0 B5 0 1 B6 0 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 11-25...
Page 388: Plru Bit Updates
No change No change No change No change No change No change No change No change No change Note that only three PLRU bits are updated for any access. PowerPC e500 Core Family Reference Manual, Rev. 1 11-26 Freescale Semiconductor...
Page 389: Cache Locking And Plru
An L2 cache may also recognize this transaction as a direction to establish and capture the cache line and mark it as locked. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 11-27...
Page 390: L2 Unlocking
L1 data cache. This write operation looks identical on the bus to the hit-to-modified case described Section 11.7.2, “L2 Locking.” PowerPC e500 Core Family Reference Manual, Rev. 1 11-28 Freescale Semiconductor...
Page 391: Memory Management Units
• No page table format is defined; software is free to use its own page table format. • TLBs maintained by system software through the TLB instructions and six (e500v1) or seven (e500v2) MAS registers PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 12-1...
Page 392 Also supports snooping of TLB1 and TLB0 for invalidation caused by tlbivax instructions executed by other masters. • IPROT bit implemented in TLB1 prevents invalidations, protecting critical entries (so designated by having the IPROT bit set) from being invalidated. PowerPC e500 Core Family Reference Manual, Rev. 1 12-2 Freescale Semiconductor...
Page 393: Tlb Entry Maintenance Features
Instruction permissions violation exception Causes ISI interrupt 12.5.2.1/12-24 Data permissions violation exception Causes DSI interrupt Other hardware assistance features for maintenance of the TLBs on the e500 are described in Section 12.5, “TLB Entry Maintenance—Details.” PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 12-3...
Page 394: Effective-To-Real Address Translation
4–20 bits* 12–28 bits* 32-bit Real Address Real Page Number Byte Address * Number of bits depends on page size (4 Kbytes–256 Mbytes) Figure 12-1. Effective-to-Real Address Translation Flow (e500v1) PowerPC e500 Core Family Reference Manual, Rev. 1 12-4 Freescale Semiconductor...
Page 395: Virtual Addresses With Three Pid Registers
TID field in all the TLBs. If any of the PID values in PID0–PID2 matches with a TLB entry in which all the other match criteria are met, that entry is used for translation. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 396: Variable-Sized
256 Mbyte e500v2 1 Gbyte 4 Gbyte For more information on the bit ranges of effective page numbers and offsets that are translated for these pages sizes, see the EREF. PowerPC e500 Core Family Reference Manual, Rev. 1 12-6 Freescale Semiconductor...
Page 397: Checking For Tlb Entry Hit
TLB entry are compared with attribute information of the access (read/write, instruction/data, user/supervisor) to see if the access is allowed to that page. The checking of permissions on the e500 functions as described in the EREF. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 12-7...
Page 398: Translation Lookaside Buffers (Tlbs)
This is also the case if an access results in a hit to multiple TLB entries in the L2 MMU. If this occurs, the TLB generates an invalid address and TLB entries may be corrupted (an exception is not reported). PowerPC e500 Core Family Reference Manual, Rev. 1 12-8 Freescale Semiconductor...
Page 399: L1 Tlb Arrays
TLB entry are then concatenated with the page offset of the original effective address; the bit range that is translated is determined by the page size. The result constitutes the real (physical) address for the access. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 12-9...
Page 400: L1 Mmu Tlb Organization
L1 MMUs that cause the LRU bits to be updated. The performance of the L1 MMUs is high, even though it is not possible to predict (externally) exactly which entry is the next to be replaced. PowerPC e500 Core Family Reference Manual, Rev. 1 12-10...
Page 401: L2 Tlb Arrays
Figure 12-6. Virtual Addresses TLB1 Compare Compare TLB0 way 1 Compare way 0 Compare Select Real Address (translated bits, depending on page size) Figure 12-6. L2 MMU TLB Organization—e500v1 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 12-11...
Page 402: Iprot Invalidation Protection In Tlb1
TLB miss exception. Entries with IPROT set can only be invalidated by writing a 0 to the valid bit of the entry (by using the MAS registers and executing the tlbwe instruction). PowerPC e500 Core Family Reference Manual, Rev. 1 12-12 Freescale Semiconductor...
Page 403: Replacement Algorithms For L2 Mmu
Also, note that the value of MAS0[NV] is indeterminate after any TLB entry invalidate operation (including a flash invalidate). If the software must know its value after an invalidate operation, MAS0[NV] must be explicitly read. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 12-13...
Page 404: Round-Robin Replacement For Tlb0-E500V1
MAS0[NV] for use by the next tlbwe instruction. tlbwe (if MAS0[TLBSEL] = 00) MAS0 selects way TLB0 ESEL 2-bit counter TLB miss (TLB error interrupt) if MAS4[TLBSELD] = 00 Figure 12-9. Round Robin Replacement for TLB0—e500v2 PowerPC e500 Core Family Reference Manual, Rev. 1 12-14 Freescale Semiconductor...
Page 405: Consistency Between L1 And L2 Tlbs
L1 TLB entries created for TID = 0. Therefore, it is recommended that TID = 0 be used as much as possible to maximize L1 TLB hit rates. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 406: L1 And L2 Tlb Access Times
Note that after an access with G = 1 is begun to the CCB, it is guaranteed to be completed. That is, after the address tenure is acknowledged on the CCB, the core completes the access, even if an asynchronous interrupt is pending. PowerPC e500 Core Family Reference Manual, Rev. 1 12-16 Freescale Semiconductor...
Page 407: Tlb Entry Field Definitions
TLBs. For example, data is read from the TLBs into the MAS registers with a TLB Read Entry (tlbre) instruction, and data is written to the TLBs from the MAS registers with a TLB Write Entry (tlbwe) instruction. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 12-17...
Page 408: Tlb Read Entry (Tlbre) Instruction
EPN[45–51] in MAS2 must be loaded with the desired index. After executing the tlbre instruction, MAS0–MAS3 (and optionally, MAS7 for the e500v2) are updated with the data from the selected TLB entry in TLB0. PowerPC e500 Core Family Reference Manual, Rev. 1 12-18 Freescale Semiconductor...
Page 409: Tlb Write Entry (Tlbwe) Instruction
MAS6. The values placed into MAS0, MAS1, MAS2, MAS3, and optionally, MAS7 differ, depending on whether a successful or unsuccessful search occurred. See Section 12.7.2, “MAS Register Updates,” for details on which MAS register fields are updated for these cases. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 12-19...
Page 410: Tlb Invalidate (Tlbivax) Instruction
Because the virtual address can be much larger than the physical address, the full virtual address specified by the tlbivax instruction cannot be broadcast to all devices. Instead, a subset address is broadcast that fits within the space of the implemented physical addressing model. PowerPC e500 Core Family Reference Manual, Rev. 1 12-20 Freescale Semiconductor...
Page 411: Tlb Selection For Tlbivax Instruction
(32–51) of address are broadcast and can be used in the invalidate comparison for TLB1, and most of those bits are masked out for larger page sizes, the TLBSEL field avoids unnecessary invalidations of large superpages in TLB1 when the tlbivax is targeting TLB0. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 12-21...
Page 412: Invalidate All Address Encoding For Tlbivax Instruction
• Automatic loading of the data exception address register (DEAR) with the effective address of the load, store, or cache management instruction that caused an alignment, data TLB miss (data TLB error interrupt), or permissions violation (DSI interrupt). PowerPC e500 Core Family Reference Manual, Rev. 1 12-22 Freescale Semiconductor...
Page 413: Automatic Updates-Tlb Miss Exceptions
TLB entry being loaded, then the TLB miss exception handler must update MAS0–MAS2 appropriately before performing the TLB write. See Section 12.5.2, “TLB Interrupt Routines,” for more information on the handling of TLB miss exceptions. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 12-23...
Page 414: Tlb Interrupt Routines
Other fields of TLB entries are set not set to a known state and software should be careful to insure that all fields of a TLB entry are appropriately initialized through the MAS registers before it is used for translation. PowerPC e500 Core Family Reference Manual, Rev. 1 12-24 Freescale Semiconductor...
Page 415: Core Complex Mmu Registers
Reference (Section/Page) (Section/Page) Process ID (PID0–PID2) 2.12.1/2-36 — MMU control and status register (MMUCSR0) 2.12.2/2-36 — MMU configuration register (MMUCFG) 2.12.3/2-37 — TLB configuration registers (TLB0CFG–TLB1CFG) 2.12.4/2-37 — PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 12-25...
Page 416: E500 Mas Registers
Table 12-8. MAS0 Field Descriptions—MMU Read/Write and Replacement Control Bits Name Descriptions 32–34 — Reserved, should be cleared. TLBSEL Selects TLB for access 0 TLB0 1 TLB1 36–43 — Reserved, should be cleared. PowerPC e500 Core Family Reference Manual, Rev. 1 12-26 Freescale Semiconductor...
Page 417: Mas Register 1 (Mas1)
Translation identity. An 8-bit field that defines the process ID for this TLB entry. TID is compared with the current process IDs of the three virtual address to be translated. A TID value of 0 defines an entry as global and matches with all process IDs. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 12-27...
Page 418: Mas Register 2 (Mas2)
0 Accesses to this page are considered cacheable. 1 The page is considered caching-inhibited. All loads and stores to the page bypass the caches and are performed directly to main memory. PowerPC e500 Core Family Reference Manual, Rev. 1 12-28 Freescale Semiconductor...
Page 419: Mas Register 3 (Mas3)
58–63 PERMIS Permission bits (UX, SX, UW, SW, UR, SR). User and supervisor read, write, and execute permission bits. See the EREF : . for more information on the page permission bits as they are defined by Book E. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 420: Mas Register 4 (Mas4)
Default G value. Specifies the default value to be loaded into MAS2[G] on a TLB miss exception. Default E value. Specifies the default value to be loaded into MAS2[E] on a TLB miss exception. Note that MAS5 is not implemented in the e500 core complex. PowerPC e500 Core Family Reference Manual, Rev. 1 12-30 Freescale Semiconductor...
Page 421: Mas Register 7 (Mas7)
Real page number, 4 high-order bits. MAS3 holds only RPN[4–23]. The byte offset within the page is provided by the EA and is not present in MAS3 or MAS7. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 12-31...
Page 422: Mas Register Updates
— — — — — — — SPID0 PID0 — — — — — — MSR[IS] for — — — — — — instruction access; MSR[DS] for data access PowerPC e500 Core Family Reference Manual, Rev. 1 12-32 Freescale Semiconductor...
Page 423: Core Complex Bus (Ccb)
The CCB derivation starts with the 60x bus, separates the bidirectional pins into unidirectional components (for system-on-chip use), and adds new attributes and capabilities to enhance data flow implementation or parallelism in certain system configurations. Note that this chapter does PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 13-1...
Page 424: Signal Summary
For burst writes and address-only transactions, ci is always negated. O Cache lock. Indicates L2 (level 2) cache lock status for the transaction; also asserted during a burst write for dcbf PowerPC e500 Core Family Reference Manual, Rev. 1 13-2 Freescale Semiconductor...
Page 425 JTAG test mode select. Decoded by the internal JTAG TAP controller to determine the primary operation of the test support circuitry JTAG test data input. The value present on the rising edge of tck is loaded into the selected JTAG test instruction or data register. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor 13-3...
Page 426 Machine check interrupt. Initiates a machine check operation. If MSR[ME] is set, the e500 vectors to IVOR1. If MSR[ME] is clear, then the e500 goes into checkstop state. MCSR is updated as defined in Section 2.7.2.4, “Machine Check Syndrome Register (MCSR).” PowerPC e500 Core Family Reference Manual, Rev. 1 13-4 Freescale Semiconductor...
Page 427: Core Interface Behavior
For write transactions, the core complex always supplies correct data parity across all byte lanes of the write data bus. If an internal parity error is detected in the L1 data cache during a castout PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 428: Msync Operation And The Bus
(L1 cache, bus, and system). On the bus, this ordering barrier is issued as an ORDER command (if HID1[ABE] is set through tt[0:4]). PowerPC e500 Core Family Reference Manual, Rev. 1 13-6 Freescale Semiconductor...
Page 429: Address Streaming Mode
A front-side L2 cache may recognize this transaction as a direction to establish the cache line (if not already valid) and to mark it as locked. Note that this is a complete PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 430: L2 Unlocking
For systems that require the implementation of atomic accesses without a requirement for bus snooping, a following option is recommended. A system-defined atomic operation could be implemented directly in the memory subsystem and keyed off of a unique bus transaction (such as PowerPC e500 Core Family Reference Manual, Rev. 1 13-8 Freescale Semiconductor...
Page 431: Remote Atomic Status Monitoring
This interrupt signalling typically PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 432 Section 11.3.4.5, “Speculative Accesses to Guarded Memory,” for a cautionary statement regarding memory areas that are set up as both cacheable and guarded. PowerPC e500 Core Family Reference Manual, Rev. 1 13-10 Freescale Semiconductor...
Page 433: Appendix A Programming Examples
Let addr be the location that is the common target of the load and reserve and store conditional instructions. Then the guarantee the architecture makes for the PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 434: Synchronization Primitives
PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 435: Fetch And Store
#loop if lost reservation This sequence can be changed to perform another Boolean operation atomically on a word in memory by changing the and to the desired Boolean instruction (or, xor, etc.). PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 436: Notes
The sequence shown above has the same weakness. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 437: Lock Acquisition And Release
In this example, the unlock procedure begins with an msync for this purpose. unlock: msync #order prior stores addi r1,r0,0 #before lock release r1,0(r3) #store 0 to lock location #return PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 438: List Insertion
#order stw before stwcx. loop2: lwarx r2,0,r3 #get it again cmpw r2,r5 #loop if changed (someone 4,2,loop1 # else progressed) stwcx. r4,0,r3 #add new element to list 4,2,loop #loop if failed PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 439: Notes
Section 3.3.1.7, “Atomic Update Primitives Using lwarx and stwcx.” For example, the first code sequence shown in Section A.1.3, “List Insertion,” can cause livelock if two list elements have next element pointers in the same reservation granule. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 440 Programming Examples PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 441: Appendix B Guidelines For 32-Bit Book E
— rldcl, rldcr, rldic, rldicl, rldicr, rldimi, sld, srad, sradi, srd — cntlzd, td, tdi • 64-bit extended addressing branch instructions—bcctre[l], bce[l][a], bclre[l], be[l][a] • 64-bit extended addressing cache management instructions—dcbae, dcbfe, dcbie, dcbste, dcbte, dcbtste, dcbze, icbie, icbte PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 442: Registers On 32-Bit Book E Implementations
TLB. This size provides support for a 32-bit effective address, which PowerPC ABIs may have come to expect to be available. 32-bit Book E implementations may support greater than PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 443: 32-Bit Book E Software Guidelines
0 be placed at address 0xFFFF_FFFC to emulate the wrap. Either of these approaches allows the application to execute on 32-bit and 64-bit Book E implementations. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 444 Guidelines for 32-Bit Book E PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 445: Appendix C Simplified Mnemonics For Powerpc Instructions
(for example, AltiVec instructions and Book E auxiliary processing units (APUs)). Simplified mnemonics have been added for new architecturally defined and new implementation-specific special-purpose registers (SPRs). These simplified mnemonics are described only in a very general way. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 446: Subtract Simplified Mnemonics
• Rotate—Rotate the contents of a register right or left n bits without masking. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 447: Operations On Words
3. Shift the contents of rA left 8 bits. slwi rA,rA,8 equivalent to rlwinm rA,rA,8,0,23 4. Clear the high-order 16 bits of rS and place the result into rA. clrlwi rA,rS,16 equivalent to rlwinm rA,rS,0,16,31 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 448: Branch Instruction Simplified Mnemonics
Table C-7). Incorporating the branch-if-true condition adds a ‘t’ to the simplified mnemonic, bdnzt. The equal condition that is specified by a BI value of 2 (indicating the EQ bit PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 449: Key Facts About Simplified Branch Mnemonics
C-2, encodes the following operations in conditional branch instructions: • Decrement count register (CTR) — And test if result is equal to zero — And test if result is not equal to zero PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 450: C-2 Bo Field (Bits 6–10 Of The Instruction Encoding)
Decrement the CTR, then branch if the decremented CTR ≠ 0; condition is TRUE. 0100 y dnzt 0101 y Decrement the CTR, then branch if the decremented CTR = 0; condition is TRUE. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 451: Incorporating The Bo Branch Prediction
For branches to an address in the LR or CTR (bclr[l] or bcctr[l]), coding the suffix ‘+’ causes the y bit to be set, and coding the suffix ‘–’ causes the bit to be cleared. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 452: The Bi Operand-Cr Bit And Field Representations
CR condition, the BI operand provides all 5 bits. For simplified branch mnemonics described in Section C.4.6, “Simplified Mnemonics that Incorporate CR Conditions (Eliminates BO and Replaces BI with crS),” the BI operand is PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 453: Specifying A Cr Bit
CR instructions, and others can also modify CR fields, so CR0 and CR1 may hold values that do not adhere to the meanings described in Table C-7. CR logical instructions, described in Section C.6, “Condition Register Logical Simplified Mnemonics,” can update individual CR bits. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 454: The Crs Operand
C.4.4.1.2 The crS Operand The crS symbols are shown in Table C-9. Note that either the symbol or the operand value can be used in the syntax used with the simplified mnemonic. PowerPC e500 Core Family Reference Manual, Rev. 1 C-10 Freescale Semiconductor...
Page 455: Simplified Mnemonics That Incorporate The Bo Operand
— CTR = 0 and condition false Simplified mnemonics for branch instructions that do not test CR bits should specify only a target. Otherwise a programming error may occur. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor C-11...
Page 456: Examples That Eliminate The Bo Operand
4,27,target bf 4*cr6+so,target would also work 5. Same as (4), but set the link register. This is a form of conditional call. bfl 27,target equivalent to bcl 4,27,target PowerPC e500 Core Family Reference Manual, Rev. 1 C-12 Freescale Semiconductor...
Page 457 BI field. See Section C.4.6, “Simplified Mnemonics that Incorporate CR Conditions (Eliminates BO and Replaces BI with crS).” PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor C-13...
Page 458 Decrement CTR, branch if CTR = 0 and condition false bclrl 2,BI bdzflrl BI — — Simplified mnemonics for branch instructions that do not test a CR bit should not specify one. A programming error may occur. PowerPC e500 Core Family Reference Manual, Rev. 1 C-14 Freescale Semiconductor...
Page 459: Simplified Mnemonics That Incorporate Cr Conditions (Eliminates Bo And Replaces Bi With Crs
Not less than (equivalent to ge) Not equal — Not greater than (equivalent to le) Summary overflow — Not summary overflow — Unordered (after floating-point comparison) — Not unordered (after floating-point comparison) — PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor C-15...
Page 460 CR field. If no field is specified, CR0 is used. The CR field symbols defined in Table C-9 (cr0–cr7) are used for this operand, as shown in examples 2–4 below. PowerPC e500 Core Family Reference Manual, Rev. 1 C-16 Freescale Semiconductor...
Page 461: Branch Simplified Mnemonics That Incorporate Cr Conditions: Examples
The value in the BI operand selects CR n [1], the GT bit. The value in the BI operand selects CR n [2], the EQ bit. The value in the BI operand selects CR n [3], the SO bit. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor C-17...
Page 462 ,target bnela crS target Branch if summary overflow bcl 12,BI ,target bsol crS target bcla 12,BI ,target bsola crS target Branch if unordered bunl crS target bunla crS target PowerPC e500 Core Family Reference Manual, Rev. 1 C-18 Freescale Semiconductor...
Page 463 The value in the BI operand selects CR n [1], the GT bit. The value in the BI operand selects CR n [2], the EQ bit. The value in the BI operand selects CR n [3], the SO bit. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor C-19...
Page 464: Compare Word Simplified Mnemonics
Equivalent to Condition register set crset bx creqv bx,bx,bx Condition register clear crclr bx crxor bx,bx,bx Condition register move crmove bx,by cror bx,by,by Condition register not crnot bx,by crnor bx,by,by PowerPC e500 Core Family Reference Manual, Rev. 1 C-20 Freescale Semiconductor...
Page 465: Trap Instructions Simplified Mnemonics
Logically not less than Logically not greater than — Unconditional The symbol ‘<U’ indicates an unsigned less-than evaluation is performed. The symbol ‘>U’ indicates an unsigned greater-than evaluation is performed. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor C-21...
Page 466 Trap instructions evaluate a trap condition as follows: The contents of rA are compared with either the sign-extended SIMM field or the contents of rB, depending on the trap instruction. PowerPC e500 Core Family Reference Manual, Rev. 1 C-22 Freescale Semiconductor...
Page 467: Simplified Mnemonics For Accessing Sprs
2. Copy the contents of IVOR0 to rS. mfivor0 rD equivalent to mfspr rD,400 3. Copy the contents of rS to the MAS1. mtmas1 rS equivalent to mtspr 625,rS PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor C-23...
Page 468: Recommended Simplified Mnemonics
The la mnemonic is useful for obtaining the address of a variable specified by name, allowing the assembler to supply the base register number and compute the displacement. If the variable v is PowerPC e500 Core Family Reference Manual, Rev. 1 C-24...
Page 469: Move Register (Mr
Move to Condition Register (mtcr) This mnemonic permits copying the contents of a GPR to the CR, using the same syntax as the mfcr instruction. mtcr rS equivalent to mtcrf 0xFF,rS PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor C-25...
Page 470: Eis-Specific Simplified Mnemonics
Decrement CTR, branch if CTR ≠ 0 (bc without LR bdnz target bc 16,0,target update) Decrement CTR, branch if CTR ≠ 0 (bca without LR bdnza target bca 16,0,target update) PowerPC e500 Core Family Reference Manual, Rev. 1 C-26 Freescale Semiconductor...
Page 471 Decrement CTR, branch if CTR = 0 and condition false (bc without LR update) bdzfa BI,target bca 2,BI,target Decrement CTR, branch if CTR = 0 and condition false (bca without LR update) PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor C-27...
Page 472 LR updating) beqlrl crS target bclrl 12,BI ,target Branch if equal (bclrl with comparison conditions and LR update) bf BI,target bc 4,BI,target Branch if condition false (bc without LR update) PowerPC e500 Core Family Reference Manual, Rev. 1 C-28 Freescale Semiconductor...
Page 473 Branch if greater than (bclrl with comparison conditions and LR update) ble crS target bc 4,BI ,target Branch if less than or equal (bc without comparison conditions or LR updating) PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor C-29...
Page 474 ,target Branch if not equal (bcctrl with comparison conditions and LR update) bnel crS target bcl 4,BI ,target Branch if not equal (bcl with comparison conditions and LR updating) PowerPC e500 Core Family Reference Manual, Rev. 1 C-30 Freescale Semiconductor...
Page 475 Branch if not summary overflow (bc without comparison conditions or LR updating) bnsa crS target bca 4,BI ,target Branch if not summary overflow (bca without comparison conditions or LR updating) PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor C-31...
Page 476 ,target Branch if summary overflow (bcla with comparison conditions and LR updating) bsolr crS target bclr 12,BI ,target Branch if summary overflow (bclr without comparison conditions and LR updating) PowerPC e500 Core Family Reference Manual, Rev. 1 C-32 Freescale Semiconductor...
Page 477 Condition register move crnot bx,by crnor bx,by,by Condition register not crset bx creqv bx,bx,bx Condition register set evmr rD,rA evor rD,rA,rA Vector Move Register evnot rD,rA evnor rD,rA,rA Vector Complement Register PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor C-33...
Page 478 12,rA,SIMM Trap if greater than or equal twgei rA,SIMM twi 12,rA,SIMM Trap immediate if greater than or equal twgt rA,SIMM tw 8,rA,SIMM Trap if greater than PowerPC e500 Core Family Reference Manual, Rev. 1 C-34 Freescale Semiconductor...
Page 479 The value in the BI operand selects CR n [0], the LT bit. The value in the BI operand selects CR n [1], the GT bit. The value in the BI operand selects CR n [3], the SO bit. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor C-35...
Page 480 Simplified Mnemonics for PowerPC Instructions PowerPC e500 Core Family Reference Manual, Rev. 1 C-36 Freescale Semiconductor...
Page 481: Appendix D Opcode Listings
1 0 1 1 1 0 1 0 1 0 0 addmeo addmeo. 0 1 1 1 1 1 1 0 1 1 1 0 1 0 1 0 1 addmeo. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 482 BI,target equivalent to bca 0,BI,target bdnzfa bdnzfl bdnzfl BI,target equivalent to bcl 0,BI,target bdnzfl bdnzfla bdnzfla BI,target equivalent to bcla 0,BI,target bdnzfla bdnzflr bdnzflr BI equivalent to bclr 0,BI bdnzflr PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 483 12,BI ,target beqa beqa crS,target equivalent to bca 12,BI ,target beqa beqctr beqctr crS,target equivalent to bcctr 12,BI ,target beqctr beqctrl beqctrl crS,target equivalent to bcctrl 12,BI ,target beqctrl PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 484 0 1 0 0 1 0 ble crS,target equivalent to bc 4,BI ,target blea blea crS,target equivalent to bca 4,BI ,target blea blectr blectr crS,target equivalent to bcctr 4,BI ,target blectr PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 485 4,BI ,target bnglr bnglrl bnglrl crS,target equivalent to bclrl 4,BI ,target bnglrl bnl crS,target equivalent to bc 4,BI ,target bnla bnla crS,target equivalent to bca 4,BI ,target bnla PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 486 12,BI ,target bsolr bsolrl bsolrl crS,target equivalent to bclrl 12,BI ,target bsolrl bt BI,target equivalent to bc 12,BI,target bta BI,target equivalent to bca 12,BI,target PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 487 0 1 0 0 1 1 crbD crbA crbB 0 0 1 1 1 0 0 0 0 1 / XL crnand PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 488 0 1 0 1 1 1 1 0 0 0 0 EFX efdcfui efdcmpeq 0 0 0 1 0 0 crfD 0 1 0 1 1 1 0 1 1 1 0 EFX efdcmpeq PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 489 0 1 0 1 1 0 1 1 0 0 0 EFX efsctuiz efsdiv 0 0 0 1 0 0 0 1 0 1 1 0 0 1 0 0 1 EFX efsdiv PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 490 0 1 0 1 0 0 0 0 0 0 0 EVX evfsadd evfscfsf 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 1 EVX evfscfsf PowerPC e500 Core Family Reference Manual, Rev. 1 D-10 Freescale Semiconductor...
Page 491 0 1 1 0 0 0 0 1 1 0 0 EVX evlhhousplatx evlwhe 0 0 0 1 0 0 UIMM 0 1 1 0 0 0 1 0 0 0 1 EVX evlwhe PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor D-11...
Page 492 1 0 1 0 0 0 0 0 0 0 1 EVX evmhessiaaw evmhessianw 0 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 EVX evmhessianw PowerPC e500 Core Family Reference Manual, Rev. 1 D-12 Freescale Semiconductor...
Page 493 EVX evmhousiaaw evmhousianw 0 0 0 1 0 0 1 0 1 1 0 0 0 0 1 0 0 EVX evmhousianw evmr evmr rD,rA equivalent to evor rD,rA,rA evmr PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor D-13...
Page 494 1 0 1 0 1 0 1 1 0 0 0 EVX evmwumiaa evmwumian 0 0 0 1 0 0 1 0 1 1 1 0 1 1 0 0 0 EVX evmwumian PowerPC e500 Core Family Reference Manual, Rev. 1 D-14 Freescale Semiconductor...
Page 495 0 1 1 0 0 1 1 1 1 0 0 EVX evstwwox evsubfsmiaaw 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 1 EVX evsubfsmiaaw PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor D-15...
Page 496 1 0 1 0 1 0 lhau 1 0 1 0 1 1 lhau lhaux 0 1 1 1 1 1 0 1 0 1 1 1 0 1 1 1 / lhaux PowerPC e500 Core Family Reference Manual, Rev. 1 D-16 Freescale Semiconductor...
Page 497 0 1 1 1 0 1 0 0 1 1 / XFX mtspr mulhw 0 1 1 1 1 1 / 0 0 1 0 0 1 0 1 1 0 mulhw PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor D-17...
Page 498 0 1 0 1 0 1 rlwinm rlwinm. 0 1 0 1 0 1 rlwinm. rlwnm 0 1 0 1 1 1 rlwnm rlwnm. 0 1 0 1 1 1 rlwnm. PowerPC e500 Core Family Reference Manual, Rev. 1 D-18 Freescale Semiconductor...
Page 499 0 1 1 1 1 1 0 0 0 0 1 0 1 0 0 0 0 subf PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor D-19...
Page 500 0 0 0 0 0 0 0 1 0 0 / tweq tweq rA,SIMM equivalent to tw 4,rA,SIMM tweq tweqi tweqi rA,SIMM equivalent to twi 4,rA,SIMM tweqi twge twge rA,SIMM equivalent to tw 12,rA,SIMM twge PowerPC e500 Core Family Reference Manual, Rev. 1 D-20 Freescale Semiconductor...
Page 501 0 1 1 0 1 1 UIMM xoris Simplified mnemonics for branch instructions that do not test a CR bit should not specify one; a programming error may occur. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor D-21...
Page 502: Instructions (Decimal And Hexadecimal) By Opcode
0 1 0 1 1 0 1 1 1 1 0 EFX efststeq efststgt crfD 0 1 0 1 1 0 1 1 1 0 0 EFX efststgt PowerPC e500 Core Family Reference Manual, Rev. 1 D-22 Freescale Semiconductor...
Page 503 EVX evfscmplt evfsctsf 0 1 0 1 0 0 1 0 1 1 1 EVX evfsctsf evfsctsi 0 1 0 1 0 0 1 0 1 0 1 EVX evfsctsi PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor D-23...
Page 504 0 1 1 0 0 0 1 0 1 0 0 EVX evlwhoux evlwhsplat UIMM 0 1 1 0 0 0 1 1 1 0 1 EVX evlwhsplat PowerPC e500 Core Family Reference Manual, Rev. 1 D-24 Freescale Semiconductor...
Page 505 EVX evmheumianw evmheusiaaw 1 0 1 0 0 0 0 0 0 0 0 EVX evmheusiaaw evmheusianw 1 0 1 1 0 0 0 0 0 0 0 EVX evmheusianw PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor D-25...
Page 506 EVX evmwhsmia evmwhssf 1 0 0 0 1 0 0 0 1 1 1 EVX evmwhssf evmwhssfa 1 0 0 0 1 1 0 0 1 1 1 EVX evmwhssfa PowerPC e500 Core Family Reference Manual, Rev. 1 D-26 Freescale Semiconductor...
Page 507 0 1 0 0 0 1 0 1 0 0 0 EVX evrlw evrlwi UIMM 0 1 0 0 0 1 0 1 0 1 0 EVX evrlwi PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor D-27...
Page 508 0 1 0 0 0 0 0 0 1 1 0 EVX evsubifw evxor 0 1 0 0 0 0 1 0 1 1 0 EVX evxor mulli SIMM mulli subfic SIMM subfic PowerPC e500 Core Family Reference Manual, Rev. 1 D-28 Freescale Semiconductor...
Page 509 0 0 0 0 1 1 0 0 1 0 / XL rfi rfmci 19 (0x13) 0 0 0 0 1 0 0 1 1 0 / XL rfmci rlwimi 20 (0x14) rlwimi PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor D-29...
Page 510 31 (0x1F) 0 0 0 0 0 1 1 1 0 0 0 and. 31 (0x1F) 0 0 0 0 0 1 1 1 0 0 1 and. PowerPC e500 Core Family Reference Manual, Rev. 1 D-30 Freescale Semiconductor...
Page 511 31 (0x1F) 1 1 1 0 0 1 1 0 1 0 1 extsh. icbi 31 (0x1F) 1 1 1 1 0 1 0 1 1 0 / icbi PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor D-31...
Page 512 31 (0x1F) 0 0 1 1 1 0 1 0 1 1 1 mullw. mullwo 31 (0x1F) 1 0 1 1 1 0 1 0 1 1 0 mullwo PowerPC e500 Core Family Reference Manual, Rev. 1 D-32 Freescale Semiconductor...
Page 513 31 (0x1F) 0 0 0 0 1 0 1 0 0 0 1 subf. subfc 31 (0x1F) 0 0 0 0 0 0 1 0 0 0 0 subfc PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor D-33...
Page 514 0 1 0 0 1 1 1 1 0 0 1 xor. 32 (0x20) lwzu 33 (0x21) lwzu 34 (0x22) lbzu 35 (0x23) lbzu 36 (0x24) stwu 37 (0x25) stwu PowerPC e500 Core Family Reference Manual, Rev. 1 D-34 Freescale Semiconductor...
Page 515: Instructions By Form
1 0 1 1 1 0 1 0 1 0 0 addmeo addmeo. 0 1 1 1 1 1 1 0 1 1 1 0 1 0 1 0 1 addmeo. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor D-35...
Page 516 0 1 1 1 0 0 1 0 1 1 1 divwu. divwuo 0 1 1 1 1 1 1 1 1 1 0 0 1 0 1 1 0 divwuo PowerPC e500 Core Family Reference Manual, Rev. 1 D-36 Freescale Semiconductor...
Page 517 / 0 0 0 0 0 1 0 1 1 0 mulhwu mulhwu. 0 1 1 1 1 1 / 0 0 0 0 0 1 0 1 1 1 mulhwu. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor D-37...
Page 518 0 0 0 0 1 0 1 0 0 0 0 subf subf. 0 1 1 1 1 1 0 0 0 0 1 0 1 0 0 0 1 subf. PowerPC e500 Core Family Reference Manual, Rev. 1 D-38 Freescale Semiconductor...
Page 519 0 1 0 0 0 0 0 1 0 0 0 0 bcla 0 1 0 0 0 0 bcla addi 0 0 1 1 1 0 SIMM addi PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor D-39...
Page 520 0 1 1 0 1 1 UIMM xoris efdabs 0 0 0 1 0 0 0 1 0 1 1 1 0 0 1 0 0 EFX efdabs PowerPC e500 Core Family Reference Manual, Rev. 1 D-40 Freescale Semiconductor...
Page 521 0 1 0 1 1 0 0 1 1 0 0 EFX efscmpgt efscmplt 0 0 0 1 0 0 crfD 0 1 0 1 1 0 0 1 1 0 1 EFX efscmplt PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor D-41...
Page 522 1 0 0 1 1 0 0 0 1 1 0 EVX evdivws evdivwu 0 0 0 1 0 0 1 0 0 1 1 0 0 0 1 1 1 EVX evdivwu PowerPC e500 Core Family Reference Manual, Rev. 1 D-42 Freescale Semiconductor...
Page 523 0 1 1 0 0 0 0 0 0 1 0 EVX evldwx evlhhesplat 0 0 0 1 0 0 UIMM 0 1 1 0 0 0 0 1 0 0 1 EVX evlhhesplat PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor D-43...
Page 524 1 0 1 0 0 0 0 1 0 0 1 EVX evmhesmiaaw evmhesmianw 0 0 0 1 0 0 1 0 1 1 0 0 0 1 0 0 1 EVX evmhesmianw PowerPC e500 Core Family Reference Manual, Rev. 1 D-44 Freescale Semiconductor...
Page 525 1 0 1 1 0 0 0 0 1 0 1 EVX evmhossianw evmhoumi 0 0 0 1 0 0 1 0 0 0 0 0 0 1 1 0 0 EVX evmhoumi PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor D-45...
Page 526 1 0 0 0 1 1 1 0 0 1 1 EVX evmwssfa evmwssfaa 0 0 0 1 0 0 1 0 1 0 1 0 1 0 0 1 1 EVX evmwssfaa PowerPC e500 Core Family Reference Manual, Rev. 1 D-46 Freescale Semiconductor...
Page 527 0 1 1 0 0 1 1 0 1 0 0 EVX evstwhox evstwwe 0 0 0 1 0 0 UIMM 0 1 1 0 0 1 1 1 0 0 1 EVX evstwwe PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor D-47...
Page 528 0 0 1 0 0 0 0 0 0 1 / XL crandc creqv 0 1 0 0 1 1 crbD crbA crbB 0 1 0 0 1 0 0 0 0 1 / XL creqv PowerPC e500 Core Family Reference Manual, Rev. 1 D-48 Freescale Semiconductor...
Page 529 This field is defined as allocated by the Book E architecture, for possible use in an implementation. These bits are not implemented in the e500. d = UIMM * 8 d = UIMM * 2 d = UIMM * 4 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor D-49...
Page 530 Opcode Listings PowerPC e500 Core Family Reference Manual, Rev. 1 D-50 Freescale Semiconductor...
Page 531: Appendix E Revision History
Appendix E Revision History This appendix provides a list of major differences between revisions of the PowerPC e500 Core Reference Manual. NOTE While previous revisions of this manual covered only the e500v1 core, referring to it simply as the e500 core, this revision includes coverage of both the e500v1 and e500v2 cores.
Page 532: Instruction Model
Section 11.2.4, “Cache Changed name of L1CSR0[PEIE] to CPI and L1CSR1[IPEIE] to ICPI. Added requirement to have Parity Error Injection” cache parity checking enabled if cache parity injection is enabled. PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 533 Removed references to SHAREN, SHAREND, MEI Management Units” Section 12.2, Corrected bit number compositions in effective-to-real address translation figures, Figure 12-1 “Effective-to-Real Address Figure 12-2 Translation” Chapter 13, “Core Complex Added chapter (CCB)” PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 534 Revision History PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 535 (instruction select) APU, 3-25, 3-60 speculative copies of LR and CTR, 4-15 machine check interrupt APU, 3-63, 5-2 Branch target buffer (BTB) branch unit control and status register (BUCSR), 2-26 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor Index-1...
Page 536: Execution Timing
Context synchronization, 3-11, 3-44 coherency required bit (M bit), 11-12 Conventions global signaling, M bit , and snooping, 11-12 execution timing terminology, 4-1 instruction cache coherency model, 11-8, 11-11 PowerPC e500 Core Family Reference Manual, Rev. 1 Index-2 Freescale Semiconductor...
Page 537 8-12 instructions, 1-13 data address compare, 8-9 interrupts, 5-32 instruction address compare, 8-7 see also Interrupt handling instruction complete debug event, 8-12 Embedded single-precision floating-point (SPFP) APUs PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor Index-3...
Page 538 4-18–4-25 write-back, 4-8, 4-9 branch prediction, 4-1, 4-11, 4-20–4-25 instruction unit see also Branch target buffer (BTB) instruction line fill buffer (ILFB), 11-5 completion, 4-18 integer instructions PowerPC e500 Core Family Reference Manual, Rev. 1 Index-4 Freescale Semiconductor...
Page 539 Book E signal processing engine (SPE) APU, 5-3 64-bit–specific, B-1 Freescale Book E implementation standards (EIS) Book E, see Book E architecture oveview, 1-3 branch, 4-18–4-25 condition register logical, 3-25 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor Index-5...
Page 540 3-12 SPE and SPFP descriptions, 3-49 ISI (instruction storage interrupt), 5-20–5-21, 12-24 speculative instructions, 4-3 machine check interrupt, 1-22, 2-30, 5-2, 5-14–5-18, SPFP (single-precision floating-point) APUs, 3-58 13-9 PowerPC e500 Core Family Reference Manual, Rev. 1 Index-6 Freescale Semiconductor...
Page 541 IVOR0–IVOR15, IVOR32–IVOR35 (vector offset registers), 2-19, 5-5 Machine check interrupt APU, 1-22, 3-63, 5-14–5-18 IVPR32–IVPR47 (vector prefix registers), 2-19, 5-5 see also Interrupt handling MAS0–MAS4, MAS6–MAS7 (MMU assist registers), 1-27, 2-39–2-45, 12-26–12-31 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor Index-7...
Page 542 (general), 12-13 msync, 3-31, 3-46, 4-17, 13-6 replacement algorithm, hints for round robin (TLB0), mtmsr, 3-40 12-13 mtspr, 3-26 structure, 12-11 TLB0 (4 Kbyte page sizes), 12-11, 12-18 PowerPC e500 Core Family Reference Manual, Rev. 1 Index-8 Freescale Semiconductor...
Page 543 2-9–2-10 superscalar diagram, 4-4, 4-5 condition register (CR), 2-9 PIR (processor ID register), 2-12 count register (CTR), 2-10 link register (LR), 2-10 disabling for power savings, 6-3 BTB, 10-3 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor Index-9...
Page 544 3-49, 3-52 user global control 0 (UPMGC0), 7-5 execution latencies, 4-38 user local control A (UPMLCa0–UPMLCa3), 2-56, 7-6 interrupts, 5-3 user local control B (UPMLCb0–UPMLCb3), 2-57, 7-7 registers PowerPC e500 Core Family Reference Manual, Rev. 1 Index-10 Freescale Semiconductor...
Page 545 TLBs, 12-8–12-17 execution synchronization, 3-11 L1 TLB arrays, 12-9 general, A-1 L2 TLB arrays, 12-11 memory instructions, 3-30 synchronization requirements, 3-6, 3-10 timing considerations, 4-17–4-18 TLB entry field definitions, 12-17 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor Index-11...
Page 546 5-27 see also Interrupt handling Weakly ordered memory references, 1-29, 11-14 Write-back definition, 4-3, 4-8, 4-9 wrtee, 3-40 wrteei, 3-40 XER (integer exception register), 2-2, 2-9 PowerPC e500 Core Family Reference Manual, Rev. 1 Index-12 Freescale Semiconductor...
Page 547: Interrupts And Exceptions
Part I—e500 Core Core Complex Overview Register Model Instruction Model Execution Timing Interrupts and Exceptions Power Management Performance Monitor Debug Support Part II—e500 Core Complex Timer Facilities Auxiliary Processing Units (APUs) L1 Caches Memory Management Units Core Complex Bus (CCB) Appendix A—Programming Examples Appendix B—Guidelines for 32-Bit Book E Appendix C—Simplified Mnemonics for PowerPC Instructions...
Page 548: Power Management
Part I—e500 Core Core Complex Overview Register Model Instruction Model Execution Timing Interrupts and Exceptions Power Management Performance Monitor Debug Support Part II—e500 Core Complex Timer Facilities Auxiliary Processing Units (APUs) L1 Caches Memory Management Units Core Complex Bus (CCB) Appendix A—Programming Examples Appendix B—Guidelines for 32-Bit Book E Appendix C—Simplified Mnemonics for PowerPC Instructions...

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