Freescale Semiconductor PowerPC e500 Core Manuals

Manuals and User Guides for Freescale Semiconductor PowerPC e500 Core. We have 1 Freescale Semiconductor PowerPC e500 Core manual available for free PDF download: Reference Manual

Freescale Semiconductor PowerPC e500 Core Reference Manual (548 pages)

Brand: Freescale Semiconductor | Category: Motherboard | Size: 3.62 MB

Table of Contents
5
Paragraph Page

6
Number Title Number

6
Figure Page

24
Number Title Number

24
- Powerpc E500 Core Family Reference Manual
  24
  - About this Book
    31
  - Audience
    32
  - Organization
    32
  - Core Complex Overview
    32
  - Suggested Reading
    33
    
    General Information
    33
    
    Related Documentation
    34
  - Conventions
    34
  - Terminology Conventions
    35
    
    Part I E500 Core
    37
    
    Register Model
    37
Chapter 1 Core Complex Overview

39
- Overview
  39
  - E500 Core Complex Block Diagram
    40
- Upward Compatibility
  41
- Core Complex Summary
  41
- E500 Processor and System Version Numbers
  43
- Features
  43
- Vector and Floating-Point Apus
  44
  - Four-Stage MU Pipeline, Showing Divide Bypass
    46
  - Three-Stage Load/Store Unit
    47
- E500V2 Differences
  49
- Instruction Set
  50
- Instruction Flow
  52
- Initial Instruction Fetch
  52
- Branch Detection and Prediction
  52
- E500 Execution Pipeline
  54
  - GPR Issue Queue (GIQ)
    55
- Programming Model
  56
  - E500 Core Programming Model
    57
- On-Chip Cache Implementation
  58
- Interrupts and Exception Handling
  58
- Exception Handling
  58
- Interrupt Classes
  59
- Interrupt Types
  59
- Upper Bound on Interrupt Latencies
  60
- Interrupt Registers
  60
- Memory Management
  62
  - MMU Structure
    63
- Address Translation
  64
- MMU Assist Registers (MAS0-MAS4 and MAS6-MAS7)
  65
- Process ID Registers (PID0-PID2)
  66
- TLB Coherency
  66
- Memory Coherency
  67
- Atomic Update Memory References
  67
- Memory Access Ordering
  67
- Cache Control Instructions
  67
- Programmable
  68
- Core Complex Bus (CCB)
  68
- Performance Monitoring
  68
- Global Control Register
  69
- Performance Monitor Counter Registers
  69
- Local Control Registers
  69
- Legacy Support of Powerpc Architecture
  70
- Instruction Set Compatibility
  70
- User Instruction Set
  70
- Supervisor Instruction Set
  70
- Memory Subsystem
  71
- Exception Handling
  71
- Memory Management
  71
- Reset
  72
- Little-Endian Mode
  72
Chapter 2 Register Model

73
Synchronization with Tlbwe and Tlbivax Instructions

140
- Context Synchronization
  141
- Instruction-Related Interrupts
  142
  - Instruction Set Overview
    143
  - Integer Compare Instructions
    145
  - Integer Rotate and Shift Instructions
    146
- Load and Store Instructions
  147
  - Integer Load and Store Address Generation
    148
- Register Indirect with Index Addressing for Integer Loads/Stores
  149
- Branch and Flow Control Instructions
  153
  - Branch Instructions
    154
  - Condition Register Logical Instructions
    155
  - System Linkage Instruction
    156
Number

159
- Performance Monitor
  159
  - Memory Synchronization Instructions
    160
  - Mbar (MO = 1)
    161
  - Atomic Update Primitives Using Lwarx and Stwcx
    162
    
    Reservations
    164
    
    Forward Progress
    166
- Memory Control Instructions
  167
- User-Level Cache Instructions
  167
- Supervisor-Level Instructions
  169
- System Linkage Instructions
  169
- Supervisor-Level Cache Instruction
  170
- Supervisor-Level Memory Control Instructions
  170
- Supervisor-Level TLB Management Instructions
  171
- Recommended Simplified Mnemonics
  172
- Book E Instructions with Implementation-Specific Features
  173
- E500 Instructions
  173
- Context Synchronization
  174
- Memory Access Alignment Support
  174
- Acquire Lock and Import Shared Memory
  175
- Lock Acquisition and Import Barriers
  175
- Obtain Pointer and Import Shared Memory
  175
Using Msync and Mbar to Order Memory Accesses

175
- Export Shared Memory and Release Lock
  176
- Lock Release and Export Barriers
  176
Export Shared Memory and Release Lock Using Mbar (MO = 0)

177
- Safe Fetch
  177
- Update Instructions
  177
- EIS-Defined Instructions and Apus Implemented on the E500
  178
- Memory Synchronization
  178
- SPE and Embedded Floating-Point Apus
  179
- SPE and Floating-Point APU GPR Usage
  180
- SPE Operands: Signed Fractions
  181
- Integer and Fractional Operations
  182
- SPE APU Instructions
  182
- SPE Integer and Fractional Operations
  182
- Embedded Floating-Point APU Instructions
  188
Integer Select (Isel) APU

190
- Performance Monitor APU
  190
- Cache Locking APU
  191
- Branch Target Buffer (BTB) Locking Instructions
  193
- E500-Specific Instructions
  193
- Machine Check APU
  193
- Instruction Listing
  196
- Execution Timing
  203
- Terminology and Conventions
  203
- Instruction Timing Overview
  206
- E500 Instruction Flow Diagram-Details
  207
- GPR Issue Queue (GIQ)
  209
- Execution Pipeline Stages and Events
  211
- General Timing Considerations
  212
- General Instruction Flow
  213
- Instruction Fetch Timing Considerations
  214
- Interrupts Associated with Instruction Fetching
  214
- L1 and L2 TLB Access Times
  214
- Cache-Related Latency
  215
- Dispatch, Issue, and Completion Considerations
  216
- GPR and CR Rename Register Operation
  217
- Instruction Serialization
  217
- LR and CTR Shadow (Speculative) Registers
  217
- Interrupt Latency
  218
Msync Instruction Timing Considerations

219
- Branch Instructions and Completion
  220
- Branch Unit Execution
  220
- Execution
  220
- Branch Completion (LR/CTR Write-Back)
  221
- BTB Branch Prediction and Resolution
  222
- BTB Operations
  223
- Fetch Group Addresses
  224
- BTB Locking
  225
- BTB Locking APU Programming Model
  226
- BTB Operations Controlled by BUCSR
  226
- BTB Special Cases-Phantom Branches and Multiple Matches
  227
- Load/Store Unit Execution
  227
- Load/Store Unit Queueing Structures
  227
- Cache/Core Interface Unit Integration
  228
- Simple and Multiple Unit Execution
  229
- MU Divide Execution
  230
- Load/Store Execution
  231
- MU Floating-Point Execution
  231
- Effect of Operand Placement on Performance
  232
- Memory Performance Considerations
  232
- Instruction Latency Summary
  233
- Instruction Scheduling Guidelines
  246
- Dispatch Unit Resource Requirements
  247
- Dynamic Prediction Versus no Branch Prediction
  247
- Fetch/Branch Considerations
  247
- Position-Independent Code
  247
- Branch Issue Queue (BIQ)
  248
- Completion Unit Resource Requirements
  248
- Dispatch Groupings
  248
- General Issue Queue (GIQ)
  248
- Issue Queue Resource Requirements
  248
- Completion Groupings
  249
- Execution Unit Considerations
  249
- Serialization Effects
  249
- SU Considerations
  249
- Load/Store Interaction
  250
- LSU Considerations
  250
- MU Considerations
  250
- Misalignment Effects
  251
- Load Miss Pipeline
  252
- Interrupts and Exceptions
  253
- Overview
  253
- E500 Interrupt Definitions
  254
- Recoverability from Interrupts
  256
- Interrupt Registers
  257
- Exceptions
  260
- Interrupt Classes
  261
- Interrupt Processing
  262
- Requirements for System Reset Generation
  262
- Interrupt Definitions
  264
- Critical Input Interrupt
  265
- Machine Check Interrupt
  266
- Core Complex Bus (CCB) and L1 Cache Machine Check Errors
  268
- Cache Parity Error Injection
  270
- Data Storage Interrupt
  271
- Instruction Storage Interrupt
  272
- External Input Interrupt
  273
- Alignment Interrupt
  274
- Program Interrupt
  276
- Decrementer Interrupt
  277
- System Call Interrupt
  277
- Fixed-Interval Timer Interrupt
  278
- Data TLB Error Interrupt
  279
- Watchdog Timer Interrupt
  279
- Instruction TLB Error Interrupt
  281
- Debug Interrupt
  282
- EIS-Defined Interrupts
  283
- Spe/Embedded Floating-Point APU Unavailable Interrupt
  283
- Embedded Floating-Point Data Interrupt
  284
- Embedded Floating-Point Round Interrupt
  284
- Partially Executed Instructions
  285
- Performance Monitor Interrupt
  285
- Interrupt Ordering and Masking
  287
- Guidelines for System Software
  288
- Exception Priorities
  289
- Interrupt Order
  289
- E500 Exception Priorities
  291
- E500 Interrupt Latency
  291
Mbar Instruction Timing Considerations

219
- Memory Synchronization Timing Considerations
  219
Guarded Load and Cache-Inhibited Stwcx. Instructions

292
Chapter 6 Power Management

293
- Overview
  293
- Power Management Signals
  293
- Core and Integrated Device Power Management States
  294
- Core Power Management State Diagram
  294
- Power Management Control Bits
  295
- Software Considerations for Power Management
  296
- Power Management Protocol
  297
- Interrupts and Power Management
  298
Chapter 7 Performance Monitor

299
- Overview
  299
- Performance Monitor APU Registers
  300
- Global Control Register 0 (PMGC0)
  302
  - User Performance Monitor Global Control Register 0 (UPMGC0)
    302
- User Global Control Register 0 (UPMGC0)
  303
- Local Control a Registers (Pmlca0-Pmlca3)
  303
- User Local Control a Registers (Upmlca0-Upmlca3)
  304
- Local Control B Registers (Pmlcb0-Pmlcb3)
  304
- User Local Control B Registers (Upmlcb0-Upmlcb3)
  305
- Performance Monitor Counter Registers (PMC0-PMC3)
  306
- User Performance Monitor Counter Registers (UPMC0-UPMC3)
  307
- Performance Monitor APU Instructions
  307
- Performance Monitor Interrupt
  308
- Event Counting
  308
- Processor Context Configurability
  308
- Examples
  309
- Chaining Counters
  309
- Thresholding
  310
- Event Selection
  310
Chapter 8 Debug Support

317
- Overview
  317
- Programming Model
  317
- Register Set
  317
- Instruction Set
  318
- Debug Interrupt Model
  318
- Deviations from the Book E Debug Model
  319
- Hardware Facilities
  320
- TAP Controller and Register Model
  320
- TAP Interface Signals
  321
- Book E Debug Events
  322
- Instruction Address Compare Debug Event
  323
- Instruction Address Compare User and Supervisor Modes
  323
- Effective Address Mode
  324
- Instruction Address Compare Mode
  324
- Data Address Compare Debug Event
  325
- Data Address Compare Read/Write Enable
  325
- Data Address Compare User/Supervisor Mode
  326
- Effective Address Mode
  326
- Data Address Compare (DAC) Mode
  326
- Trap Debug Event
  327
- Branch Taken Debug Event
  328
- Instruction Complete Debug Event
  328
- Interrupt Taken Debug Event
  329
- Return Debug Event
  329
- Unconditional Debug Event
  330
E500 Core Complex

331
Chapter 9 Timer Facilities

333
- Timer Registers
  334
- The E500 Timer Implementation
  335
- Alternate Time Base APU
  336
- Performance Monitor Time Base Event
  336
Chapter 10 Auxiliary Processing Units (Apus)

337
- Overview
  337
- Branch Target Buffer (BTB) Locking APU
  338
- BTB Locking APU Programming Model
  338
- BTB Locking APU Instructions
  338
- Vector and Floating-Point Apus
  338
- BTB Locking APU Registers
  339
- Alternate Time Base APU
  339
- Programming Model
  339
- Double-Precision Floating-Point APU (E500 V2 Only)
  340
- Programming Model
  340
- Double-Precision Floating-Point APU Operations
  340
- Operational Modes
  340
- Floating-Point Data Formats
  341
- Overflow and Underflow
  342
- Instruction Descriptions
  342
- Embedded Floating-Point Results Summary
  358
- Floating-Point Conversion Models
  358
- Common Functions
  358
- Convert from Double-Precision Floating-Point to Integer Word with Saturation
  359
- Convert to Double-Precision Floating-Point from Integer Word with Saturation
  361
Chapter 11

363
- Overview
  363
- Block Diagram
  365
- Load/Store Unit (LSU)
  365
- Caching-Allowed Loads and the LSU
  366
- Store Queue
  366
- L1 Load Miss Queue (LMQ)
  366
- Data Line Fill Buffer (DLFB)
  366
- Data Write Buffer (DWB)
  367
- Instruction Unit
  367
- Core Interface Unit
  367
- L1 Cache Organization
  368
- L1 Data Cache Organization
  368
- L1 Instruction Cache Organization
  369
- L1 Cache Parity
  370
- Cache Parity Error Injection
  371
- Cache Coherency Support
  371
- Data Cache Coherency Model
  371
- Instruction Cache Coherency Model
  373
- Snoop Signaling
  374
- WIMGE Settings and Effect on L1 Caches
  375
- Write-Back Stores
  375
- Write-Through Stores
  375
- Caching-Inhibited Loads and Stores
  375
- Misaligned Accesses and the Endian (E) Bit
  375
- Speculative Accesses to Guarded Memory
  375
- Load/Store Operations
  376
- Performed Loads and Stores
  376
- Sequential Consistency of Memory Accesses
  377
- Enforcing Store Ordering with Respect to Loads
  377
- Atomic Memory References
  377
- L1 Cache Control
  378
- Cache Control Instructions
  378
- L1 Instruction and Data Cache Enabling/Disabling
  380
- L1 Instruction and Data Cache Flash Invalidation
  380
- L1 Instruction and Data Cache Line Locking/Unlocking
  381
- Effects of Other Cache Instructions on Locked Lines
  383
- Flash Clearing of Lock Bits
  383
- L1 Data Cache Flushing
  384
- L1 Cache Operation
  384
- Cache Miss and Reload Operations
  385
- Data Cache Fills
  385
- Instruction Cache Fills
  385
- Cache Allocation on Misses
  386
- Store Miss Merging
  386
- Store Hit to a Data Cache Block Marked Shared
  386
- Data Cache Block Push Operation
  386
- L1 Cache Block Replacement
  387
- PLRU Replacement
  387
- PLRU Bit Updates
  388
- Cache Locking and PLRU
  389
- L2 Cache Support
  389
- Invalidating the L2 Cache after a Cache Tag Parity Error
  389
- L2 Locking
  389
- L2 Unlocking
  390
- L1 Overlock
  390
Chapter 12 Memory Management Units

391
- E500 MMU Overview
  391
- MMU Features
  391
- TLB Entry Maintenance Features
  393
- Effective-To-Real Address Translation
  394
- Virtual Addresses with Three PID Registers
  395
- Variable-Sized
  396
- Checking for TLB Entry Hit
  397
- Checking for Access Permissions
  397
- Translation Lookaside Buffers (Tlbs)
  398
- L1 TLB Arrays
  399
- L1 MMU TLB Organization
  400
- L2 TLB Arrays
  401
- IPROT Invalidation Protection in TLB1
  402
- Replacement Algorithms for L2 MMU
  403
- Round-Robin Replacement for TLB0-E500V1
  404
- Round Robin Replacement for TLB0-E500V1
  404
- Round-Robin Replacement for TLB0-E500V2
  404
- Round Robin Replacement for TLB0-E500V2
  404
- Consistency between L1 and L2 Tlbs
  405
- L1 and L2 TLB Access Times
  406
- The G Bit (of WIMGE)
  406
- TLB Entry Field Definitions
  407
- TLB Instructions-Implementation
  407
TLB Read Entry (Tlbre) Instruction

408
- Reading Entries from the TLB1 Array
  408
- Reading Entries from the TLB0 Array
  408
TLB Write Entry (Tlbwe) Instruction

409
- Writing to the TLB1 Array
  409
- Writing to the TLB0 Array
  409
TLB Search (Tlbsx) Instruction-Searching the TLB1 and TLB0 Arrays

409
TLB Invalidate (Tlbivax) Instruction

410
TLB Selection for Tlbivax Instruction

411
Invalidate All Address Encoding for Tlbivax Instruction

412
- TLB Invalidate Broadcast Enabling
  412
TLB Synchronize (Tlbsync) Instruction

412
- TLB Entry Maintenance-Details
  412
- Automatic Updates-TLB Miss Exceptions
  413
- TLB Interrupt Routines
  414
- Permissions Violations (ISI, DSI) Interrupt Handlers
  414
- TLB States after Reset
  414
- Core Complex MMU Registers
  415
- E500 MAS Registers
  416
- MAS Register 1 (MAS1)
  417
- MAS Register 2 (MAS2)
  418
- MAS Register 3 (MAS3)
  419
- MAS Register 4 (MAS4)
  420
- MAS Register 7 (MAS7)
  421
- MAS Register Updates
  422
Chapter 13 Core Complex Bus (CCB)

423
- Overview
  423
- Signal Summary
  424
- Core Interface Behavior
  427
- Parity Specification
  427
Msync Operation and the Bus

428
Mbar Operation and the Bus

428
- Address Streaming Mode
  429
- L2 Cache Support
  429
- L2 Locking
  429
- L2 Unlocking
  430
- L1 Overlock
  430
- Reservation Management
  430
- Remote Atomic Status Monitoring
  431
- Proper Reporting of Bus Faults
  431
Appendix A Programming Examples

433
- Synchronization
  433
- A.1 Synchronization
  433
- Synchronization Primitives
  434
- Fetch and No-Op
  434
- A.1.1 Synchronization Primitives
  434
- Fetch and Store
  435
- Fetch and and
  435
- Notes
  436
- A.1.1.5 Test and Set
  436
- Lock Acquisition and Release
  437
- List Insertion
  438
- A.1.3 List Insertion
  438
- Notes
  439
- A.1.3.1 Notes
  439
Appendix B Guidelines for 32-Bit Book E

441
Appendix C Simplified Mnemonics for Powerpc Instructions

445
- Overview
  445
- C.1 Overview
  445
- Subtract Simplified Mnemonics
  446
- Subtract Immediate
  446
- Subtract
  446
- Rotate and Shift Simplified Mnemonics
  446
- Operations on Words
  447
- C.3.1 Operations on Words
  447
- Branch Instruction Simplified Mnemonics
  448
- Key Facts about Simplified Branch Mnemonics
  449
- Eliminating the BO Operand
  449
- C-2 BO Field (Bits 6–10 of the Instruction Encoding)
  450
- Incorporating the BO Branch Prediction
  451
- The BI Operand-CR Bit and Field Representations
  452
- BI Operand Instruction Encoding
  452
- Specifying a CR Bit
  453
- BO Field (Bits 6-10 of the Instruction Encoding
  453
- C.4.4.1.1 Specifying a CR Bit
  453
- The Crs Operand
  454
- Simplified Mnemonics that Incorporate the BO Operand
  455
- Examples that Eliminate the BO Operand
  456
Simplified Mnemonics that Incorporate CR Conditions (Eliminates BO and Replaces BI with Crs

459
No-Op (Nop

468
Load Immediate (Li

468
Load Address (la

468
Move Register (Mr

469
Complement Register (Not

469
Move to Condition Register (Mtcr

469
- EIS-Specific Simplified Mnemonics
  470
Integer Select (Isel

470
- SPE Mnemonics
  470
Appendix D Opcode Listings

481
Appendix E Revision History

531
- Major Changes from Revision 0 to Revision 1
  531
Chapter 3 Instruction Model

532
Chapter 4 Execution Timing

536
Chapter 5 Interrupts and Exceptions

547
- Power Management
  548

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Freescale Semiconductor PowerPC e500 Core Manuals

Freescale Semiconductor PowerPC e500 Core Reference Manual (548 pages)

Table of Contents

Paragraph Page

Number Title Number

Figure Page

Number Title Number

Chapter 1 Core Complex Overview

Chapter 2 Register Model

Synchronization with Tlbwe and Tlbivax Instructions

Number

Using Msync and Mbar to Order Memory Accesses

Export Shared Memory and Release Lock Using Mbar (MO = 0)

Integer Select (Isel) APU

Msync Instruction Timing Considerations

Mbar Instruction Timing Considerations

Guarded Load and Cache-Inhibited Stwcx. Instructions

Chapter 6 Power Management

Chapter 7 Performance Monitor

Chapter 8 Debug Support

E500 Core Complex

Chapter 9 Timer Facilities

Chapter 10 Auxiliary Processing Units (Apus)

Chapter 11

Chapter 12 Memory Management Units

TLB Read Entry (Tlbre) Instruction

TLB Write Entry (Tlbwe) Instruction

TLB Search (Tlbsx) Instruction-Searching the TLB1 and TLB0 Arrays

TLB Invalidate (Tlbivax) Instruction

TLB Selection for Tlbivax Instruction

Invalidate All Address Encoding for Tlbivax Instruction

TLB Synchronize (Tlbsync) Instruction

Chapter 13 Core Complex Bus (CCB)

Msync Operation and the Bus

Mbar Operation and the Bus

Appendix A Programming Examples

Appendix B Guidelines for 32-Bit Book E

Appendix C Simplified Mnemonics for Powerpc Instructions

Simplified Mnemonics that Incorporate CR Conditions (Eliminates BO and Replaces BI with Crs

No-Op (Nop

Load Immediate (Li

Load Address (la

Move Register (Mr

Complement Register (Not

Move to Condition Register (Mtcr

Integer Select (Isel

Appendix D Opcode Listings

Appendix E Revision History

Chapter 3 Instruction Model

Chapter 4 Execution Timing

Chapter 5 Interrupts and Exceptions

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