Toshiba H1 Series Data Book page 530

1. LVSYNC Signal
The period of the vertical synchronization signal LVSYNC indicates the time for each
screen update (refresh rate). The LVSYNC period is defined as an integral multiple of
the period of the horizontal synchronization signal LHSYNC.
The LVSYNC period is calculated as the product of the value set in LCDVSP<LV 9:0>
and the LHSYNC period. The value to be set in LCDVSP<LV9:0> should be "common
size + number of dummy clocks" or larger for TFT and STN.
LVSYNC [s: period]
LCDVSP
bit Symbol
(028CH)
Read/Write
After reset
Function
(028DH)
bit Symbol
Read/Write
After reset
Function
The enable width of the LVSYNC signal can be specified as 1 clock, 2 clocks, or 3
clocks of LHSYNC in LCDCTL1<LVSW1:0>.
The phase of the LVSYNC signal can be inverted by the setting of LCDCTL1
<LVSP>.
LVSP=0
LVSP=1
bit Symbol
LCDCTL1
Read/Write
(0286H)
After reset
Function
= LHSYNC [s: period] × (<LVP9:0> + 1)
= LCP0 [s: period] × (<LH15:0> + 1) × (<LVP9:0> + 1)
LCD V SYNC Pulse Register
7 6 5
LVP7 LVP6 LVP5
0 0 0
7 6 5
(Enable width control)
LCD Control 1 Register
7 6
LCP0P LHSP
R/W R/W
1 0
LCP0 LHSYNC LVSYNC
phase phase phase
0: Rising 0: Rising 0: Rising
1: Falling 1: Falling 1: Falling
92CZ26A-527
4 3
LVP4 LVP3
W
0 0
LVSYNC period (bits 7-0)
4 3
Refresh rate
(Phase control)
LVSYNC signal
5 4 3
LVSP LLDP
R/W R/W
1 0
LLOAD
phase
0: Rising
1: Falling
TMP92CZ26A
2 1 0
LVP2 LVP1 LVP0
0 0 0
2 1 0
LVP9 LVP8
W
0 0
LVSYNC period
(bits 9-8)
2 1
LVSW1
R/W
0
LVSYNC
enable time control
00 : 1 clock of LHSYNC
01 : 2 clocks of LHSYNC
10 : 3 clocks of LHSYNC
11 : Reserved
0
LVSW0
R/W
0