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Stage change condition of control write (no data stage) transfer type
SETUP DATA0 ACK
INT_SETUP
INT_ ENDPOINT0
INT_STATUS
REQUEST FLAG
DATASET register
BRD
BWR
bmRequestType register
bRequest register
wValue register
wINdex register
wLength register
Figure 3.16.12 The Control Flow in UDC (Control Write Transfer Type not Dataphase)
1.
Receive SETUP token from host
•
Start setup stage in UDC.
•
Receive data in request normally and judge. And assert INT_SETUP
interrupt to external.
•
Change data stage in UDC.
2.
Receive IN token from host
•
CPU receive request from request register every INT_SETUP
interrupt.
•
Judge request and access Setup Received register for inform that
recognized INT_SETUP interrupt to UDC.
•
CPU process receiving data by device request.
•
When CPU finish transaction, it writes "0" to EP0 bit of EOP register.
•
Change status stage in UDC.
•
Return data packet of 0 data to IN token, and state change to IDLE in
UDC.
•
Assert INT_STATUS interrupt to external when receive ACK for 0
data packet.
These change condition is Figure 3.16.12.
IN
NAK
Setup Received register
92CZ26A-435
IN
DATA1
ACK
EOP register
TMP92CZ26A
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