Casio UP-360 Service Manual page 15

Function of HD64F7045
SH7040 Product Overview [HD6437040], [HD6417040]
SH7041 Product Overview [HD6437041], [HD6417041]
SH7042 Product Overview [HD6437042], [HD6477042]
SH7043 Product Overview [HD6437043], [HD6477043]
SH7044 Product Overview [HD64F7044], [HD6437044]
SH7045 Product Overview [HD64F7045], [HD6437045]
CPU:
Original Renesas architecture
32-bit internal data bus
General-register machine
• Sixteen 32-bit general registers
• Three 32-bit control registers
• Four 32-bit system registers
RISC-type instruction set
• Instruction length: 16-bit fixed length for improved code efficiency
• Load-store architecture (basic operations are executed between registers)
• Delayed branch instructions reduce pipeline disruption during branch
• Instruction set based on C language
Instruction execution time: one instruction/cycle (35 ns/instruction at 28.7-MHz operation)
Address space: Architecture supports 4 G bytes
On-chip multiplier: multiplication operations (32 bits x 32 bits 64 bits) and multiplication/accumulation operations
(32 bits x 32 bits + 64 bits 64 bits) executed in two to four cycles
Five-stage pipeline
Cache Memory:
1-kbyte instruction cache
Caching of instruction codes and PC relative read data
4-byte line length (1 longword: 2 instruction lengths)
256 entry cache tags
Direct map method
On-chip ROM/RAM, and on-chip I/O areas not objects of cache
Used in common with on-chip RAM; 2 k bytes of on-chip RAM used as address array/data array
when cache is enabled
Interrupt Controller (INTC):
Nine external interrupt pins (NMI, IRQ0-IRQ7)
Forty-three internal interrupt sources (forty-four for A mask)
Sixteen programmable priority levels
User Break Controller (UBC):
Generates an interrupt when the CPU or DMAC generates a bus cycle with specified conditions
Simplifies configuration of an on-chip debugger
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