Casio QT-2100 Service Manual page 28

5-7. LCD CONTROLLER (IC4)
5-7-1. BLOCK DIAGRAM
I/O
CONTROLLER
(IC11)
78 K IV
12.5 MHz
5-7-2. Pin description
PIN NO NAME I/O
1 DB7 I/O System data bus
2 Vss
3 Vdd
4 DB8 I/O Connected to Vdd
5 DB9 I/O Connected to Vdd
6 DB10 I/O Connected to Vdd
7 DB11 I/O Connected to Vdd
8 DB12 I/O Connected to Vdd
9 DB13 I/O Connected to Vdd
10 DB14 I/O Connected to Vdd
11 DB15 I/O Connected to Vdd
12 AB0
13 AB1
14 AB2
15 AB3
16 AB4
17 AB5
18 AB6
19 AB7
20 AB8
21 AB9
22 AB10
23 AB11
24 AB12
25 AB13
26 AB14
27 AB15
28 AB16
29 AB17
30 AB18
31 AB19
32 RESET
33 VA0
34 VA1
35 VA2
36 VA3
37 VA4
38 VA5
39 VA6
40 VA7
41 VA8
42 VA9
43 VA10
44 VD0 I/O Display memory data bus
45 VD1 I/O Display memory data bus
46 VD2 I/O Display memory data bus
47 VD3 I/O Display memory data bus
48 VD4 I/O Display memory data bus
49 VD5 I/O Display memory data bus
50 VD6 I/O Display memory data bus
A0-A15
IOCS
DECODER MEMCS
LCD
D0-D7
CONTROLLER
RD
(IC4)
WR
WAIT
MPUCLK (12.5 MHz)
VRAM
BUS
Display memory
(IC1)
256 Kbit
DESCRIPTION
GND
Vcc
I System address bus
I System address bus
I System address bus
I System address bus
I System address bus
I System address bus
I System address bus
I System address bus
I System address bus
I System address bus
I System address bus
I System address bus
I System address bus
I System address bus
I System address bus
I Connected to GND
I Connected to GND
I Connected to GND
I Connected to GND
I Connected to GND
I Reset signal
O Display memory address bus
O Display memory address bus
O Display memory address bus
O Display memory address bus
O Display memory address bus
O Display memory address bus
O Display memory address bus
O Display memory address bus
O Display memory address bus
O Display memory address bus
O Display memory address bus
— 26 —
MCLK (LCD BUS CLOCK)
D0-D3
MCLK
6.00 Mhz
PIN NO NAME I/O
51 VD7 I/O Display memory data bus
52 Vss GND
53 Vdd Vcc
54 VD8 I/O Not used
55 VD9 I/O Not used
56 VD10 I/O Not used
57 VD11 I/O Not used
58 VD12 I/O Not used
59 VD13 I/O Not used
60 VD14 I/O Not used
61 VD15 I/O Not used
62 VA11 O Display memory address bus
63 VA12 O Display memory address bus
64 VA13 O Display memory address bus
65 O Display memory address bus
66 VA15 O Display memory address bus
67 VWE O Write signal for display memory
68 VCS0 O Select display memory
69 VCS1 O Not used
70 UD3 O Panel display data bus
71 UD2 O Panel display data bus
72 UD1 O Panel display data bus
73 UD0 O Panel display data bus
74 LD3 O Not used
75 LD2 O Not used
76 LD1 O Not used
77 LD0 O Not used
78 YD O Vertical scanning start pulse
79 LP O Display data latch clock
80 WF O Not used
81 XSCL O Display data shift clock
82 LCDENB O LCD enable signal output
83 VOE O Read signal for display memory
84 IOCS I Select internal registers
85 IOW I Write signal for internal register
86 IOR I Read signal for internal register
87 MEMCS I Indicate a memory cycle
88 MEMW I Indicate a memory write cycle
89 MEMR I Indicate a memory read cycle
90 READY O Ready signal
91 BHE I Vcc
92 OSC1 I Clock signal
93 OSC2 O Clock signal
94 DB0 I/O System data bus
95 DB1 I/O System data bus
96 DB2 I/O System data bus
97 DB3 I/O System data bus
98 DB4 I/O System data bus
99 DB5 I/O System data bus
100 DB6 I/O System data bus
LCD
DESCRIPTION