Input Power Connector P7 Pin Assignments; P8 Expansion Connector Pin Assignments - Motorola MPC505EVB User Manual

Table 4-7. Input Power Connector P7 Pin Assignments
Pin Mnemonic
1 VCC
2 GND
3 GND
Table 4-8. P8 Expansion Connector Pin Assignments
Pin Mnemonic
A-1, A-2 V3.3
A-3 AACK*
A-4 TS*
A-5 VDDSYN
A-6 A-8 IRQ6*
IRQ4*
A-9 A-12 CT0 CT3
A-13 GND
A-14 A-16 VF0 VF2
A-17 R_W*
A-18 TA*
A-19 TEA*
A-20 AT1
MPC505EVBUM/D
+5 VDC POWER – Input voltage (+5 Vdc @ 2.0 A) used by the EVB
logic circuits. The "VCC" write on the board nere the coresponding pin.
GROUND The "GND" write on the board nere the coresponding pin
GROUND The "GND" write on the board nere the coresponding pin
+3.3 VDC POWER – Voltage generated by the on-board voltage
converter for use by the MPC505 MCU logic circuits.
ADDRESS ACKNOWLEDGE – An active-low input signal that indicates
the slave has received the address from the bus master.
TRANSFER START – An active-low output signal that indicates the
start of a bus cycle.
VDDSYN – Clock synthesizer power.
–
INTERRUPT REQUEST (6 -4) – Prioritized active low input lines that
requests MCU synchronous interrupts. IRQ1* has the highest priority.
CYCLE TYPE SIGNALS – Four bits that indicate what type of bus cycle
the bus master is initiating.
GROUND
VISIBILITY FETCH – Instruction queue status bits that indicate the last
fetched instruction or the number of instructions flushed from the
instruction queue.
READ/WRITE – Active-high output signal that indicates the direction of
data transfer on the bus.
TRANSFER ACKNOWLEDGE – An active-low input signal that
indicates the slave has received data during a write cycle or returned
data during a read cycle.
TRANSFER ERROR ACKNOWLEDGE – An active-low input signal that
indicates bus error condition.
ADDRESS TYPES bit 1 – One of two output bits that defines address
space as: user data, user instruction, supervisor data, or supervisor
instruction.
SUPPORT INFORMATION
Signal
Signal
4-9