External Bus Interface; Chip Selects; System Clock; Test Module - Motorola MPC505EVB User Manual

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3.3.5

External Bus Interface

The external bus consists of 24 address lines and a 16-bit data bus. The data bus allows dynamic
sizing between 8- and 16-bit data accesses. A read-modify-write cycle (RMC) signal prevents
bus cycle interruption. External bus arbitration is accomplished by a three-line handshaking
interface.
3.3.6

Chip Selects

Twelve independently programmable chip selects provide fast, two-cycle external memory, or
peripheral access. Block size is programmable from 2 kilobytes through 1 megabyte. Accesses
can be selected for either 8- or 16-bit transfers. As many as 13 wait states can be programmed for
insertion during the access. All bus interface signals are automatically handled by the chip select
logic.
3.3.7

System Clock

An on-chip phase locked loop circuit generates the system clock signal to run the device up to
16.78 MHz from a 32.768 kHz watch crystal. The system speed can be changed dynamically,
providing either high performance or low power consumption under software control. The
system clock is a fully-static CMOS design, so it is possible to completely stop the system clock
via a low power stop instruction, while still retaining the contents of the registers and on-board
RAM.
3.3.8

Test Module

The test module consolidates the microcontroller test logic into a single block to facilitate
production testing, user self-test, and system diagnostics. Scan paths throughout the MC68332
provide signature analysis checks on internal logic. User self-test is initiated by asserting the test
pin to enter test mode. This test provides a pass/fail response to various externally supplied test
vectors.
3.4

USER MEMORY

On board the BCC is 32k x 16 bits of RAM and 64k x 16 bits of EPROM. The RAM is the
debug monitor storage area and user accessible memory space; the M68MPCBUG Debug
Monitor is stored in the BCC EPROMs. For debug monitor functionality see the M68MPCBUG
Debug Monitor User's Manual, M68MPCBUG /AD1. Figure 3-3 is the EVB memory map.
The PFB has sockets for 32k x 16 or 64k x 16 bit RAM or 64k x 16 bit EPROM. The RAM
and/or EPROM, supplied by the user, is user-accessible memory space.
MPC505EVBUM/D
FUNCTIONAL DESCRIPTION
3-5

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