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HARDWARE PREPARATION AND INSTALLATION
2.3.10.2
Reset Data Dip Switches (DS2 – DS5)
Dip switches DS2 – DS5 are connected through 4 buffers on the MPC505 MCU data bus (D31 –
D0). At RESET the MCU reads the data bus and changes its configuration according to these
switches ("ON" = 0 LOGIC).
There are two reset configuration modes: data bus configuration mode (pertinent to the EVB) or
internal default mode. In either mode the configuration is set by the MCU driving a configuration
word onto the internal data bus. Table 2-7 describes the configuration options. The EVB Default
Mode column shows the default reset configuration word. The default reset data bus
configuration word is X9E5EF4A3. For information on the internal reset configuration mode
refer to the PowerPC MPC505 RISC Microcontroller Technical Summary, MPC505TS/D.
Data
Configuration
Bus
Function
Bit
Effected
0
Address Bus
1
Vector Table Location
(IP Bit)
2
Burst Type/Indication
3
Interface Type for
CSBOOT
4
CSBOOT Port Size
5
Reset Configuration
Source For DATA[6:13]
[6:8]
TA Delay For CSBOOT
2-12
Table 2-7. Data Bus Reset Configuration Word
Effect of
Mode Select = 1
During Reset
Minimum Bus Mode
ADDR[0:11] = CS[0:11]
Vector Table
0xFFF0 0000
Type 2/LAST
ITYPE = 001
Asynchronous (Time to
Hi-Z = 2Clk)
32-Bit
Latch Configuration from
external pins.
TA Delay Encoding
000
001
010
011
100
101
110
111
Effect of
Mode Select = 0
During Reset
Maximum Bus Mode
ADDR[0:11] = Address Pins
Vector Table
0x0000 0000
Type 1/BDIP
ITYPE = 1000
Synchronous Burst
16-Bit
Latch Configuration from
internal defaults.
# of Wait States
0
1
2
3
4
5
6
7
MPC505EVBUM/D
EVB
Default
Mode
1
0
0
1
1
1
100
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