6.9.8 Host Terminating Write DMA
Table 32: Ultra DMA cycle timing chart (Host Terminating Write)
DMARQ
DMACK-
STOP
DDMARDY-
HSTROBE
DD(15:0)
Table 33: Ultra DMA cycle timings (Host Terminating Write)
PARAMETER
DESCRIPTION
(all values in ns)
tSS
Time from HSTROBE edge
to assertion of STOP
tLI
Limited interlock time
tMLI Interlock time with mini-
mum
tCS
CRC word setup time at
device
tCH
CRC word hold time at
device
tACK Hold time for DMACK-
tIO-
Maximum time before
RDYZ
releasing IORDY
tLI
tSS
tLI
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
MODE 0
MODE 1
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
50
–
50
–
0
150
0
150
20
–
20
–
15
–
10
–
5
–
5
–
20
–
20
–
–
20
–
20
Deskstar 7K160 Hard Disk Drive Specification
tMLI
tIORDYZ
tLI
Host drives DD
MODE 2
MODE 3
50
–
50
–
0
150
0
100
20
–
20
–
7
–
7
–
5
–
5
–
20
–
20
–
–
20
–
20
39
tACK
tACK
tCH
tCS
CRC
xxxxxxxxxx
MODE 4
MODE 5
50
–
50
–
0
100
0
75
20
–
20
–
5
–
5
–
5
–
5
–
20
–
20
–
–
20
–
20
MODE 6
50
–
0
60
20
–
5
–
5
–
20
–
–
20