6.10.8 Host Terminating Write DMA
Table 32: Ultra DMA cycle timing chart (Host Terminating Write)
DMARQ
DMACK-
STOP
DDMARDY-
HSTROBE
DD(15:0)
Table 33: Ultra DMA cycle timings (Host Terminating Write)
PARAMETER
DESCRIPTION
(all values in ns)
tSS
Time from HSTROBE edge to
assertion of STOP
tLI
Limited interlock time
tMLI
Interlock time with minimum
tCS
CRC word setup time at device
tCH
CRC word hold time at device
tACK
Hold time for DMACK-
tIORDYZ
Maximum time before releasing
IORDY
tLI
tSS
tLI
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
MODE 0
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
50
–
0
150
20
–
15
–
5
–
20
–
–
20
Deskstar T7K250 Hard Disk Drive Specification
tMLI
tIORDYZ
tLI
Host drives DD
MODE 1
MODE 2
50
–
50
–
0
150
0
150
20
–
20
–
10
–
7
–
5
–
5
–
20
–
20
–
–
20
–
20
42
tACK
tACK
tCH
tCS
CRC
xxxxxxxxxx
MODE 3
MODE 4
50
–
50
–
0
100
0
100
20
–
20
–
7
–
5
–
5
–
5
–
20
–
20
–
–
20
–
20
MODE 5
50
–
0
75
20
–
5
–
5
–
20
–
–
20