Multi-Word Dma Timings; Table 18: Multiword Dma Cycle Timing Chart; Table 19: Multiword Dma Cycle Timings - Hitachi HTS542525K9SA00 Specifications

• In the event that a host reads the status register only before the sector or block transfer DRQ interval, the
DRQ interval 4.2 µs
• In the event that a host reads the status register after or both before and after the sector or block transfer,
the DRQ interval is 11.5 µs

6.8 Multi-word DMA timings

The Multiword DMA timings meet Mode 2 of the ATA/ATAPI-6 description.

Table 18: Multiword DMA cycle timing chart

CS0-/CS1-
DMARQ
DMACK-
DIOR-/DIOW-
READ DATA
WRITE DATA

Table 19: Multiword DMA cycle timings

PARAMETER DESCRIPTION
t0 Cycle time
tD DIOR-/DIOW- asserted pulse width
tE DIOR- data access
tF DIOR- data hold
tG DIOR-/DIOW- data setup
tH DIOW- data hold
tI DMACK- to -DIOR-/DIOW- setup
tJ DIOR-/DIOW- to DMACK- hold
tKR/tKW DIOR-/DIOW- negated pulse width
tLR/tLW DIOR-/DIOW- to DMARQ- delay
tM CS (1:0) valid to DIOR-/DIOW-
tN CS (1:0)
tZ DMACK- to read data released
tM
t0
tI tD
tG
tE
tG
Deskstar 7K160 Hard Disk Drive Specification
31
tLR/tLW
tKR/tKW
tF
tH
MIN (ns)
120
70
20
10
25
25
10
tN
tJ
tZ
MAX (ns)
–
–
– 50
5 –
–
–
0 –
5 –
–
– 35
-
-
– 25