Device Control Register; Drive Address Register; Table 40. Device Control Register; Table 41. Drive Address Register - Hitachi 7K100 - Travelstar - Hard Drive Specifications

10.4 Device Control Register

Table 40: Device Control Register
7 6
HOB -
Bit Definitions
HOB HOB (high order byte) is defined by the 48-bit Address feature set. A write to any Command
Register shall clear the HOB bit to zero.
SRST (RST) Software Reset. The device is held at reset when RST = 1. Setting RST = 0 again enables the
device. To ensure that the device recognizes the reset, the host must set RST = 1 and wait for at
least 5 ms before setting RST = 0.
-IEN Interrupt Enable. When IEN = 0, and the device is selected, the device interrupts to the host will
be enabled. When IEN = 1, or the device is not selected, the device interrupts to the host will be
disabled.

10.5 Drive Address Register

Table 41: Drive Address Register
7 6
HIZ -WTG -H3
This register contains the inverted drive select and head select addresses of the currently selected drive.
Bit Definitions
HIZ High Impedance. This bit is not a device and will always be in a high impedance state.
-WTG Write Gate. This bit is 0 when writing to the disk device is in progress.
-H3, -H2,- -Head Select. These four bits are the one's complement of the binary coded address of the cur-
H1,-H0- rently selected head. Bit -H0 is the least significant.
-DS1 -Drive Select 1. The Drive Select bit for device 1 is active low. DS1 = 0 when device 1 (slave) is
selected and active.
-DS0 -Drive Select 0. The Drive Select bit for device 0 is active low. DS0 = 0 when device 0 (master)
is selected and active.
5 4 3
- - 1
5 4 3
-H2 -H1
Travelstar 7K100 Hard Disk Drive Specification
2 1 0
SRST -IEN 0
2 1 0
-H0 -DS1 -DS0
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