Device Control Register; Device Register; Table 25: Device Control Register; Table 26: Device Register - Hitachi HTS541010G9AT00 - Travelstar 100 GB Hard Drive Specifications

This register contains the command code being sent to the device. Command execution begins immediately after
this register is written.
All other registers required for the command must be set up before writing the Command Register.

9.3 Device Control Register

Table 25: Device Control Register

7 6
- -
Bit Definitions
SRST (RST)
-IEN

9.4 Device Register

Table 26: Device Register

7 6
1 L
This register contains the device and head numbers.
Bit Definitions
L
DRV
HS3, HS2, HS1,
HS0
Device Control Register
5 4 3
- - 1
Software Reset. The device is held reset when RST=1. Setting
RST=0 re-enables the device.
The host must set RST=1 and wait for at least 5 microseconds
before setting RST=0, to ensure that the device recognizes the
resest.
Interrupt Enable. When IEN=0, and the device is selected, device
interurupts to the host will be enabled. When IEN=1, or the
device is not selected, device interrupts to the host will be
disabled.
Device Control Register
5 4 3
1 DRV HS3
Binary encoded address mode select. When L=0, addressing is by
CHS mode. When L=1, addressing is by LBA mode.
When DRV=0, device 0 (master) is selected. When DRV=1, device 1
(slave) is selected.
The HS3 through HSO contain bits 24-27 of the LBA. At command
completion, these bits are updated to reflect the current LBA
bits 24-27.
Travelstar 5K100 (Serial ATA) Hard Disk Drive Specification
2 1
SRST -IEN
2 1
HS2 HS1 HS0
46
0
0
0