Timing Of Setting Of Overflow Flag (Ovf); Timing Of Setting Of Watchdog Timer Reset Bit (Wrst) - Hitachi H8/3035 Series Hardware Manual

H'FF
TCNT
count value
H'00
IT
WT/ = 0
TME = 1

10.3.3 Timing of Setting of Overflow Flag (OVF)

Figure 10-6 shows the timing of setting of the OVF flag in TCSR. The OVF flag is set to 1 when
TCNT overflows. At the same time, a reset signal is generated in watchdog timer operation, or
an interval timer interrupt is generated in interval timer operation.
ø
TCNT
Overflow signal
OVF

10.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST)

The WRST bit in RSTCSR is valid when bits WT/
Figure 10-7 shows the timing of setting of WRST and the internal reset timing. The WRST bit is
set to 1 when TCNT overflows and OVF is set to 1. At the same time an internal reset signal is
generated for the entire H8/3035 Series chip. This internal reset signal clears OVF to 0, but the
WRST bit remains set to 1. The reset routine must therefore clear the WRST bit.
286
Interval Interval
timer timer
interrupt interrupt
Figure 10-5 Interval Timer Operation
H'FF H'00
Figure 10-6 Timing of Setting of OVF
Interval Interval
timer timer
interrupt interrupt
,7
and TME are both set to 1 in TCSR.
Time t
Interval
timer
interrupt