Instructions That Inhibit Interrupts; Interrupts During Eepmov Instruction Execution; Usage Notes - Hitachi H8/3035 Series Hardware Manual

5.5.3 Interrupts during EEPMOV Instruction Execution

The EEPMOV.B and EEPMOV.W instructions differ in their reaction to interrupt requests.
When the EEPMOV.B instruction is executing a transfer, no interrupts are accepted until the
transfer is completed, not even NMI.
When the EEPMOV.W instruction is executing a transfer, interrupt requests other than NMI are
not accepted until the transfer is completed. If NMI is requested, NMI exception handling starts
at a transfer cycle boundary. The PC value saved on the stack is the address of the next
instruction. Programs should be coded as follows to allow for NMI interrupts during
EEPMOV.W execution:
L1: EEPMOV.W
MOV.W R4,R4
BNE L1

5.5.4 Usage Notes

The IRQnF flag specification calls for the flag to be cleared by writing 0 to it after it has been
read while set to 1. However, it is possible for the IRQnF flag to be cleared by mistake simply
by writing 0 to it, irrespective of whether it has been read while set to 1, with the result that
interrupt exception handling is not executed. This will occur when the following conditions are
met.
1 Setting conditions
(1) Multiple external interrupts (IRQa, IRQb) are being used.
(2) Different clearing methods are being used: clearing by writing 0 for the IRQaF flag, and
clearing by hardware for the IRQbF flag.
(3) A bit-manipulation instruction is used on the IRQ status register for clearing the IRQaF
flag, or else ISR is read as a byte unit, the IRQaF flag bit is cleared, and the values read
in the other bits are written as a byte unit.
2 Generation conditions
(1) A read of the ISR register is executed to clear the IRQaF flag while it is set to 1, then
the IRQbF flag is cleared by the execution of interrupt exception handling.
(2) When the IRQaF flag is cleared, there is contention with IRQb generation (IRQaF flag
setting). (IRQbF was 0 when ISR was read to clear the IRQaF flag, but IRQbF is set to 1
before ISR is written to.)
If the above setting conditions (1) to (3) and generation conditions (1) and (3)are all
fulfilled, when the ISR write in generation condition (2) is performed the IRQbF flag will be
cleared inadvertently, and interrupt exception handling will not be executed.
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