Timing Of Setting The Overflow Flag (Ovf); Timing Of Setting The Watchdog Timer Overflow Flag (Wovf) - Hitachi SH7095 Hardware User Manual

12.3.4

Timing of Setting the Overflow Flag (OVF)

In the interval timer mode, when the WTCNT overflows, the OVF flag is set to 1 and an interval
timer interrupt is requested (figure 12.6).
12.3.5

Timing of Setting the Watchdog Timer Overflow Flag (WOVF)

When the WTCNT overflows the WOVF bit of the RSTCSR is set to 1 and a WDTOVF signal is
output. When the RSTE bit is set to 1, WTCNT overflow enables an internal reset signal to be
generated for the entire chip (figure 12.7).
Figure 12.7 Timing of Setting the WOVF Bit and Internal Reset
Figure 12.6 Timing of Setting the OVF
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