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24 a/D COnVeRTeR (aDC10)
2. Continuous conversion mode (aDMS = 1)
The A/D converter repeatedly performs A/D conversion for the channels in the range specified by ADCS[2:0]
and ADCE[2:0] until stopped with software.
At initial reset, the A/D converter is set to one-time conversion mode.
24.3.4
Trigger Selection
Select a trigger source to start A/D conversion from among the three types listed in Table 24.3.4.1 using ADTS[1:0]/
ADC10_TRG register.
1. external trigger (#aDTRG)
The signal input to the #ADTRG pin is used as a trigger. To use this trigger source, the I/O port pin must be
configured for the #ADTRG input using the port function select bit (see the "I/O Ports (P)" chapter). An A/D
conversion starts when a falling edge of the #ADTRG signal is detected.
note: When using an external trigger to start A/D conversion, ensure to maintain the Low period of the
trigger signal input to the #ADTRG pin for two or more S1C17 Core operating clock cycles.
2. 16-bit timer (T16) Ch.0
The underflow signal of T16 Ch.0 is used as a trigger. Since the T16 underflow cycle can be programmed with
flexibility, this trigger source is effective when periodic A/D conversions are required. For more information on
timer settings, see the "16-bit Timers (T16)" chapter.
3. Software trigger
Writing 1 to ADCTL/ADC10_CTL register with software serves as a trigger to start A/D conversion.
24.3.5
Sampling Time Setting
The analog signal input sampling time in this A/D converter can be configured to eight steps (two to nine A/D con-
version clock cycles) using ADST[2:0]/ADC10_TRG register.
The sampling time must satisfy the acquisition time condition (t
ure 24.3.5.1 shows an equivalent circuit of the analog input portion.
24-4
Table 24.
3.4.1 Trigger Selection
aDTS[1:0]
0x3
0x2
0x1
0x0
Table 24.
3.5.1 Sampling Time Settings
aDST[2:0]
(in a/D conversion clock cycles)
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Seiko epson Corporation
Trigger source
External trigger (#ADTRG)
Reserved
16-bit timer Ch.0
Software trigger
(Default: 0x0)
Sampling time
9 cycles
8 cycles
7 cycles
6 cycles
5 cycles
4 cycles
3 cycles
2 cycles
(Default: 0x7)
, time required for acquiring input voltage). Fig-
ACQ
S1C17624/604/622/602/621 TeChniCal Manual
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