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2
20 i
C MaSTeR (i2CM)
To return an ACK after data has been received, RTACK should be set to 0 before the I2CM module
sends the response bit. To return a NAK, set RTACK to 1.
D[7:0]
RTDT[7:0]: Receive/Transmit Data Bits
When transmitting data
Sets the transmit data. (Default: 0x0)
Data transmission is started by setting TXE to 1. If a slave address or data is currently being transmit-
ted, transmission begins once the previous transmission is completed. Serial converted data is output
from the SDA0 pin with MSB leading and bits set to 0 as Low level. A cause of transmit buffer empty
interrupt is generated as soon as the data written to this register is transferred to the shift register, after
which the subsequent transmission data can be written.
When receiving data
The received data can be read out. (Default: 0x0)
Data reception is started by setting RXE to 1. If a slave address is currently being transmitted or data
is currently being received, the new reception starts once the previous data has been transferred. The
RBRDY flag is set and a cause of receive buffer full interrupt generated as soon as reception is com-
pleted and the shift register data is transferred to this register. Data can then be read until the subsequent
data has been received. If the subsequent data is received before this register is read out, the contents
are overwritten by the most recent received data. Serial data input from the SDA0 pin with MSB lead-
ing is converted to parallel, with the High level bit set to 1 and the Low level bit set to 0, then loaded to
this register.
i
2
C Master interrupt Control Register (i2CM_iCTl)
Register name address
Bit
i
2
C Master
0x4346
D15–2 –
interrupt
(16 bits)
D1
Control Register
D0
(i2CM_iCTl)
D[15:2]
Reserved
D1
RinTe: Receive interrupt enable Bit
Enables or disables I2CM receive buffer full interrupts.
1 (R/W): Enabled
0 (R/W): Disabled (default)
Setting RINTE to 1 enables the output of I2CM interrupt requests to the ITC due to a receive data buf-
fer full. These interrupt requests are generated when the data received in the shift register is transferred
to RTDT[7:0]/I2CM_DAT register (when reception is completed).
I2CM interrupts are not generated by receive data buffer full if RINTE is set to 0.
D0
TinTe: Transmit interrupt enable Bit
Enables or disables I2CM transmit buffer empty interrupts.
1 (R/W): Enabled
0 (R/W): Disabled (default)
Setting TINTE to 1 enables the output of I2CM interrupt requests to the ITC due to a transmit buffer
empty. These interrupt requests are generated when the data written to RTDT[7:0] is transferred to the
shift register.
I2CM interrupts are not generated by transmit buffer empty if TINTE is set to 0.
20-10
name
Function
reserved
RinTe
Receive interrupt enable
TinTe
Transmit interrupt enable
Seiko epson Corporation
Setting
init. R/W
–
1 Enable
0 Disable
1 Enable
0 Disable
S1C17624/604/622/602/621 TeChniCal Manual
Remarks
–
–
0 when being read.
0
R/W
0
R/W
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