Epson S1C17624 Technical Manual page 119

TFMD[3:0]
1 2
0x0 – –
0x1 – –
0x2 – –
0x3 – –
0x4 – –
0x5 – –
0x6 – –
0x7 – –
0x8 – D
0x9 – D
0xa – D
0xb – D
0xc – D
0xd – D
0xe – D
0xf – D
Underflow signal (not corrected)
Underflow signal (corrected)
Output clock (not corrected)
Output clock (corrected)
At initial reset, TFMD[3:0] is set to 0x0, preventing insertion of delay cycles.
10.9 T8F interrupts
Each channel of the T8F module outputs an interrupt request to the interrupt controller (ITC) when the counter un-
derflows.
underflow interrupt
When the counter underflows, the interrupt flag T8FIF/T8F_INTx register, which is provided for each channel
in the T8F module, is set to 1. At the same time, an interrupt request is sent to the ITC if T8FIE/T8F_INTx reg-
ister has been set to 1 (interrupt enabled). An interrupt is generated if the ITC and S1C17 Core interrupt condi-
tions are satisfied.
If T8FIE is set to 0 (interrupt disabled, default), no interrupt request will be sent to the ITC.
For specific information on interrupt processing, see the "Interrupt Controller (ITC)" chapter.
notes: • The T8F module interrupt flag T8FIF must be reset in the interrupt handler routine after a T8F
interrupt has occurred to prevent recurring interrupts.
• Reset T8FIF before enabling T8F interrupts with T8FIE to prevent occurrence of unwanted in-
terrupt. T8FIF is reset by writing 1.
S1C17624/604/622/602/621 TeChniCal Manual
Table 10. 8.1 Delay Patterns Specified by TFMD[3:0]
3 4 5 6
– – – –
– – – –
– – – –
– – – –
– D – –
– D – –
– D – D
– D – D
– D – D
– D – D
– D – D
– D – D
D D – D
D D – D
D D D D
D D D D
Count clock
15
15
Figure 10. 8.1 Delay Cycle Insertion in Fine Mode
Seiko epson Corporation
10 Fine MODe 8-BiT TiMeRS (T8F)
underflow number
7 8 9 10 11
– – – – –
– – – – –
– D – – –
– D – – –
– D – – –
– D – – –
– D – – –
– D – D –
– D – D –
– D – D –
D D – D –
D D – D D
D D – D D
D D – D D
D D – D D
D D D D D
D: Indicates the insertion of a delay cycle.
16
16
Delayed
12 13 14 15 16
– – – –
– – – –
– – – –
D – – –
D – – –
D – D –
D – D –
D – D –
D – D –
D – D D
D – D D
D – D D
D – D D
D D D D
D D D D
D D D D
1
1
–
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
10-5