Transmit Cgms/Tsch Indicate Status Register - Fujitsu MB86617A Specification Sheet

LSI S pecification

7.38. Transmit CGMS/TSCH Indicate Status Register

Transmit CGMS/TSCH indicate status register indicates validity of source packet input from TSP IC I/F.
Bit Bit
AD R/W
15 14
84h R/W - -
Initial Value '0' '0'
BIT Bit Name
15 - 11 reserved
10 Act -TSCHB
9 Vld-TSCHB-2
8 Vld-TSCHB-1
7 - 3 reserved
Rev.1.0
Bit Bit Bit Bit
13 12 11 10
act -
vld-T
- - -
TSC
HB HB-2
'0' '0' '0' '0'
Action Value
Read - Always indicate '0'.
Write - Always write in '0'.
Indicates that the packet indicated in CGMSB-1 and TSCHB-1 (82h- bit7 to 0) was
0
finally input from port B at TSP IC I/F.
Read
Indicates that the packet indicated in CGMSB-2 and TSCHB-2 (82h- bit15 to 8)
1
was finally input from port B at TSP IC I/F.
Write - Clears to '0' by writing "1".
Indicates that the value indicated in CGMSB-2 and TSCHB-2 (82h - bit15 to 8) is
0
invalid.
Read
Indicates that the value indicated in CGMSB-2 and TSCHB-2 (82h - bit15 to 8) is
1
valid.
Write - Clears to '0' by writing "1".
Indicates that the value indicated in CGMSB -1 and TSCHB-1 (82h-bit7 to 0) is
0
invalid.
Read
Indicates that the value indicated in CGMSB -1 and TSCHB-1 (82h-bit7 to 0) is
1
valid.
Write - Clears to '0' by writing "1".
Read - Always indicate '0'.
Write - Always write in '0'.
Bit Bit Bit Bit
9 8 7 6
vld-T
- -
SC SC
HB-1
'0' '0' '0' '0'
Function
76
MB86617A
Bit Bit Bit Bit
5 4 3 2
act -
vld-T
- - -
TSC
HA HA-2
'0' '0' '0' '0'
Fujitsu VLSI
Bit Bit
1 0
vld-T
SC SC
HA-1
'0' '0'