Synchronous Eceive Fifo Extended Ode; Eceive Fifo E Xtended M Ode - Fujitsu MB86617A Specification Sheet

LSI S pecification
< Asynchronous Receive FIFO Extended Mode
<
FIFO
(2KByte)
FIFO
(2KByte)
Rev.1.0
Asynch Transmit
Exclusive FIFO
(256 byte)
Asynch Transmit
Packet Process
Asynch Transmit
Packet Process
Asynch Transmit
Exclusive FIFO
(256 byte)
(2KByte
CP IC
(2KByte)
Interface
Fig.3.1.3 Block Diagram - Asynchronous Receive FIFO Extended Mode -
PHY/
LINK
Layer
FIFO
Control
)
Circuit
FIFO
6
MB86617A
TPA0
XTPA0
TPB0
XTPB0
TPBIAS0
TPA1
XTPA1
TPB1
XTPB1
TPBIAS1
TPA2
XTPA2
TPB2
XTPB2
TPBIAS2
Fujitsu VLSI