Table Of Contents - Fujitsu MB86617A Specification Sheet

LSI Specification
CHAPTER 1 OVERVIEW ............................................................................................................................................................................1
CHAPTER 2 FEATURES ..............................................................................................................................................................................2
CHAPTER 3 CHIP BLOCK .........................................................................................................................................................................3
..................................................................................................................................................................................4
3.1. B D
LOCK IAGRAM
<N
O M
ORMAL PERATION
<A T
SYNCHRONOUS RANSMIT
<A R
SYNCHRONOUS ECEIVE
3.2. F E B
UNCTION OF ACH
<PHY L C
AYER ONTROL
<LINK L C
AYER ONTROL
<TSP IC I .................................................................................................................................................................................... 7
NTERFACE
<CP IC I ......................................................................................................................................................................................7
NTERFACE
<D B .............................................................................................................................................................................................7
ATA RIDGE
CHAPTER 4 PIN ASSIGN MENT............................................................................................................................................................... 8
..................................................................................................................................................................................... 9
4.1. P IN A SSIGNMENT
4.2.C T
ORRESPONDING ABLE OF
4.3. O D
UTLINE RAWING OF
CHAPTER 5 PIN FUNCTION ................................................................................................................................................................... 12
5.1. IEEE1394 I
NTERFACE
5.2. I I
SOCHRONOUS NTERFACE
.................................................................................................................................................................................... 16
5.4. MPU I
NTERFACE
............................................................................................................................................................................................ 17
5.5. O P
THER INS
................................................................................................................................................................................... 18
5.6. P /GND P
OWER IN
CHAPTER 6 INTERNAL REGISTER .................................................................................................................................................... 19
CHAPTER 7 INTERNAL REGISTER FUNCT ION DESCRIPTION ........................................................................................... 25
7.1. M - R
ODE CONTROL EGISTER
7.2. & R
FLAG STATUS EGISTER
Rev.1.0
......................................................................................................................................................................4
ODE
FIFO E M
XTENDED ODE
FIFO E M
XTENDED ODE
...................................................................................................................................................................7
LOCK
C .............................................................................................................................................................7
IRCUIT
C ........................................................................................................................................................... 7
IRCUIT
..................................................................................................................................... 10
MB86617A P
IN
........................................................................................................................................................ 11
P
ACKAGE
........................................................................................................................................................................... 13
.................................................................................................................................................................... 14
.................................................................................................................................................................. 27
.................................................................................................................................................................... 29
Contents
......................................................................................................................5
.......................................................................................................................... 6
ii
MB86617A
Fujitsu VLSI