Motorola MCS 2000 Service Instructions Manual page 96

7-14
U0103-30 is the high reference voltage for the A/D ports on the µP. Resistor R0112 and capacitor
C0104 filter the +5 V reference. If this voltage is lower than +5 V the A/D readings will be incorrect.
Likewise U0103-29 is the low reference for the A/D ports. This line is normally tied to ground. If this
line is not connected to ground, the A/D readings will be incorrect.
Capacitor C0105 serves to filter out any AC noise which may ride on +5V at U0103.
Support Logic IC (SLIC)
The SLIC (U0104) provides 3 primary functions, I/O port expansion, memory address expansion,
and some signalling decoding.
There are 32 I/O lines within the SLIC which are under µP control. They are grouped in 4 blocks of 8
and labelled as SLIC ports H, J, K, and L. Ports J, K, and L each have a DDR memory register and a
"value" register. Port H only has a "value" register. These ports are accessed by the µP by placing
the correct address for the I/O registers on the address bus and either reading or writing the data on
the data bus. Changing bits in the DDR registers configures specific port bits to be either input
sensors or output drivers. The "value" registers either report the state of the sensed input or provide
the logic level to be driven on a line configured as an output.
Since the 68HC11F1 only has 16 address lines (A0-A15), it can only directly address 64
Kbytes(=2^16) of external memory. The radio architecture is designed to accommodate over 2
Mbytes of memory. The SLIC contains logic which allows addressing of the memory which would
otherwise be unavailable to the µP on its own. The SLIC monitors address lines A0, A1, A2, A3, A4,
A14, and A15. Depending on what combinations appear on those lines, the SLIC may or may not
assist the µP with addressing. When the µP is addressing a device on its own then address lines A0-
A15 are used and valid. If instead the SLIC is assisting with the addressing then address lines A0-
A13 from the µP are valid, but the upper order address lines A14 OUT, A15 OUT, A16, A17, A18, and
if necessary A19 are provided from the SLIC. There is no conflict with A14 and A14 OUT or with A15
and A15 OUT. Notice for example that SRAM U0101 uses A14 meaning that line is always provided
from the µP directly. Notice also that EEPROM U0100 and FLASH ROM U0102 use A14 OUT,
meaning that their address lines come from the SLIC. On the SLIC itself, line A14 going to A14IN
and A15 going to A15IN are address input lines TO the SLIC. Whereas A14 OUT and A15 OUT are
address output lines FROM the SLIC.
The SLIC also generates chip select signals UV CS for U0102 and EE CS for U0101, as well as
memory timing signals MEMRWB and OE.
The circuitry in the SLIC is reset when either the RESET IN (U0104-A8) is a logic 1, or RESET*
(U0104-E4) is a logic 0, or PWR RST is a logic 0. These lines must be in the opposite logic state for
the SLIC to function normally.
The SLIC supports hardware signalling decoding for certain signalling standards such as MPT 1327
and Trunking (OSW). There are different versions of SLIC each having a different decoder. Currently
there are no SLIC devices which have more than 1 decoder.
The incoming data received by the radio and filtered by the ASFIC exits the ASFIC at U0200-G4 RX
DATA, and enters the SLIC at U0104-B6. Based on the data the SLIC updates internal status
registers which the µP can read using the address and data bus, and act upon it.
Notice that RX data also goes to U0103-77. This implies that the radio can be configured to perform
software decoding if desired, even if the radio has a SLIC with a hardware decoder in it.
Capacitor C0108 serves to filter out any AC noise which may ride on +5V at U0104.
FLASH Electrically Erasable Programmable Memory (FLASH EEPROM)
FLASH Electrically Erasable Programmable Memory (FLASH EEPROM).
December 6, 2004
Controller Section Theory of Operation: MicroprocessorOperation
68P81083C20-D