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Chapter 1
Overview
This chapter gives an overview of the MPC180E security processor, including the key
features, typical system architecture, and MPC180E architecture.
1.1 Features
The MPC180E is designed to work with Motorola's PowerQUICC™ family of processors.
The MPC180E interfaces gluelessly to both the PowerQUICC and PowerQUICC II™,
accelerating the performance of computationally-intensive security functions, such as key
generation and exchange, authentication, and bulk encryption. Support for 66MHz bus
frequencies enables maximum utilization of the MPC8260 local bus as well as enhanced
versions of the MPC8xx system bus.
The MPC180E is optimized to quickly process all the algorithms associated with IPSec,
WTLS/WAP, SSL/TLS, and IKE, including RSA, RSA signature, Diffie-Hellman, Elliptic
Curve Cryptography, DES, 3DES, SHA-1, MD4, MD5, and Arc Four.
Major features of MPC180E are as follows:
• Public key/ asymmetric key
— RSA
– Programmable field size of up to 2048 bits
• Elliptic curve cryptography
— F
m and F(p) modes
2
— Programmable field size of up to 511 bits
• Symmetric key
— DES
– ECB (Electronic Code Book)
– CBC (Cipher Block Chaining)
— 3DES
– Two-key (K1 = K3) or three-key (K1≠ K3) Triple-DES.
— Arc Four Stream Cipher
– key lengths of 40–128 bits
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Chapter 1. Overview
1-1
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