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9.7 Exception Timing
An interrupt occurs when MPC180E asserts IRQ, indicating to the microprocessor that an
event worth monitoring has happened. After the interrupt is received and processed by the
microprocessor, the processor may read CSTAT to determine which execution unit caused
the interrupt.
Figure 9-1 shows the timing for a typical interrupt cycle.
is asserted by the rising edge of MCLK.
The RESET input must be stable on the falling edge of MCLK to guarantee its recognition
in that cycle; otherwise, it is recognized in the following cycle. After RESET is negated, the
processor needs to guarantee at least four idle cycles before accessing the MPC180E.
MCLK
IRQ
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
)
)
(
(
)
)
(
(
Interrupt read and cleared
Figure 9-1. Exception Cycle Timing
Chapter 9. Hardware Parameters
Exception Timing
9-5
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