Dvio Board: Fifo & Control; Clock - Philips DVDR880/001 Service Manual

Circuit Diagrams and PWB Layouts
DVIO Board: Fifo & Control
1 2 3
FIFO & CONTROL
4302
A
5303 F312
+3V3_FPGA_CONF
+3V3
100MHZ
+3V3_FPGA_CONF
7309
XC18V01
F324
1 20
1 20
2 19
2 19
3 18
3 18
B
F316 F326
4 17
TDI
4 17
F319
5 16
TMS
5 16
F322
6 15
TCK
6 15
7 14
7 14
8 13
8 13 CONFIG FLASH
9 12
9 12
10
11
10 11
C
{DATA,CCLK,DONE,INITn,PROGRAMn}
+3V3_FPGA_CONF
2319
D
100n
2318
100n
7300
XC17S30XL 8 7
VCC
4 CE_
3 RESET|OE_
2 CLK
ADDR
E
COUNTER
EPROM
DATA 1
CONFIG ROM
CELL
MATRIX
GND NC
5 6
F
5301 F317 2305
+3V3_PLL
100MHZ
100n
7308
CY2071AS 7
VDD
OSC PLL
3 XTI
CLOCKGENVID BLOCK
F329 3317 F305
4 XTO CLKA 1
EPROM
F321 3318 F307
CLKB 5
8 OE|FS
+3V3 F323 3319 F308
CLKC 6
G
33R 33R 33R
GND
2
PLL VIDEO
{LINK_CYCLEOUT,LINK_AVCLK,LINK_AVSYNC,LINK_AVVALID,LINK_AVFSYNC,LINK_AVERR1,LINK_AVERR0,LINK_CSn,LINK_INTn,LINK_AVREADY}
H
LINKFIFO_DQ(0:7)
{SRAMCE0n,SRAMRDn,PINT0n,PINT1n,PALE,PWRn,PRDn,PRSTn}
PA(8:15)
PAD(7:0)
6300
LD1117
I
3
+5V IN OUT
GND
1
1 2 3
DVDR880-890 /0X1
4 5 6 7
2330
100n
2331
100n
2332
100n
+3V3_PLL
7307
CY2071AS
CLOCKGENAUD OSC
XTI
OPTION
3
4 XTO
EPROM
8 OE|FS
PLL AUDIO
F303
3315
33R
TDO
F309 3331
AUD SDO DAC
AUD BCLK 3321
AUD_WS_OUT
3325
3320
CLOCKGENAUD
SRAMCE0n
SRAMRDn
PWRn
PRDn
PA(15)
PA(14)
PA(13)
PA(12)
PA(11)
F328
4301 PA(10)
+3V3_FPGA
PA(9)
PA(8)
+5V_PROC
PRSTn
100n
7304
FXO-31FT 4 2303
VDD
3312 F300
1 3
TS OUT CLK27M_OSC
OSC
10R
GND
2
PINT0n
PINT1n
PALE
CLK27M
CLK27M_DV
CLK27M_CON
F325
2
+3V3_PLL
4 5 6 7
7. EN 121
8 9 10
{DV_LCn,DV_ERRn,DV_DRQn,DV_DTACKn,DV_ASn,DV_PDn,DV_DSUn,DV_RWn,DV_VS,DV_HS_IN,DV_RSTn,DV_HS_OUT,DV_DSLn}
3301
1K
5300 F314 2304
100MHZ
100n
7
VDD
PLL
BLOCK
F315
CLKA 1
CLKB 5
CLKC 6
GND
2 7303
XCS30XL
109
O TDO
110
F310 GND13
111
I|O85 I|O56 GCK4
47R 112
I|O86 GCK7
113
I|O87
47R F330 114
I|O88
47R F304
115
I|O89 CS1
47R 116
I|O90
117
I|O91
118
GND14
119
I|O92
120
I|O93
121
I|O94
122
I|O95
123
I|O96
124
I|O97
125 FPGA / EPLD
I|O98
126
I|O99
127
GND15
128
VCC7 I O42 INIT
129
I|O100
130
I|O101
131
I|O102
PAD(7) 132
I|O103
PAD(6)
133
I|O104
PAD(5)
134
PAD(4) I|O105
135
I|O106
PAD(3)
136
I|O107
137
GND16 I|O34 LDC
PAD(2)
138
I|O108
PAD(1)
139
I|O109
PAD(0)
140
I|O110
141
I|O111 I O30 HDC
142
I|O112 I|O29 GCK3
143
I|O113 GCK8 PWRDWN
144
VCC8
+3V3_FPGA
+3V3
F318 3313
10K
F320 3314
10K
5302 F311
+3V3 +3V3_FPGA
100MHZ
8 9 10
11 12 13 14
{TDI,TCK,TDO,TDO CONF,TMS}
+3V3_FPGA
72 DONE
DONE
71
GND9
FIFOA_A(0)
70
FIFOA_A(16) +3V3_FPGA
69
I|O55 FIFOA_A(1)
68
I|O54
FIFOA_A(15)
67
I|O53 FIFOA_A(2)
66
I|O52
FIFOA_A(14)
65
I|O51
64
GND8 FIFOA_A(3)
63
I|O50
FIFOA_A(13)
62
I|O49
61
FIFOA_OEn
I|O48 FIFOA_D(0)
60
I|O47
FIFOA_D(7)
59
I|O46 FIFOA_D(1)
58
I|O45 FIFOA_D(6)
57
I|O44
FIFOA_D(2)
56
I|O43
55
GND7
54 INITn
+3V3_FPGA
VCC3
FIFOA_D(7:0)
53
FIFOA D(5)
52
I|O41
51 FIFOA D(3)
I|O40 +3V3_SRAM
FIFOA_D(4)
50
I|O39 8 24
49 FIFOA_WEn
7301
I|O38
FIFOA_A(12)
48 VCC
CY7C1019BV33-10VC
I|O37 FIFOA_A(4)
47
I|O36 FIFOA_A(11) 5
46
CE_ WE_
I|O35
45
SRAM
GND6 FIFOA_A(5)
44
OE_
FIFOA_A(10)
43
I|O33
FIFOA_A(6)
42
I|O32 FIFOA_A(9)
41
I|O31
FIFOA_A(7)
40
FIFOA_A(8) FIFOA_A(0)
1
39
A0
38
FIFOA_A(1)
2
37
+3V3_FPGA A1
VCC2
FIFOA_A(2)
3
A2
FIFOA_A(16:0) FIFOA_A(3)
4
A3 I|O7
FIFOA_A(4)
13
A4 I|O6
FIFOA_A(5)
14
A5 I|O5
FIFOA_A(6)
15
A6 I|O4
FIFOA_A(7)
16
A7 I|O3
FIFOA_A(8)
17
A8 I|O2
FIFOA_A(9)
18
A9 I|O1
FIFOA_A(10)
19
A10 I|O0
FIFOA_A(11)
20
A11
FIFOA_A(12)
21
A12
FIFOA_A(13)
29
A13
FIFOA_A(14) 30
A14
FIFOA_A(15)
31
A15
FIFOA_A(16)
32
A16
GND
9 25
{AUD_BCLK,AUD_WS_OUT,AUD_WS_701,AUD_MUTE,AUD_SDI,AUD_SDO_DAC,AUD_SDO_CON}
5304 F313
+3V3 +3V3_SRAM
100MHZ
CL 16532145_016.eps
11 12 13 14
2301 I3 F330 D7
2302 I4 F331 C8
2303 F4 F332 C8
2304 C8 F333 E12
2305 F3 F335 B10
2306 I9 F336 B8
HAD(7:0)
2307 I9
A
2308 I9
2309 I9
2310 I9
2311 I10
2312 I10
2313 I10
2314 I8
2318 D3
2319 D3
2324 I12
B
2325 I12
2330 A4
2331 B4
2332 B4
3300 G9
3301 B11
3303 E12
3305 B1
3306 B1
C
3307 C1
3312 F5
3313 H9
3314 H9
3315 D7
3317 G3
3318 G3
3319 G3
3320 D7
D
3321 D7
3322 C10
3325 D7
3327 C9
3328 G10
3329 G11
3330 C8
3331 D7
4300 B1
E
4301 E4
4302 A2
5300 C7
5301 F2
5302 I8
5303 A1
5304 I12
6300 I3
12
7300 D2
FIFOA_WEn
F
7301 F13
28
FIFOA_OEn
7303 D10
7304 F4
7307 C7
7308 F2
7309 A2
F300 F5
FIFOA_D(7) F301 C8
27
F302 C8
FIFOA_D(6)
26
G
F303 D7
23 FIFOA_D(5)
F304 D7
FIFOA_D(4)
22 F305 G3
FIFOA_D(3) F306 C10
11
F307 G3
10 FIFOA_D(2)
F308 G3
7 FIFOA_D(1)
F309 D7
6 FIFOA_D(0)
F310 D7
F311 I10
H
F312 A2
F313 I12
F314 C7
F315 C8
F316 B2
F317 F2
F318 H9
F319 B2
F320 H9
F321 G3
I F322 B2
F323 G3
F324 B2
F325 I4
F326 B3
F328 E4
221101 F329 G3